src/dev/x86/intdev.hh

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2008 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Gabe Black
  41  */
  42
  43 #ifndef __DEV_X86_INTDEV_HH__
  44 #define __DEV_X86_INTDEV_HH__
  45
  46 #include <cassert>
  47 #include <string>
  48
  49 #include "mem/tport.hh"
  50 #include "sim/sim_object.hh"
  51
  52 namespace X86ISA
  53 {
  54
  55 template <class Device>
  56 class IntSlavePort : public SimpleTimingPort
  57 {
  58     Device * device;
  59
  60   public:
  61     IntSlavePort(const std::string& _name, SimObject* _parent,
  62                  Device* dev) :
  63         SimpleTimingPort(_name, _parent), device(dev)
  64     {
  65     }
  66
  67     AddrRangeList
  68     getAddrRanges() const
  69     {
  70         return device->getIntAddrRange();
  71     }
  72
  73     Tick
  74     recvAtomic(PacketPtr pkt)
  75     {
  76         panic_if(pkt->cmd != MemCmd::WriteReq,
  77                 "%s received unexpected command %s from %s.\n",
  78                 name(), pkt->cmd.toString(), getPeer());
  79         pkt->headerDelay = pkt->payloadDelay = 0;
  80         return device->recvMessage(pkt);
  81     }
  82 };
  83
  84 template<class T>
  85 PacketPtr
  86 buildIntPacket(Addr addr, T payload)
  87 {
  88     RequestPtr req = std::make_shared<Request>(
  89         addr, sizeof(T), Request::UNCACHEABLE, Request::intMasterId);
  90     PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
  91     pkt->allocate();
  92     pkt->setRaw<T>(payload);
  93     return pkt;
  94 }
  95
  96 template <class Device>
  97 class IntMasterPort : public QueuedMasterPort
  98 {
  99     ReqPacketQueue reqQueue;
 100     SnoopRespPacketQueue snoopRespQueue;
 101
 102     Device* device;
 103     Tick latency;
 104
 105   public:
 106     IntMasterPort(const std::string& _name, SimObject* _parent,
 107                   Device* dev, Tick _latency) :
 108         QueuedMasterPort(_name, _parent, reqQueue, snoopRespQueue),
 109         reqQueue(*_parent, *this), snoopRespQueue(*_parent, *this),
 110         device(dev), latency(_latency)
 111     {
 112     }
 113
 114     bool
 115     recvTimingResp(PacketPtr pkt) override
 116     {
 117         return device->recvResponse(pkt);
 118     }
 119
 120     void
 121     sendMessage(PacketPtr pkt, bool timing)
 122     {
 123         if (timing) {
 124             schedTimingReq(pkt, curTick() + latency);
 125             // The target handles cleaning up the packet in timing mode.
 126         } else {
 127             // ignore the latency involved in the atomic transaction
 128             sendAtomic(pkt);
 129             assert(pkt->isResponse());
 130             // also ignore the latency in handling the response
 131             device->recvResponse(pkt);
 132         }
 133     }
 134 };
 135
 136 } // namespace X86ISA
 137
 138 #endif //__DEV_X86_INTDEV_HH__