src/dev/x86/intdev.hh

   1 /*
   2  * Copyright (c) 2008 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #ifndef __DEV_X86_INTDEV_HH__
  32 #define __DEV_X86_INTDEV_HH__
  33
  34 #include <cassert>
  35 #include <list>
  36 #include <string>
  37
  38 #include "arch/x86/intmessage.hh"
  39 #include "arch/x86/x86_traits.hh"
  40 #include "mem/mem_object.hh"
  41 #include "mem/mport.hh"
  42 #include "params/X86IntLine.hh"
  43 #include "params/X86IntSinkPin.hh"
  44 #include "params/X86IntSourcePin.hh"
  45 #include "sim/sim_object.hh"
  46
  47 namespace X86ISA {
  48
  49 typedef std::list<int> ApicList;
  50
  51 class IntDev
  52 {
  53   protected:
  54     class IntPort : public MessagePort
  55     {
  56         IntDev * device;
  57         Tick latency;
  58         Addr intAddr;
  59       public:
  60         IntPort(const std::string &_name, MemObject * _parent,
  61                 IntDev *dev, Tick _latency) :
  62             MessagePort(_name, _parent), device(dev), latency(_latency)
  63         {
  64         }
  65
  66         AddrRangeList getAddrRanges()
  67         {
  68             return device->getIntAddrRange();
  69         }
  70
  71         Tick recvMessage(PacketPtr pkt)
  72         {
  73             return device->recvMessage(pkt);
  74         }
  75
  76         Tick recvResponse(PacketPtr pkt)
  77         {
  78             return device->recvResponse(pkt);
  79         }
  80
  81         // This is x86 focused, so if this class becomes generic, this would
  82         // need to be moved into a subclass.
  83         void sendMessage(ApicList apics,
  84                 TriggerIntMessage message, bool timing);
  85     };
  86
  87     IntPort intPort;
  88
  89   public:
  90     IntDev(MemObject * parent, Tick latency = 0) :
  91         intPort(parent->name() + ".int_master", parent, this, latency)
  92     {
  93     }
  94
  95     virtual ~IntDev()
  96     {}
  97
  98     virtual void init();
  99
 100     virtual void
 101     signalInterrupt(int line)
 102     {
 103         panic("signalInterrupt not implemented.\n");
 104     }
 105
 106     virtual void
 107     raiseInterruptPin(int number)
 108     {
 109         panic("raiseInterruptPin not implemented.\n");
 110     }
 111
 112     virtual void
 113     lowerInterruptPin(int number)
 114     {
 115         panic("lowerInterruptPin not implemented.\n");
 116     }
 117
 118     virtual Tick
 119     recvMessage(PacketPtr pkt)
 120     {
 121         panic("recvMessage not implemented.\n");
 122         return 0;
 123     }
 124
 125     virtual Tick
 126     recvResponse(PacketPtr pkt)
 127     {
 128         return 0;
 129     }
 130
 131     virtual AddrRangeList
 132     getIntAddrRange()
 133     {
 134         panic("intAddrRange not implemented.\n");
 135     }
 136 };
 137
 138 class IntSinkPin : public SimObject
 139 {
 140   public:
 141     IntDev * device;
 142     int number;
 143
 144     typedef X86IntSinkPinParams Params;
 145
 146     const Params *
 147     params() const
 148     {
 149         return dynamic_cast<const Params *>(_params);
 150     }
 151
 152     IntSinkPin(Params *p) : SimObject(p),
 153             device(dynamic_cast<IntDev *>(p->device)), number(p->number)
 154     {
 155         assert(device);
 156     }
 157 };
 158
 159 class IntSourcePin : public SimObject
 160 {
 161   protected:
 162     std::vector<IntSinkPin *> sinks;
 163
 164   public:
 165     typedef X86IntSourcePinParams Params;
 166
 167     const Params *
 168     params() const
 169     {
 170         return dynamic_cast<const Params *>(_params);
 171     }
 172
 173     void
 174     addSink(IntSinkPin *sink)
 175     {
 176         sinks.push_back(sink);
 177     }
 178
 179     void
 180     raise()
 181     {
 182         for (int i = 0; i < sinks.size(); i++) {
 183             const IntSinkPin &pin = *sinks[i];
 184             pin.device->raiseInterruptPin(pin.number);
 185         }
 186     }
 187
 188     void
 189     lower()
 190     {
 191         for (int i = 0; i < sinks.size(); i++) {
 192             const IntSinkPin &pin = *sinks[i];
 193             pin.device->lowerInterruptPin(pin.number);
 194         }
 195     }
 196
 197     IntSourcePin(Params *p) : SimObject(p)
 198     {}
 199 };
 200
 201 class IntLine : public SimObject
 202 {
 203   protected:
 204     IntSourcePin *source;
 205     IntSinkPin *sink;
 206
 207   public:
 208     typedef X86IntLineParams Params;
 209
 210     const Params *
 211     params() const
 212     {
 213         return dynamic_cast<const Params *>(_params);
 214     }
 215
 216     IntLine(Params *p) : SimObject(p), source(p->source), sink(p->sink)
 217     {
 218         source->addSink(sink);
 219     }
 220 };
 221
 222 } // namespace X86ISA
 223
 224 #endif //__DEV_X86_INTDEV_HH__