src/dev/x86/intdev.hh

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2008 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Gabe Black
  41  */
  42
  43 #ifndef __DEV_X86_INTDEV_HH__
  44 #define __DEV_X86_INTDEV_HH__
  45
  46 #include <cassert>
  47 #include <functional>
  48 #include <string>
  49
  50 #include "mem/tport.hh"
  51 #include "sim/sim_object.hh"
  52
  53 namespace X86ISA
  54 {
  55
  56 template <class Device>
  57 class IntSlavePort : public SimpleTimingPort
  58 {
  59     Device * device;
  60
  61   public:
  62     IntSlavePort(const std::string& _name, SimObject* _parent,
  63                  Device* dev) :
  64         SimpleTimingPort(_name, _parent), device(dev)
  65     {
  66     }
  67
  68     AddrRangeList
  69     getAddrRanges() const
  70     {
  71         return device->getIntAddrRange();
  72     }
  73
  74     Tick
  75     recvAtomic(PacketPtr pkt)
  76     {
  77         panic_if(pkt->cmd != MemCmd::WriteReq,
  78                 "%s received unexpected command %s from %s.\n",
  79                 name(), pkt->cmd.toString(), getPeer());
  80         pkt->headerDelay = pkt->payloadDelay = 0;
  81         return device->recvMessage(pkt);
  82     }
  83 };
  84
  85 template<class T>
  86 PacketPtr
  87 buildIntPacket(Addr addr, T payload)
  88 {
  89     RequestPtr req = std::make_shared<Request>(
  90         addr, sizeof(T), Request::UNCACHEABLE, Request::intMasterId);
  91     PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
  92     pkt->allocate();
  93     pkt->setRaw<T>(payload);
  94     return pkt;
  95 }
  96
  97 template <class Device>
  98 class IntMasterPort : public QueuedMasterPort
  99 {
 100   private:
 101     ReqPacketQueue reqQueue;
 102     SnoopRespPacketQueue snoopRespQueue;
 103
 104     Device* device;
 105     Tick latency;
 106
 107     typedef std::function<void(PacketPtr)> OnCompletionFunc;
 108     OnCompletionFunc onCompletion = nullptr;
 109     // If nothing extra needs to happen, just clean up the packet.
 110     static void defaultOnCompletion(PacketPtr pkt) { delete pkt; }
 111
 112   public:
 113     IntMasterPort(const std::string& _name, SimObject* _parent,
 114                   Device* dev, Tick _latency) :
 115         QueuedMasterPort(_name, _parent, reqQueue, snoopRespQueue),
 116         reqQueue(*_parent, *this), snoopRespQueue(*_parent, *this),
 117         device(dev), latency(_latency)
 118     {
 119     }
 120
 121     bool
 122     recvTimingResp(PacketPtr pkt) override
 123     {
 124         assert(pkt->isResponse());
 125         onCompletion(pkt);
 126         onCompletion = nullptr;
 127         return true;
 128     }
 129
 130     void
 131     sendMessage(PacketPtr pkt, bool timing,
 132             OnCompletionFunc func=defaultOnCompletion)
 133     {
 134         if (timing) {
 135             onCompletion = func;
 136             schedTimingReq(pkt, curTick() + latency);
 137             // The target handles cleaning up the packet in timing mode.
 138         } else {
 139             // ignore the latency involved in the atomic transaction
 140             sendAtomic(pkt);
 141             func(pkt);
 142         }
 143     }
 144 };
 145
 146 } // namespace X86ISA
 147
 148 #endif //__DEV_X86_INTDEV_HH__