src/dev/x86/intdev.hh

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2008 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __DEV_X86_INTDEV_HH__
  42 #define __DEV_X86_INTDEV_HH__
  43
  44 #include <cassert>
  45 #include <functional>
  46 #include <string>
  47
  48 #include "mem/tport.hh"
  49 #include "sim/sim_object.hh"
  50
  51 namespace X86ISA
  52 {
  53
  54 template <class Device>
  55 class IntSlavePort : public SimpleTimingPort
  56 {
  57     Device * device;
  58
  59   public:
  60     IntSlavePort(const std::string& _name, SimObject* _parent,
  61                  Device* dev) :
  62         SimpleTimingPort(_name, _parent), device(dev)
  63     {
  64     }
  65
  66     AddrRangeList
  67     getAddrRanges() const
  68     {
  69         return device->getIntAddrRange();
  70     }
  71
  72     Tick
  73     recvAtomic(PacketPtr pkt)
  74     {
  75         panic_if(pkt->cmd != MemCmd::WriteReq,
  76                 "%s received unexpected command %s from %s.\n",
  77                 name(), pkt->cmd.toString(), getPeer());
  78         pkt->headerDelay = pkt->payloadDelay = 0;
  79         return device->recvMessage(pkt);
  80     }
  81 };
  82
  83 template<class T>
  84 PacketPtr
  85 buildIntPacket(Addr addr, T payload)
  86 {
  87     RequestPtr req = std::make_shared<Request>(
  88         addr, sizeof(T), Request::UNCACHEABLE, Request::intMasterId);
  89     PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
  90     pkt->allocate();
  91     pkt->setRaw<T>(payload);
  92     return pkt;
  93 }
  94
  95 template <class Device>
  96 class IntMasterPort : public QueuedMasterPort
  97 {
  98   private:
  99     ReqPacketQueue reqQueue;
 100     SnoopRespPacketQueue snoopRespQueue;
 101
 102     Device* device;
 103     Tick latency;
 104
 105     typedef std::function<void(PacketPtr)> OnCompletionFunc;
 106     OnCompletionFunc onCompletion = nullptr;
 107     // If nothing extra needs to happen, just clean up the packet.
 108     static void defaultOnCompletion(PacketPtr pkt) { delete pkt; }
 109
 110   public:
 111     IntMasterPort(const std::string& _name, SimObject* _parent,
 112                   Device* dev, Tick _latency) :
 113         QueuedMasterPort(_name, _parent, reqQueue, snoopRespQueue),
 114         reqQueue(*_parent, *this), snoopRespQueue(*_parent, *this),
 115         device(dev), latency(_latency)
 116     {
 117     }
 118
 119     bool
 120     recvTimingResp(PacketPtr pkt) override
 121     {
 122         assert(pkt->isResponse());
 123         onCompletion(pkt);
 124         onCompletion = nullptr;
 125         return true;
 126     }
 127
 128     void
 129     sendMessage(PacketPtr pkt, bool timing,
 130             OnCompletionFunc func=defaultOnCompletion)
 131     {
 132         if (timing) {
 133             onCompletion = func;
 134             schedTimingReq(pkt, curTick() + latency);
 135             // The target handles cleaning up the packet in timing mode.
 136         } else {
 137             // ignore the latency involved in the atomic transaction
 138             sendAtomic(pkt);
 139             func(pkt);
 140         }
 141     }
 142 };
 143
 144 } // namespace X86ISA
 145
 146 #endif //__DEV_X86_INTDEV_HH__