src/dev/x86/pc.cc

   1 /*
   2  * Copyright (c) 2008 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 /** @file
  32  * Implementation of PC platform.
  33  */
  34
  35 #include <deque>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "arch/x86/x86_traits.hh"
  40 #include "cpu/intr_control.hh"
  41 #include "dev/terminal.hh"
  42 #include "dev/x86/i8254.hh"
  43 #include "dev/x86/pc.hh"
  44 #include "dev/x86/south_bridge/south_bridge.hh"
  45 #include "sim/system.hh"
  46
  47 using namespace std;
  48 using namespace TheISA;
  49
  50 PC::PC(const Params *p)
  51     : Platform(p), system(p->system)
  52 {
  53     southBridge = NULL;
  54     // set the back pointer from the system to myself
  55     system->platform = this;
  56 }
  57
  58 void
  59 PC::init()
  60 {
  61     assert(southBridge);
  62     I8254 & timer = *southBridge->pit;
  63     //Timer 0, mode 2, no bcd, 16 bit count
  64     timer.writeControl(0x34);
  65     //Timer 0, latch command
  66     timer.writeControl(0x00);
  67     //Write a 16 bit count of 0
  68     timer.writeCounter(0, 0);
  69     timer.writeCounter(0, 0);
  70 }
  71
  72 Tick
  73 PC::intrFrequency()
  74 {
  75     panic("Need implementation\n");
  76     M5_DUMMY_RETURN
  77 }
  78
  79 void
  80 PC::postConsoleInt()
  81 {
  82     warn_once("Don't know what interrupt to post for console.\n");
  83     //panic("Need implementation\n");
  84 }
  85
  86 void
  87 PC::clearConsoleInt()
  88 {
  89     warn_once("Don't know what interrupt to clear for console.\n");
  90     //panic("Need implementation\n");
  91 }
  92
  93 void
  94 PC::postPciInt(int line)
  95 {
  96     panic("Need implementation\n");
  97 }
  98
  99 void
 100 PC::clearPciInt(int line)
 101 {
 102     panic("Need implementation\n");
 103 }
 104
 105 Addr
 106 PC::pciToDma(Addr pciAddr) const
 107 {
 108     panic("Need implementation\n");
 109     M5_DUMMY_RETURN
 110 }
 111
 112
 113 Addr
 114 PC::calcConfigAddr(int bus, int dev, int func)
 115 {
 116     assert(func < 8);
 117     assert(dev < 32);
 118     assert(bus == 0);
 119     return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
 120 }
 121
 122 PC *
 123 PCParams::create()
 124 {
 125     return new PC(this);
 126 }