src/dev/x86/pc.cc

   1 /*
   2  * Copyright (c) 2008 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Implementation of PC platform.
  31  */
  32
  33 #include "dev/x86/pc.hh"
  34
  35 #include <deque>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "arch/x86/intmessage.hh"
  40 #include "arch/x86/x86_traits.hh"
  41 #include "cpu/intr_control.hh"
  42 #include "dev/x86/i82094aa.hh"
  43 #include "dev/x86/i8254.hh"
  44 #include "dev/x86/i8259.hh"
  45 #include "dev/x86/south_bridge.hh"
  46 #include "sim/system.hh"
  47
  48 Pc::Pc(const Params *p)
  49     : Platform(p), system(p->system)
  50 {
  51     southBridge = NULL;
  52 }
  53
  54 void
  55 Pc::init()
  56 {
  57     assert(southBridge);
  58
  59     /*
  60      * Initialize the timer.
  61      */
  62     auto &timer = *southBridge->pit;
  63     //Timer 0, mode 2, no bcd, 16 bit count
  64     timer.writeControl(0x34);
  65     //Timer 0, latch command
  66     timer.writeControl(0x00);
  67     //Write a 16 bit count of 0
  68     timer.writeCounter(0, 0);
  69     timer.writeCounter(0, 0);
  70
  71     /*
  72      * Initialize the I/O APIC.
  73      */
  74     X86ISA::I82094AA &ioApic = *southBridge->ioApic;
  75     X86ISA::I82094AA::RedirTableEntry entry = 0;
  76     entry.deliveryMode = X86ISA::DeliveryMode::ExtInt;
  77     entry.vector = 0x20;
  78     ioApic.writeReg(0x10, entry.bottomDW);
  79     ioApic.writeReg(0x11, entry.topDW);
  80     entry.deliveryMode = X86ISA::DeliveryMode::Fixed;
  81     entry.vector = 0x24;
  82     ioApic.writeReg(0x18, entry.bottomDW);
  83     ioApic.writeReg(0x19, entry.topDW);
  84     entry.mask = 1;
  85     entry.vector = 0x21;
  86     ioApic.writeReg(0x12, entry.bottomDW);
  87     ioApic.writeReg(0x13, entry.topDW);
  88     entry.vector = 0x20;
  89     ioApic.writeReg(0x14, entry.bottomDW);
  90     ioApic.writeReg(0x15, entry.topDW);
  91     entry.vector = 0x28;
  92     ioApic.writeReg(0x20, entry.bottomDW);
  93     ioApic.writeReg(0x21, entry.topDW);
  94     entry.vector = 0x2C;
  95     ioApic.writeReg(0x28, entry.bottomDW);
  96     ioApic.writeReg(0x29, entry.topDW);
  97     entry.vector = 0x2E;
  98     ioApic.writeReg(0x2C, entry.bottomDW);
  99     ioApic.writeReg(0x2D, entry.topDW);
 100     entry.vector = 0x30;
 101     ioApic.writeReg(0x30, entry.bottomDW);
 102     ioApic.writeReg(0x31, entry.topDW);
 103
 104     /*
 105      * Mask the PICs. I'm presuming the BIOS/bootloader would have cleared
 106      * these out and masked them before passing control to the OS.
 107      */
 108     southBridge->pic1->maskAll();
 109     southBridge->pic2->maskAll();
 110 }
 111
 112 void
 113 Pc::postConsoleInt()
 114 {
 115     southBridge->ioApic->signalInterrupt(4);
 116     southBridge->pic1->signalInterrupt(4);
 117 }
 118
 119 void
 120 Pc::clearConsoleInt()
 121 {
 122     warn_once("Don't know what interrupt to clear for console.\n");
 123     //panic("Need implementation\n");
 124 }
 125
 126 void
 127 Pc::postPciInt(int line)
 128 {
 129     southBridge->ioApic->signalInterrupt(line);
 130 }
 131
 132 void
 133 Pc::clearPciInt(int line)
 134 {
 135     warn_once("Tried to clear PCI interrupt %d\n", line);
 136 }
 137
 138 Pc *
 139 PcParams::create()
 140 {
 141     return new Pc(this);
 142 }