src/dev/x86/pc.cc

   1 /*
   2  * Copyright (c) 2008 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 /** @file
  32  * Implementation of PC platform.
  33  */
  34
  35 #include <deque>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "arch/x86/x86_traits.hh"
  40 #include "dev/intel_8254_timer.hh"
  41 #include "cpu/intr_control.hh"
  42 #include "dev/terminal.hh"
  43 #include "dev/x86/pc.hh"
  44 #include "sim/system.hh"
  45
  46 using namespace std;
  47 using namespace TheISA;
  48
  49 PC::PC(const Params *p)
  50     : Platform(p), system(p->system)
  51 {
  52     southBridge = NULL;
  53     // set the back pointer from the system to myself
  54     system->platform = this;
  55 }
  56
  57 void
  58 PC::init()
  59 {
  60     assert(southBridge);
  61     Intel8254Timer & timer = southBridge->pit.pit;
  62     //Timer 0, mode 2, no bcd, 16 bit count
  63     timer.writeControl(0x34);
  64     //Timer 0, latch command
  65     timer.writeControl(0x00);
  66     //Write a 16 bit count of 0
  67     timer.counter0.write(0);
  68     timer.counter0.write(0);
  69 }
  70
  71 Tick
  72 PC::intrFrequency()
  73 {
  74     panic("Need implementation\n");
  75     M5_DUMMY_RETURN
  76 }
  77
  78 void
  79 PC::postConsoleInt()
  80 {
  81     warn_once("Don't know what interrupt to post for console.\n");
  82     //panic("Need implementation\n");
  83 }
  84
  85 void
  86 PC::clearConsoleInt()
  87 {
  88     warn_once("Don't know what interrupt to clear for console.\n");
  89     //panic("Need implementation\n");
  90 }
  91
  92 void
  93 PC::postPciInt(int line)
  94 {
  95     panic("Need implementation\n");
  96 }
  97
  98 void
  99 PC::clearPciInt(int line)
 100 {
 101     panic("Need implementation\n");
 102 }
 103
 104 Addr
 105 PC::pciToDma(Addr pciAddr) const
 106 {
 107     panic("Need implementation\n");
 108     M5_DUMMY_RETURN
 109 }
 110
 111
 112 Addr
 113 PC::calcConfigAddr(int bus, int dev, int func)
 114 {
 115     assert(func < 8);
 116     assert(dev < 32);
 117     assert(bus == 0);
 118     return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
 119 }
 120
 121 PC *
 122 PCParams::create()
 123 {
 124     return new PC(this);
 125 }