src/dev/x86/pc.cc

   1 /*
   2  * Copyright (c) 2008 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 /** @file
  32  * Implementation of PC platform.
  33  */
  34
  35 #include "dev/x86/pc.hh"
  36
  37 #include <deque>
  38 #include <string>
  39 #include <vector>
  40
  41 #include "arch/x86/intmessage.hh"
  42 #include "arch/x86/x86_traits.hh"
  43 #include "cpu/intr_control.hh"
  44 #include "dev/x86/i82094aa.hh"
  45 #include "dev/x86/i8254.hh"
  46 #include "dev/x86/i8259.hh"
  47 #include "dev/x86/south_bridge.hh"
  48 #include "sim/system.hh"
  49
  50 Pc::Pc(const Params *p)
  51     : Platform(p), system(p->system)
  52 {
  53     southBridge = NULL;
  54 }
  55
  56 void
  57 Pc::init()
  58 {
  59     assert(southBridge);
  60
  61     /*
  62      * Initialize the timer.
  63      */
  64     auto &timer = *southBridge->pit;
  65     //Timer 0, mode 2, no bcd, 16 bit count
  66     timer.writeControl(0x34);
  67     //Timer 0, latch command
  68     timer.writeControl(0x00);
  69     //Write a 16 bit count of 0
  70     timer.writeCounter(0, 0);
  71     timer.writeCounter(0, 0);
  72
  73     /*
  74      * Initialize the I/O APIC.
  75      */
  76     X86ISA::I82094AA &ioApic = *southBridge->ioApic;
  77     X86ISA::I82094AA::RedirTableEntry entry = 0;
  78     entry.deliveryMode = X86ISA::DeliveryMode::ExtInt;
  79     entry.vector = 0x20;
  80     ioApic.writeReg(0x10, entry.bottomDW);
  81     ioApic.writeReg(0x11, entry.topDW);
  82     entry.deliveryMode = X86ISA::DeliveryMode::Fixed;
  83     entry.vector = 0x24;
  84     ioApic.writeReg(0x18, entry.bottomDW);
  85     ioApic.writeReg(0x19, entry.topDW);
  86     entry.mask = 1;
  87     entry.vector = 0x21;
  88     ioApic.writeReg(0x12, entry.bottomDW);
  89     ioApic.writeReg(0x13, entry.topDW);
  90     entry.vector = 0x20;
  91     ioApic.writeReg(0x14, entry.bottomDW);
  92     ioApic.writeReg(0x15, entry.topDW);
  93     entry.vector = 0x28;
  94     ioApic.writeReg(0x20, entry.bottomDW);
  95     ioApic.writeReg(0x21, entry.topDW);
  96     entry.vector = 0x2C;
  97     ioApic.writeReg(0x28, entry.bottomDW);
  98     ioApic.writeReg(0x29, entry.topDW);
  99     entry.vector = 0x2E;
 100     ioApic.writeReg(0x2C, entry.bottomDW);
 101     ioApic.writeReg(0x2D, entry.topDW);
 102     entry.vector = 0x30;
 103     ioApic.writeReg(0x30, entry.bottomDW);
 104     ioApic.writeReg(0x31, entry.topDW);
 105
 106     /*
 107      * Mask the PICs. I'm presuming the BIOS/bootloader would have cleared
 108      * these out and masked them before passing control to the OS.
 109      */
 110     southBridge->pic1->maskAll();
 111     southBridge->pic2->maskAll();
 112 }
 113
 114 void
 115 Pc::postConsoleInt()
 116 {
 117     southBridge->ioApic->signalInterrupt(4);
 118     southBridge->pic1->signalInterrupt(4);
 119 }
 120
 121 void
 122 Pc::clearConsoleInt()
 123 {
 124     warn_once("Don't know what interrupt to clear for console.\n");
 125     //panic("Need implementation\n");
 126 }
 127
 128 void
 129 Pc::postPciInt(int line)
 130 {
 131     southBridge->ioApic->signalInterrupt(line);
 132 }
 133
 134 void
 135 Pc::clearPciInt(int line)
 136 {
 137     warn_once("Tried to clear PCI interrupt %d\n", line);
 138 }
 139
 140 Pc *
 141 PcParams::create()
 142 {
 143     return new Pc(this);
 144 }