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32 * Implementation of PC platform.
39 #include "arch/x86/intmessage.hh"
40 #include "arch/x86/x86_traits.hh"
41 #include "config/the_isa.hh"
42 #include "cpu/intr_control.hh"
43 #include "dev/x86/i82094aa.hh"
44 #include "dev/x86/i8254.hh"
45 #include "dev/x86/i8259.hh"
46 #include "dev/x86/pc.hh"
47 #include "dev/x86/south_bridge.hh"
48 #include "dev/terminal.hh"
49 #include "sim/system.hh"
52 using namespace TheISA
;
54 Pc::Pc(const Params
*p
)
55 : Platform(p
), system(p
->system
)
66 * Initialize the timer.
68 I8254
& timer
= *southBridge
->pit
;
69 //Timer 0, mode 2, no bcd, 16 bit count
70 timer
.writeControl(0x34);
71 //Timer 0, latch command
72 timer
.writeControl(0x00);
73 //Write a 16 bit count of 0
74 timer
.writeCounter(0, 0);
75 timer
.writeCounter(0, 0);
78 * Initialize the I/O APIC.
80 I82094AA
& ioApic
= *southBridge
->ioApic
;
81 I82094AA::RedirTableEntry entry
= 0;
82 entry
.deliveryMode
= DeliveryMode::ExtInt
;
84 ioApic
.writeReg(0x10, entry
.bottomDW
);
85 ioApic
.writeReg(0x11, entry
.topDW
);
86 entry
.deliveryMode
= DeliveryMode::Fixed
;
88 ioApic
.writeReg(0x18, entry
.bottomDW
);
89 ioApic
.writeReg(0x19, entry
.topDW
);
92 ioApic
.writeReg(0x12, entry
.bottomDW
);
93 ioApic
.writeReg(0x13, entry
.topDW
);
95 ioApic
.writeReg(0x14, entry
.bottomDW
);
96 ioApic
.writeReg(0x15, entry
.topDW
);
98 ioApic
.writeReg(0x20, entry
.bottomDW
);
99 ioApic
.writeReg(0x21, entry
.topDW
);
101 ioApic
.writeReg(0x28, entry
.bottomDW
);
102 ioApic
.writeReg(0x29, entry
.topDW
);
104 ioApic
.writeReg(0x2C, entry
.bottomDW
);
105 ioApic
.writeReg(0x2D, entry
.topDW
);
107 ioApic
.writeReg(0x30, entry
.bottomDW
);
108 ioApic
.writeReg(0x31, entry
.topDW
);
111 * Mask the PICs. I'm presuming the BIOS/bootloader would have cleared
112 * these out and masked them before passing control to the OS.
114 southBridge
->pic1
->maskAll();
115 southBridge
->pic2
->maskAll();
121 southBridge
->ioApic
->signalInterrupt(4);
122 southBridge
->pic1
->signalInterrupt(4);
126 Pc::clearConsoleInt()
128 warn_once("Don't know what interrupt to clear for console.\n");
129 //panic("Need implementation\n");
133 Pc::postPciInt(int line
)
135 southBridge
->ioApic
->signalInterrupt(line
);
139 Pc::clearPciInt(int line
)
141 warn_once("Tried to clear PCI interrupt %d\n", line
);