src/dev/x86/pc.cc

   1 /*
   2  * Copyright (c) 2008 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 /** @file
  32  * Implementation of PC platform.
  33  */
  34
  35 #include <deque>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "arch/x86/intmessage.hh"
  40 #include "arch/x86/x86_traits.hh"
  41 #include "cpu/intr_control.hh"
  42 #include "dev/terminal.hh"
  43 #include "dev/x86/i82094aa.hh"
  44 #include "dev/x86/i8254.hh"
  45 #include "dev/x86/i8259.hh"
  46 #include "dev/x86/pc.hh"
  47 #include "dev/x86/south_bridge.hh"
  48 #include "sim/system.hh"
  49
  50 using namespace std;
  51 using namespace TheISA;
  52
  53 Pc::Pc(const Params *p)
  54     : Platform(p), system(p->system)
  55 {
  56     southBridge = NULL;
  57     // set the back pointer from the system to myself
  58     system->platform = this;
  59 }
  60
  61 void
  62 Pc::init()
  63 {
  64     assert(southBridge);
  65
  66     /*
  67      * Initialize the timer.
  68      */
  69     I8254 & timer = *southBridge->pit;
  70     //Timer 0, mode 2, no bcd, 16 bit count
  71     timer.writeControl(0x34);
  72     //Timer 0, latch command
  73     timer.writeControl(0x00);
  74     //Write a 16 bit count of 0
  75     timer.writeCounter(0, 0);
  76     timer.writeCounter(0, 0);
  77
  78     /*
  79      * Initialize the I/O APIC.
  80      */
  81     I82094AA & ioApic = *southBridge->ioApic;
  82     I82094AA::RedirTableEntry entry = 0;
  83     entry.deliveryMode = DeliveryMode::ExtInt;
  84     entry.vector = 0x20;
  85     ioApic.writeReg(0x10, entry.bottomDW);
  86     ioApic.writeReg(0x11, entry.topDW);
  87     entry.deliveryMode = DeliveryMode::Fixed;
  88     entry.vector = 0x24;
  89     ioApic.writeReg(0x18, entry.bottomDW);
  90     ioApic.writeReg(0x19, entry.topDW);
  91     entry.mask = 1;
  92     entry.vector = 0x21;
  93     ioApic.writeReg(0x12, entry.bottomDW);
  94     ioApic.writeReg(0x13, entry.topDW);
  95     entry.vector = 0x20;
  96     ioApic.writeReg(0x14, entry.bottomDW);
  97     ioApic.writeReg(0x15, entry.topDW);
  98     entry.vector = 0x28;
  99     ioApic.writeReg(0x20, entry.bottomDW);
 100     ioApic.writeReg(0x21, entry.topDW);
 101     entry.vector = 0x2C;
 102     ioApic.writeReg(0x28, entry.bottomDW);
 103     ioApic.writeReg(0x29, entry.topDW);
 104     entry.vector = 0x2E;
 105     ioApic.writeReg(0x2C, entry.bottomDW);
 106     ioApic.writeReg(0x2D, entry.topDW);
 107     entry.vector = 0x30;
 108     ioApic.writeReg(0x30, entry.bottomDW);
 109     ioApic.writeReg(0x31, entry.topDW);
 110 }
 111
 112 Tick
 113 Pc::intrFrequency()
 114 {
 115     panic("Need implementation for intrFrequency\n");
 116     M5_DUMMY_RETURN
 117 }
 118
 119 void
 120 Pc::postConsoleInt()
 121 {
 122     southBridge->ioApic->signalInterrupt(4);
 123     southBridge->pic1->signalInterrupt(4);
 124 }
 125
 126 void
 127 Pc::clearConsoleInt()
 128 {
 129     warn_once("Don't know what interrupt to clear for console.\n");
 130     //panic("Need implementation\n");
 131 }
 132
 133 void
 134 Pc::postPciInt(int line)
 135 {
 136     southBridge->ioApic->signalInterrupt(line);
 137 }
 138
 139 void
 140 Pc::clearPciInt(int line)
 141 {
 142     warn_once("Tried to clear PCI interrupt %d\n", line);
 143 }
 144
 145 Addr
 146 Pc::pciToDma(Addr pciAddr) const
 147 {
 148     return pciAddr;
 149 }
 150
 151 Addr
 152 Pc::calcPciConfigAddr(int bus, int dev, int func)
 153 {
 154     assert(func < 8);
 155     assert(dev < 32);
 156     assert(bus == 0);
 157     return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
 158 }
 159
 160 Addr
 161 Pc::calcPciIOAddr(Addr addr)
 162 {
 163     return PhysAddrPrefixIO + addr;
 164 }
 165
 166 Addr
 167 Pc::calcPciMemAddr(Addr addr)
 168 {
 169     return addr;
 170 }
 171
 172 Pc *
 173 PcParams::create()
 174 {
 175     return new Pc(this);
 176 }