X86: Start implementing the south bridge stuff.
[gem5.git] / src / dev / x86 / south_bridge / cmos.cc
1 /*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31 #include "dev/x86/south_bridge/cmos.hh"
32 #include "mem/packet_access.hh"
33
34 Tick
35 X86ISA::Cmos::read(PacketPtr pkt)
36 {
37 assert(pkt->getSize() == 1);
38 switch(pkt->getAddr() - addrRange.start)
39 {
40 case 0x0:
41 pkt->set(address);
42 break;
43 case 0x1:
44 pkt->set(readRegister(address));
45 break;
46 default:
47 panic("Read from undefined CMOS port.\n");
48 }
49 return latency;
50 }
51
52 Tick
53 X86ISA::Cmos::write(PacketPtr pkt)
54 {
55 assert(pkt->getSize() == 1);
56 switch(pkt->getAddr() - addrRange.start)
57 {
58 case 0x0:
59 address = pkt->get<uint8_t>();
60 break;
61 case 0x1:
62 writeRegister(address, pkt->get<uint8_t>());
63 break;
64 default:
65 panic("Write to undefined CMOS port.\n");
66 }
67 return latency;
68 }
69
70 uint8_t
71 X86ISA::Cmos::readRegister(uint8_t reg)
72 {
73 assert(reg < numRegs);
74 switch(reg)
75 {
76 case 0x0:
77 case 0x1:
78 case 0x2:
79 case 0x3:
80 case 0x4:
81 case 0x5:
82 case 0x6:
83 case 0x7:
84 case 0x8:
85 case 0x9:
86 case 0xA:
87 case 0xB:
88 case 0xC:
89 case 0xD:
90 warn("Reading RTC in the CMOS.\n");
91 break;
92 default:
93 warn("Reading non-volitile CMOS address %x as %x.\n", reg, regs[reg]);
94 break;
95 }
96 return regs[reg];
97 }
98
99 void
100 X86ISA::Cmos::writeRegister(uint8_t reg, uint8_t val)
101 {
102 assert(reg < numRegs);
103 switch(reg)
104 {
105 case 0x0:
106 case 0x1:
107 case 0x2:
108 case 0x3:
109 case 0x4:
110 case 0x5:
111 case 0x6:
112 case 0x7:
113 case 0x8:
114 case 0x9:
115 case 0xA:
116 case 0xB:
117 case 0xC:
118 case 0xD:
119 warn("Writing RTC in the CMOS.\n");
120 break;
121 default:
122 warn("Writing non-volitile CMOS address %x with %x.\n", reg, val);
123 break;
124 }
125 regs[reg] = val;
126 }