src/egl/drivers/dri2/platform_drm.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT.  IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  19  * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  20  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Kristian Høgsberg <krh@bitplanet.net>
  26  */
  27
  28 #include <stdlib.h>
  29 #include <string.h>
  30 #include <stdio.h>
  31 #include <limits.h>
  32 #include <dlfcn.h>
  33 #include <fcntl.h>
  34 #include <errno.h>
  35 #include <unistd.h>
  36 #include <xf86drm.h>
  37 #include <sys/types.h>
  38 #include <sys/stat.h>
  39
  40 #ifdef HAVE_LIBUDEV
  41 #include <libudev.h>
  42 #endif
  43
  44 #include "egl_dri2.h"
  45
  46
  47 #ifdef HAVE_LIBUDEV
  48
  49 struct dri2_driver_map {
  50    int vendor_id;
  51    const char *driver;
  52    const int *chip_ids;
  53    int num_chips_ids;
  54 };
  55
  56 const int i915_chip_ids[] = {
  57    0x3577, /* PCI_CHIP_I830_M */
  58    0x2562, /* PCI_CHIP_845_G */
  59    0x3582, /* PCI_CHIP_I855_GM */
  60    0x2572, /* PCI_CHIP_I865_G */
  61    0x2582, /* PCI_CHIP_I915_G */
  62    0x258a, /* PCI_CHIP_E7221_G */
  63    0x2592, /* PCI_CHIP_I915_GM */
  64    0x2772, /* PCI_CHIP_I945_G */
  65    0x27a2, /* PCI_CHIP_I945_GM */
  66    0x27ae, /* PCI_CHIP_I945_GME */
  67    0x29b2, /* PCI_CHIP_Q35_G */
  68    0x29c2, /* PCI_CHIP_G33_G */
  69    0x29d2, /* PCI_CHIP_Q33_G */
  70    0xa001, /* PCI_CHIP_IGD_G */
  71    0xa011, /* Pineview */
  72 };
  73
  74 const int i965_chip_ids[] = {
  75    0x0042, /* PCI_CHIP_ILD_G */
  76    0x0046, /* PCI_CHIP_ILM_G */
  77    0x0102, /* PCI_CHIP_SANDYBRIDGE_GT1 */
  78    0x0106, /* PCI_CHIP_SANDYBRIDGE_M_GT1 */
  79    0x010a, /* PCI_CHIP_SANDYBRIDGE_S */
  80    0x0112, /* PCI_CHIP_SANDYBRIDGE_GT2 */
  81    0x0116, /* PCI_CHIP_SANDYBRIDGE_M_GT2 */
  82    0x0122, /* PCI_CHIP_SANDYBRIDGE_GT2_PLUS */
  83    0x0126, /* PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS */
  84    0x0152, /* PCI_CHIP_IVYBRIDGE_GT1 */
  85    0x0162, /* PCI_CHIP_IVYBRIDGE_GT2 */
  86    0x0156, /* PCI_CHIP_IVYBRIDGE_M_GT1 */
  87    0x0166, /* PCI_CHIP_IVYBRIDGE_M_GT2 */
  88    0x015a, /* PCI_CHIP_IVYBRIDGE_S_GT1 */
  89    0x29a2, /* PCI_CHIP_I965_G */
  90    0x2992, /* PCI_CHIP_I965_Q */
  91    0x2982, /* PCI_CHIP_I965_G_1 */
  92    0x2972, /* PCI_CHIP_I946_GZ */
  93    0x2a02, /* PCI_CHIP_I965_GM */
  94    0x2a12, /* PCI_CHIP_I965_GME */
  95    0x2a42, /* PCI_CHIP_GM45_GM */
  96    0x2e02, /* PCI_CHIP_IGD_E_G */
  97    0x2e12, /* PCI_CHIP_Q45_G */
  98    0x2e22, /* PCI_CHIP_G45_G */
  99    0x2e32, /* PCI_CHIP_G41_G */
 100    0x2e42, /* PCI_CHIP_B43_G */
 101    0x2e92, /* PCI_CHIP_B43_G1 */
 102 };
 103
 104 const int r100_chip_ids[] = {
 105    0x4C57, /* PCI_CHIP_RADEON_LW */
 106    0x4C58, /* PCI_CHIP_RADEON_LX */
 107    0x4C59, /* PCI_CHIP_RADEON_LY */
 108    0x4C5A, /* PCI_CHIP_RADEON_LZ */
 109    0x5144, /* PCI_CHIP_RADEON_QD */
 110    0x5145, /* PCI_CHIP_RADEON_QE */
 111    0x5146, /* PCI_CHIP_RADEON_QF */
 112    0x5147, /* PCI_CHIP_RADEON_QG */
 113    0x5159, /* PCI_CHIP_RADEON_QY */
 114    0x515A, /* PCI_CHIP_RADEON_QZ */
 115    0x5157, /* PCI_CHIP_RV200_QW */
 116    0x5158, /* PCI_CHIP_RV200_QX */
 117    0x515E, /* PCI_CHIP_RN50_515E */
 118    0x5969, /* PCI_CHIP_RN50_5969 */
 119    0x4136, /* PCI_CHIP_RS100_4136 */
 120    0x4336, /* PCI_CHIP_RS100_4336 */
 121    0x4137, /* PCI_CHIP_RS200_4137 */
 122    0x4337, /* PCI_CHIP_RS200_4337 */
 123    0x4237, /* PCI_CHIP_RS250_4237 */
 124    0x4437, /* PCI_CHIP_RS250_4437 */
 125 };
 126
 127 const int r200_chip_ids[] = {
 128    0x5148, /* PCI_CHIP_R200_QH */
 129    0x514C, /* PCI_CHIP_R200_QL */
 130    0x514D, /* PCI_CHIP_R200_QM */
 131    0x4242, /* PCI_CHIP_R200_BB */
 132    0x4966, /* PCI_CHIP_RV250_If */
 133    0x4967, /* PCI_CHIP_RV250_Ig */
 134    0x4C64, /* PCI_CHIP_RV250_Ld */
 135    0x4C66, /* PCI_CHIP_RV250_Lf */
 136    0x4C67, /* PCI_CHIP_RV250_Lg */
 137    0x5960, /* PCI_CHIP_RV280_5960 */
 138    0x5961, /* PCI_CHIP_RV280_5961 */
 139    0x5962, /* PCI_CHIP_RV280_5962 */
 140    0x5964, /* PCI_CHIP_RV280_5964 */
 141    0x5965, /* PCI_CHIP_RV280_5965 */
 142    0x5C61, /* PCI_CHIP_RV280_5C61 */
 143    0x5C63, /* PCI_CHIP_RV280_5C63 */
 144    0x5834, /* PCI_CHIP_RS300_5834 */
 145    0x5835, /* PCI_CHIP_RS300_5835 */
 146    0x7834, /* PCI_CHIP_RS350_7834 */
 147    0x7835, /* PCI_CHIP_RS350_7835 */
 148 };
 149
 150 const int r300_chip_ids[] = {
 151    0x4144, /* PCI_CHIP_R300_AD */
 152    0x4145, /* PCI_CHIP_R300_AE */
 153    0x4146, /* PCI_CHIP_R300_AF */
 154    0x4147, /* PCI_CHIP_R300_AG */
 155    0x4E44, /* PCI_CHIP_R300_ND */
 156    0x4E45, /* PCI_CHIP_R300_NE */
 157    0x4E46, /* PCI_CHIP_R300_NF */
 158    0x4E47, /* PCI_CHIP_R300_NG */
 159    0x4E48, /* PCI_CHIP_R350_NH */
 160    0x4E49, /* PCI_CHIP_R350_NI */
 161    0x4E4B, /* PCI_CHIP_R350_NK */
 162    0x4148, /* PCI_CHIP_R350_AH */
 163    0x4149, /* PCI_CHIP_R350_AI */
 164    0x414A, /* PCI_CHIP_R350_AJ */
 165    0x414B, /* PCI_CHIP_R350_AK */
 166    0x4E4A, /* PCI_CHIP_R360_NJ */
 167    0x4150, /* PCI_CHIP_RV350_AP */
 168    0x4151, /* PCI_CHIP_RV350_AQ */
 169    0x4152, /* PCI_CHIP_RV350_AR */
 170    0x4153, /* PCI_CHIP_RV350_AS */
 171    0x4154, /* PCI_CHIP_RV350_AT */
 172    0x4155, /* PCI_CHIP_RV350_AU */
 173    0x4156, /* PCI_CHIP_RV350_AV */
 174    0x4E50, /* PCI_CHIP_RV350_NP */
 175    0x4E51, /* PCI_CHIP_RV350_NQ */
 176    0x4E52, /* PCI_CHIP_RV350_NR */
 177    0x4E53, /* PCI_CHIP_RV350_NS */
 178    0x4E54, /* PCI_CHIP_RV350_NT */
 179    0x4E56, /* PCI_CHIP_RV350_NV */
 180    0x5460, /* PCI_CHIP_RV370_5460 */
 181    0x5462, /* PCI_CHIP_RV370_5462 */
 182    0x5464, /* PCI_CHIP_RV370_5464 */
 183    0x5B60, /* PCI_CHIP_RV370_5B60 */
 184    0x5B62, /* PCI_CHIP_RV370_5B62 */
 185    0x5B63, /* PCI_CHIP_RV370_5B63 */
 186    0x5B64, /* PCI_CHIP_RV370_5B64 */
 187    0x5B65, /* PCI_CHIP_RV370_5B65 */
 188    0x3150, /* PCI_CHIP_RV380_3150 */
 189    0x3152, /* PCI_CHIP_RV380_3152 */
 190    0x3154, /* PCI_CHIP_RV380_3154 */
 191    0x3155, /* PCI_CHIP_RV380_3155 */
 192    0x3E50, /* PCI_CHIP_RV380_3E50 */
 193    0x3E54, /* PCI_CHIP_RV380_3E54 */
 194    0x4A48, /* PCI_CHIP_R420_JH */
 195    0x4A49, /* PCI_CHIP_R420_JI */
 196    0x4A4A, /* PCI_CHIP_R420_JJ */
 197    0x4A4B, /* PCI_CHIP_R420_JK */
 198    0x4A4C, /* PCI_CHIP_R420_JL */
 199    0x4A4D, /* PCI_CHIP_R420_JM */
 200    0x4A4E, /* PCI_CHIP_R420_JN */
 201    0x4A4F, /* PCI_CHIP_R420_JO */
 202    0x4A50, /* PCI_CHIP_R420_JP */
 203    0x4A54, /* PCI_CHIP_R420_JT */
 204    0x5548, /* PCI_CHIP_R423_UH */
 205    0x5549, /* PCI_CHIP_R423_UI */
 206    0x554A, /* PCI_CHIP_R423_UJ */
 207    0x554B, /* PCI_CHIP_R423_UK */
 208    0x5550, /* PCI_CHIP_R423_5550 */
 209    0x5551, /* PCI_CHIP_R423_UQ */
 210    0x5552, /* PCI_CHIP_R423_UR */
 211    0x5554, /* PCI_CHIP_R423_UT */
 212    0x5D57, /* PCI_CHIP_R423_5D57 */
 213    0x554C, /* PCI_CHIP_R430_554C */
 214    0x554D, /* PCI_CHIP_R430_554D */
 215    0x554E, /* PCI_CHIP_R430_554E */
 216    0x554F, /* PCI_CHIP_R430_554F */
 217    0x5D48, /* PCI_CHIP_R430_5D48 */
 218    0x5D49, /* PCI_CHIP_R430_5D49 */
 219    0x5D4A, /* PCI_CHIP_R430_5D4A */
 220    0x5D4C, /* PCI_CHIP_R480_5D4C */
 221    0x5D4D, /* PCI_CHIP_R480_5D4D */
 222    0x5D4E, /* PCI_CHIP_R480_5D4E */
 223    0x5D4F, /* PCI_CHIP_R480_5D4F */
 224    0x5D50, /* PCI_CHIP_R480_5D50 */
 225    0x5D52, /* PCI_CHIP_R480_5D52 */
 226    0x4B49, /* PCI_CHIP_R481_4B49 */
 227    0x4B4A, /* PCI_CHIP_R481_4B4A */
 228    0x4B4B, /* PCI_CHIP_R481_4B4B */
 229    0x4B4C, /* PCI_CHIP_R481_4B4C */
 230    0x564A, /* PCI_CHIP_RV410_564A */
 231    0x564B, /* PCI_CHIP_RV410_564B */
 232    0x564F, /* PCI_CHIP_RV410_564F */
 233    0x5652, /* PCI_CHIP_RV410_5652 */
 234    0x5653, /* PCI_CHIP_RV410_5653 */
 235    0x5657, /* PCI_CHIP_RV410_5657 */
 236    0x5E48, /* PCI_CHIP_RV410_5E48 */
 237    0x5E4A, /* PCI_CHIP_RV410_5E4A */
 238    0x5E4B, /* PCI_CHIP_RV410_5E4B */
 239    0x5E4C, /* PCI_CHIP_RV410_5E4C */
 240    0x5E4D, /* PCI_CHIP_RV410_5E4D */
 241    0x5E4F, /* PCI_CHIP_RV410_5E4F */
 242    0x5A41, /* PCI_CHIP_RS400_5A41 */
 243    0x5A42, /* PCI_CHIP_RS400_5A42 */
 244    0x5A61, /* PCI_CHIP_RC410_5A61 */
 245    0x5A62, /* PCI_CHIP_RC410_5A62 */
 246    0x5954, /* PCI_CHIP_RS480_5954 */
 247    0x5955, /* PCI_CHIP_RS480_5955 */
 248    0x5974, /* PCI_CHIP_RS482_5974 */
 249    0x5975, /* PCI_CHIP_RS482_5975 */
 250    0x7100, /* PCI_CHIP_R520_7100 */
 251    0x7101, /* PCI_CHIP_R520_7101 */
 252    0x7102, /* PCI_CHIP_R520_7102 */
 253    0x7103, /* PCI_CHIP_R520_7103 */
 254    0x7104, /* PCI_CHIP_R520_7104 */
 255    0x7105, /* PCI_CHIP_R520_7105 */
 256    0x7106, /* PCI_CHIP_R520_7106 */
 257    0x7108, /* PCI_CHIP_R520_7108 */
 258    0x7109, /* PCI_CHIP_R520_7109 */
 259    0x710A, /* PCI_CHIP_R520_710A */
 260    0x710B, /* PCI_CHIP_R520_710B */
 261    0x710C, /* PCI_CHIP_R520_710C */
 262    0x710E, /* PCI_CHIP_R520_710E */
 263    0x710F, /* PCI_CHIP_R520_710F */
 264    0x7140, /* PCI_CHIP_RV515_7140 */
 265    0x7141, /* PCI_CHIP_RV515_7141 */
 266    0x7142, /* PCI_CHIP_RV515_7142 */
 267    0x7143, /* PCI_CHIP_RV515_7143 */
 268    0x7144, /* PCI_CHIP_RV515_7144 */
 269    0x7145, /* PCI_CHIP_RV515_7145 */
 270    0x7146, /* PCI_CHIP_RV515_7146 */
 271    0x7147, /* PCI_CHIP_RV515_7147 */
 272    0x7149, /* PCI_CHIP_RV515_7149 */
 273    0x714A, /* PCI_CHIP_RV515_714A */
 274    0x714B, /* PCI_CHIP_RV515_714B */
 275    0x714C, /* PCI_CHIP_RV515_714C */
 276    0x714D, /* PCI_CHIP_RV515_714D */
 277    0x714E, /* PCI_CHIP_RV515_714E */
 278    0x714F, /* PCI_CHIP_RV515_714F */
 279    0x7151, /* PCI_CHIP_RV515_7151 */
 280    0x7152, /* PCI_CHIP_RV515_7152 */
 281    0x7153, /* PCI_CHIP_RV515_7153 */
 282    0x715E, /* PCI_CHIP_RV515_715E */
 283    0x715F, /* PCI_CHIP_RV515_715F */
 284    0x7180, /* PCI_CHIP_RV515_7180 */
 285    0x7181, /* PCI_CHIP_RV515_7181 */
 286    0x7183, /* PCI_CHIP_RV515_7183 */
 287    0x7186, /* PCI_CHIP_RV515_7186 */
 288    0x7187, /* PCI_CHIP_RV515_7187 */
 289    0x7188, /* PCI_CHIP_RV515_7188 */
 290    0x718A, /* PCI_CHIP_RV515_718A */
 291    0x718B, /* PCI_CHIP_RV515_718B */
 292    0x718C, /* PCI_CHIP_RV515_718C */
 293    0x718D, /* PCI_CHIP_RV515_718D */
 294    0x718F, /* PCI_CHIP_RV515_718F */
 295    0x7193, /* PCI_CHIP_RV515_7193 */
 296    0x7196, /* PCI_CHIP_RV515_7196 */
 297    0x719B, /* PCI_CHIP_RV515_719B */
 298    0x719F, /* PCI_CHIP_RV515_719F */
 299    0x7200, /* PCI_CHIP_RV515_7200 */
 300    0x7210, /* PCI_CHIP_RV515_7210 */
 301    0x7211, /* PCI_CHIP_RV515_7211 */
 302    0x71C0, /* PCI_CHIP_RV530_71C0 */
 303    0x71C1, /* PCI_CHIP_RV530_71C1 */
 304    0x71C2, /* PCI_CHIP_RV530_71C2 */
 305    0x71C3, /* PCI_CHIP_RV530_71C3 */
 306    0x71C4, /* PCI_CHIP_RV530_71C4 */
 307    0x71C5, /* PCI_CHIP_RV530_71C5 */
 308    0x71C6, /* PCI_CHIP_RV530_71C6 */
 309    0x71C7, /* PCI_CHIP_RV530_71C7 */
 310    0x71CD, /* PCI_CHIP_RV530_71CD */
 311    0x71CE, /* PCI_CHIP_RV530_71CE */
 312    0x71D2, /* PCI_CHIP_RV530_71D2 */
 313    0x71D4, /* PCI_CHIP_RV530_71D4 */
 314    0x71D5, /* PCI_CHIP_RV530_71D5 */
 315    0x71D6, /* PCI_CHIP_RV530_71D6 */
 316    0x71DA, /* PCI_CHIP_RV530_71DA */
 317    0x71DE, /* PCI_CHIP_RV530_71DE */
 318    0x7281, /* PCI_CHIP_RV560_7281 */
 319    0x7283, /* PCI_CHIP_RV560_7283 */
 320    0x7287, /* PCI_CHIP_RV560_7287 */
 321    0x7290, /* PCI_CHIP_RV560_7290 */
 322    0x7291, /* PCI_CHIP_RV560_7291 */
 323    0x7293, /* PCI_CHIP_RV560_7293 */
 324    0x7297, /* PCI_CHIP_RV560_7297 */
 325    0x7280, /* PCI_CHIP_RV570_7280 */
 326    0x7288, /* PCI_CHIP_RV570_7288 */
 327    0x7289, /* PCI_CHIP_RV570_7289 */
 328    0x728B, /* PCI_CHIP_RV570_728B */
 329    0x728C, /* PCI_CHIP_RV570_728C */
 330    0x7240, /* PCI_CHIP_R580_7240 */
 331    0x7243, /* PCI_CHIP_R580_7243 */
 332    0x7244, /* PCI_CHIP_R580_7244 */
 333    0x7245, /* PCI_CHIP_R580_7245 */
 334    0x7246, /* PCI_CHIP_R580_7246 */
 335    0x7247, /* PCI_CHIP_R580_7247 */
 336    0x7248, /* PCI_CHIP_R580_7248 */
 337    0x7249, /* PCI_CHIP_R580_7249 */
 338    0x724A, /* PCI_CHIP_R580_724A */
 339    0x724B, /* PCI_CHIP_R580_724B */
 340    0x724C, /* PCI_CHIP_R580_724C */
 341    0x724D, /* PCI_CHIP_R580_724D */
 342    0x724E, /* PCI_CHIP_R580_724E */
 343    0x724F, /* PCI_CHIP_R580_724F */
 344    0x7284, /* PCI_CHIP_R580_7284 */
 345    0x793F, /* PCI_CHIP_RS600_793F */
 346    0x7941, /* PCI_CHIP_RS600_7941 */
 347    0x7942, /* PCI_CHIP_RS600_7942 */
 348    0x791E, /* PCI_CHIP_RS690_791E */
 349    0x791F, /* PCI_CHIP_RS690_791F */
 350    0x796C, /* PCI_CHIP_RS740_796C */
 351    0x796D, /* PCI_CHIP_RS740_796D */
 352    0x796E, /* PCI_CHIP_RS740_796E */
 353    0x796F, /* PCI_CHIP_RS740_796F */
 354 };
 355
 356 const int r600_chip_ids[] = {
 357    0x9400, /* PCI_CHIP_R600_9400 */
 358    0x9401, /* PCI_CHIP_R600_9401 */
 359    0x9402, /* PCI_CHIP_R600_9402 */
 360    0x9403, /* PCI_CHIP_R600_9403 */
 361    0x9405, /* PCI_CHIP_R600_9405 */
 362    0x940A, /* PCI_CHIP_R600_940A */
 363    0x940B, /* PCI_CHIP_R600_940B */
 364    0x940F, /* PCI_CHIP_R600_940F */
 365    0x94C0, /* PCI_CHIP_RV610_94C0 */
 366    0x94C1, /* PCI_CHIP_RV610_94C1 */
 367    0x94C3, /* PCI_CHIP_RV610_94C3 */
 368    0x94C4, /* PCI_CHIP_RV610_94C4 */
 369    0x94C5, /* PCI_CHIP_RV610_94C5 */
 370    0x94C6, /* PCI_CHIP_RV610_94C6 */
 371    0x94C7, /* PCI_CHIP_RV610_94C7 */
 372    0x94C8, /* PCI_CHIP_RV610_94C8 */
 373    0x94C9, /* PCI_CHIP_RV610_94C9 */
 374    0x94CB, /* PCI_CHIP_RV610_94CB */
 375    0x94CC, /* PCI_CHIP_RV610_94CC */
 376    0x94CD, /* PCI_CHIP_RV610_94CD */
 377    0x9580, /* PCI_CHIP_RV630_9580 */
 378    0x9581, /* PCI_CHIP_RV630_9581 */
 379    0x9583, /* PCI_CHIP_RV630_9583 */
 380    0x9586, /* PCI_CHIP_RV630_9586 */
 381    0x9587, /* PCI_CHIP_RV630_9587 */
 382    0x9588, /* PCI_CHIP_RV630_9588 */
 383    0x9589, /* PCI_CHIP_RV630_9589 */
 384    0x958A, /* PCI_CHIP_RV630_958A */
 385    0x958B, /* PCI_CHIP_RV630_958B */
 386    0x958C, /* PCI_CHIP_RV630_958C */
 387    0x958D, /* PCI_CHIP_RV630_958D */
 388    0x958E, /* PCI_CHIP_RV630_958E */
 389    0x958F, /* PCI_CHIP_RV630_958F */
 390    0x9500, /* PCI_CHIP_RV670_9500 */
 391    0x9501, /* PCI_CHIP_RV670_9501 */
 392    0x9504, /* PCI_CHIP_RV670_9504 */
 393    0x9505, /* PCI_CHIP_RV670_9505 */
 394    0x9506, /* PCI_CHIP_RV670_9506 */
 395    0x9507, /* PCI_CHIP_RV670_9507 */
 396    0x9508, /* PCI_CHIP_RV670_9508 */
 397    0x9509, /* PCI_CHIP_RV670_9509 */
 398    0x950F, /* PCI_CHIP_RV670_950F */
 399    0x9511, /* PCI_CHIP_RV670_9511 */
 400    0x9515, /* PCI_CHIP_RV670_9515 */
 401    0x9517, /* PCI_CHIP_RV670_9517 */
 402    0x9519, /* PCI_CHIP_RV670_9519 */
 403    0x95C0, /* PCI_CHIP_RV620_95C0 */
 404    0x95C2, /* PCI_CHIP_RV620_95C2 */
 405    0x95C4, /* PCI_CHIP_RV620_95C4 */
 406    0x95C5, /* PCI_CHIP_RV620_95C5 */
 407    0x95C6, /* PCI_CHIP_RV620_95C6 */
 408    0x95C7, /* PCI_CHIP_RV620_95C7 */
 409    0x95C9, /* PCI_CHIP_RV620_95C9 */
 410    0x95CC, /* PCI_CHIP_RV620_95CC */
 411    0x95CD, /* PCI_CHIP_RV620_95CD */
 412    0x95CE, /* PCI_CHIP_RV620_95CE */
 413    0x95CF, /* PCI_CHIP_RV620_95CF */
 414    0x9590, /* PCI_CHIP_RV635_9590 */
 415    0x9591, /* PCI_CHIP_RV635_9591 */
 416    0x9593, /* PCI_CHIP_RV635_9593 */
 417    0x9595, /* PCI_CHIP_RV635_9595 */
 418    0x9596, /* PCI_CHIP_RV635_9596 */
 419    0x9597, /* PCI_CHIP_RV635_9597 */
 420    0x9598, /* PCI_CHIP_RV635_9598 */
 421    0x9599, /* PCI_CHIP_RV635_9599 */
 422    0x959B, /* PCI_CHIP_RV635_959B */
 423    0x9610, /* PCI_CHIP_RS780_9610 */
 424    0x9611, /* PCI_CHIP_RS780_9611 */
 425    0x9612, /* PCI_CHIP_RS780_9612 */
 426    0x9613, /* PCI_CHIP_RS780_9613 */
 427    0x9614, /* PCI_CHIP_RS780_9614 */
 428    0x9615, /* PCI_CHIP_RS780_9615 */
 429    0x9616, /* PCI_CHIP_RS780_9616 */
 430    0x9710, /* PCI_CHIP_RS880_9710 */
 431    0x9711, /* PCI_CHIP_RS880_9711 */
 432    0x9712, /* PCI_CHIP_RS880_9712 */
 433    0x9713, /* PCI_CHIP_RS880_9713 */
 434    0x9714, /* PCI_CHIP_RS880_9714 */
 435    0x9715, /* PCI_CHIP_RS880_9715 */
 436    0x9440, /* PCI_CHIP_RV770_9440 */
 437    0x9441, /* PCI_CHIP_RV770_9441 */
 438    0x9442, /* PCI_CHIP_RV770_9442 */
 439    0x9443, /* PCI_CHIP_RV770_9443 */
 440    0x9444, /* PCI_CHIP_RV770_9444 */
 441    0x9446, /* PCI_CHIP_RV770_9446 */
 442    0x944A, /* PCI_CHIP_RV770_944A */
 443    0x944B, /* PCI_CHIP_RV770_944B */
 444    0x944C, /* PCI_CHIP_RV770_944C */
 445    0x944E, /* PCI_CHIP_RV770_944E */
 446    0x9450, /* PCI_CHIP_RV770_9450 */
 447    0x9452, /* PCI_CHIP_RV770_9452 */
 448    0x9456, /* PCI_CHIP_RV770_9456 */
 449    0x945A, /* PCI_CHIP_RV770_945A */
 450    0x945B, /* PCI_CHIP_RV770_945B */
 451    0x945E, /* PCI_CHIP_RV770_945E */
 452    0x9460, /* PCI_CHIP_RV790_9460 */
 453    0x9462, /* PCI_CHIP_RV790_9462 */
 454    0x946A, /* PCI_CHIP_RV770_946A */
 455    0x946B, /* PCI_CHIP_RV770_946B */
 456    0x947A, /* PCI_CHIP_RV770_947A */
 457    0x947B, /* PCI_CHIP_RV770_947B */
 458    0x9480, /* PCI_CHIP_RV730_9480 */
 459    0x9487, /* PCI_CHIP_RV730_9487 */
 460    0x9488, /* PCI_CHIP_RV730_9488 */
 461    0x9489, /* PCI_CHIP_RV730_9489 */
 462    0x948A, /* PCI_CHIP_RV730_948A */
 463    0x948F, /* PCI_CHIP_RV730_948F */
 464    0x9490, /* PCI_CHIP_RV730_9490 */
 465    0x9491, /* PCI_CHIP_RV730_9491 */
 466    0x9495, /* PCI_CHIP_RV730_9495 */
 467    0x9498, /* PCI_CHIP_RV730_9498 */
 468    0x949C, /* PCI_CHIP_RV730_949C */
 469    0x949E, /* PCI_CHIP_RV730_949E */
 470    0x949F, /* PCI_CHIP_RV730_949F */
 471    0x9540, /* PCI_CHIP_RV710_9540 */
 472    0x9541, /* PCI_CHIP_RV710_9541 */
 473    0x9542, /* PCI_CHIP_RV710_9542 */
 474    0x954E, /* PCI_CHIP_RV710_954E */
 475    0x954F, /* PCI_CHIP_RV710_954F */
 476    0x9552, /* PCI_CHIP_RV710_9552 */
 477    0x9553, /* PCI_CHIP_RV710_9553 */
 478    0x9555, /* PCI_CHIP_RV710_9555 */
 479    0x9557, /* PCI_CHIP_RV710_9557 */
 480    0x955F, /* PCI_CHIP_RV710_955F */
 481    0x94A0, /* PCI_CHIP_RV740_94A0 */
 482    0x94A1, /* PCI_CHIP_RV740_94A1 */
 483    0x94A3, /* PCI_CHIP_RV740_94A3 */
 484    0x94B1, /* PCI_CHIP_RV740_94B1 */
 485    0x94B3, /* PCI_CHIP_RV740_94B3 */
 486    0x94B4, /* PCI_CHIP_RV740_94B4 */
 487    0x94B5, /* PCI_CHIP_RV740_94B5 */
 488    0x94B9, /* PCI_CHIP_RV740_94B9 */
 489    0x68E0, /* PCI_CHIP_CEDAR_68E0 */
 490    0x68E1, /* PCI_CHIP_CEDAR_68E1 */
 491    0x68E4, /* PCI_CHIP_CEDAR_68E4 */
 492    0x68E5, /* PCI_CHIP_CEDAR_68E5 */
 493    0x68E8, /* PCI_CHIP_CEDAR_68E8 */
 494    0x68E9, /* PCI_CHIP_CEDAR_68E9 */
 495    0x68F1, /* PCI_CHIP_CEDAR_68F1 */
 496    0x68F2, /* PCI_CHIP_CEDAR_68F2 */
 497    0x68F8, /* PCI_CHIP_CEDAR_68F8 */
 498    0x68F9, /* PCI_CHIP_CEDAR_68F9 */
 499    0x68FE, /* PCI_CHIP_CEDAR_68FE */
 500    0x68C0, /* PCI_CHIP_REDWOOD_68C0 */
 501    0x68C1, /* PCI_CHIP_REDWOOD_68C1 */
 502    0x68C8, /* PCI_CHIP_REDWOOD_68C8 */
 503    0x68C9, /* PCI_CHIP_REDWOOD_68C9 */
 504    0x68D8, /* PCI_CHIP_REDWOOD_68D8 */
 505    0x68D9, /* PCI_CHIP_REDWOOD_68D9 */
 506    0x68DA, /* PCI_CHIP_REDWOOD_68DA */
 507    0x68DE, /* PCI_CHIP_REDWOOD_68DE */
 508    0x68A0, /* PCI_CHIP_JUNIPER_68A0 */
 509    0x68A1, /* PCI_CHIP_JUNIPER_68A1 */
 510    0x68A8, /* PCI_CHIP_JUNIPER_68A8 */
 511    0x68A9, /* PCI_CHIP_JUNIPER_68A9 */
 512    0x68B0, /* PCI_CHIP_JUNIPER_68B0 */
 513    0x68B8, /* PCI_CHIP_JUNIPER_68B8 */
 514    0x68B9, /* PCI_CHIP_JUNIPER_68B9 */
 515    0x68BA, /* PCI_CHIP_JUNIPER_68BA */
 516    0x68BE, /* PCI_CHIP_JUNIPER_68BE */
 517    0x68BF, /* PCI_CHIP_JUNIPER_68BF */
 518    0x6880, /* PCI_CHIP_CYPRESS_6880 */
 519    0x6888, /* PCI_CHIP_CYPRESS_6888 */
 520    0x6889, /* PCI_CHIP_CYPRESS_6889 */
 521    0x688A, /* PCI_CHIP_CYPRESS_688A */
 522    0x6898, /* PCI_CHIP_CYPRESS_6898 */
 523    0x6899, /* PCI_CHIP_CYPRESS_6899 */
 524    0x689B, /* PCI_CHIP_CYPRESS_689B */
 525    0x689E, /* PCI_CHIP_CYPRESS_689E */
 526    0x689C, /* PCI_CHIP_HEMLOCK_689C */
 527    0x689D, /* PCI_CHIP_HEMLOCK_689D */
 528    0x9802, /* PCI_CHIP_PALM_9802 */
 529    0x9803, /* PCI_CHIP_PALM_9803 */
 530    0x9804, /* PCI_CHIP_PALM_9804 */
 531    0x9805, /* PCI_CHIP_PALM_9805 */
 532    0x9806, /* PCI_CHIP_PALM_9806 */
 533    0x9807, /* PCI_CHIP_PALM_9807 */
 534    0x6720, /* PCI_CHIP_BARTS_6720 */
 535    0x6721, /* PCI_CHIP_BARTS_6721 */
 536    0x6722, /* PCI_CHIP_BARTS_6722 */
 537    0x6723, /* PCI_CHIP_BARTS_6723 */
 538    0x6724, /* PCI_CHIP_BARTS_6724 */
 539    0x6725, /* PCI_CHIP_BARTS_6725 */
 540    0x6726, /* PCI_CHIP_BARTS_6726 */
 541    0x6727, /* PCI_CHIP_BARTS_6727 */
 542    0x6728, /* PCI_CHIP_BARTS_6728 */
 543    0x6729, /* PCI_CHIP_BARTS_6729 */
 544    0x6738, /* PCI_CHIP_BARTS_6738 */
 545    0x6739, /* PCI_CHIP_BARTS_6738 */
 546    0x673E, /* PCI_CHIP_BARTS_673E */
 547    0x6740, /* PCI_CHIP_TURKS_6740 */
 548    0x6741, /* PCI_CHIP_TURKS_6741 */
 549    0x6742, /* PCI_CHIP_TURKS_6742 */
 550    0x6743, /* PCI_CHIP_TURKS_6743 */
 551    0x6744, /* PCI_CHIP_TURKS_6744 */
 552    0x6745, /* PCI_CHIP_TURKS_6745 */
 553    0x6746, /* PCI_CHIP_TURKS_6746 */
 554    0x6747, /* PCI_CHIP_TURKS_6747 */
 555    0x6748, /* PCI_CHIP_TURKS_6748 */
 556    0x6749, /* PCI_CHIP_TURKS_6749 */
 557    0x6750, /* PCI_CHIP_TURKS_6750 */
 558    0x6758, /* PCI_CHIP_TURKS_6758 */
 559    0x6759, /* PCI_CHIP_TURKS_6759 */
 560    0x6760, /* PCI_CHIP_CAICOS_6760 */
 561    0x6761, /* PCI_CHIP_CAICOS_6761 */
 562    0x6762, /* PCI_CHIP_CAICOS_6762 */
 563    0x6763, /* PCI_CHIP_CAICOS_6763 */
 564    0x6764, /* PCI_CHIP_CAICOS_6764 */
 565    0x6765, /* PCI_CHIP_CAICOS_6765 */
 566    0x6766, /* PCI_CHIP_CAICOS_6766 */
 567    0x6767, /* PCI_CHIP_CAICOS_6767 */
 568    0x6768, /* PCI_CHIP_CAICOS_6768 */
 569    0x6770, /* PCI_CHIP_CAICOS_6770 */
 570    0x6779, /* PCI_CHIP_CAICOS_6779 */
 571 };
 572
 573 const struct dri2_driver_map driver_map[] = {
 574    { 0x8086, "i915", i915_chip_ids, ARRAY_SIZE(i915_chip_ids) },
 575    { 0x8086, "i965", i965_chip_ids, ARRAY_SIZE(i965_chip_ids) },
 576    { 0x1002, "radeon", r100_chip_ids, ARRAY_SIZE(r100_chip_ids) },
 577    { 0x1002, "r200", r200_chip_ids, ARRAY_SIZE(r200_chip_ids) },
 578    { 0x1002, "r300", r300_chip_ids, ARRAY_SIZE(r300_chip_ids) },
 579    { 0x1002, "r600", r600_chip_ids, ARRAY_SIZE(r600_chip_ids) },
 580    { 0x10de, "nouveau", NULL, -1 },
 581 };
 582
 583 static char *
 584 dri2_get_device_name(int fd)
 585 {
 586    struct udev *udev;
 587    struct udev_device *device;
 588    struct stat buf;
 589    const char *const_device_name;
 590    char *device_name = NULL;
 591
 592    udev = udev_new();
 593    if (fstat(fd, &buf) < 0) {
 594       _eglLog(_EGL_WARNING, "EGL-DRI2: failed to stat fd %d", fd);
 595       goto out;
 596    }
 597
 598    device = udev_device_new_from_devnum(udev, 'c', buf.st_rdev);
 599    if (device == NULL) {
 600       _eglLog(_EGL_WARNING,
 601               "EGL-DRI2: could not create udev device for fd %d", fd);
 602       goto out;
 603    }
 604
 605    const_device_name = udev_device_get_devnode(device);
 606    if (!const_device_name) {
 607       goto out;
 608    }
 609    device_name = strdup(const_device_name);
 610
 611  out:
 612    udev_device_unref(device);
 613    udev_unref(udev);
 614
 615    return device_name;
 616 }
 617
 618 char *
 619 dri2_get_driver_for_fd(int fd)
 620 {
 621    struct udev *udev;
 622    struct udev_device *device, *parent;
 623    struct stat buf;
 624    const char *pci_id;
 625    char *driver = NULL;
 626    int vendor_id, chip_id, i, j;
 627
 628    udev = udev_new();
 629    if (fstat(fd, &buf) < 0) {
 630       _eglLog(_EGL_WARNING, "EGL-DRI2: failed to stat fd %d", fd);
 631       goto out;
 632    }
 633
 634    device = udev_device_new_from_devnum(udev, 'c', buf.st_rdev);
 635    if (device == NULL) {
 636       _eglLog(_EGL_WARNING,
 637               "EGL-DRI2: could not create udev device for fd %d", fd);
 638       goto out;
 639    }
 640
 641    parent = udev_device_get_parent(device);
 642    if (parent == NULL) {
 643       _eglLog(_EGL_WARNING, "DRI2: could not get parent device");
 644       goto out;
 645    }
 646
 647    pci_id = udev_device_get_property_value(parent, "PCI_ID");
 648    if (pci_id == NULL || sscanf(pci_id, "%x:%x", &vendor_id, &chip_id) != 2) {
 649       _eglLog(_EGL_WARNING, "EGL-DRI2: malformed or no PCI ID");
 650       goto out;
 651    }
 652
 653    for (i = 0; i < ARRAY_SIZE(driver_map); i++) {
 654       if (vendor_id != driver_map[i].vendor_id)
 655          continue;
 656       if (driver_map[i].num_chips_ids == -1) {
 657             driver = strdup(driver_map[i].driver);
 658             _eglLog(_EGL_DEBUG, "pci id for %d: %04x:%04x, driver %s",
 659                     fd, vendor_id, chip_id, driver);
 660             goto out;
 661       }
 662
 663       for (j = 0; j < driver_map[i].num_chips_ids; j++)
 664          if (driver_map[i].chip_ids[j] == chip_id) {
 665             driver = strdup(driver_map[i].driver);
 666             _eglLog(_EGL_DEBUG, "pci id for %d: %04x:%04x, driver %s",
 667                     fd, vendor_id, chip_id, driver);
 668             goto out;
 669          }
 670    }
 671
 672  out:
 673    udev_device_unref(device);
 674    udev_unref(udev);
 675
 676    return driver;
 677 }
 678
 679 static int
 680 dri2_drm_authenticate(_EGLDisplay *disp, uint32_t id)
 681 {
 682    struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
 683
 684    return drmAuthMagic(dri2_dpy->fd, id);
 685 }
 686
 687 EGLBoolean
 688 dri2_initialize_drm(_EGLDriver *drv, _EGLDisplay *disp)
 689 {
 690    struct dri2_egl_display *dri2_dpy;
 691    int i;
 692
 693    dri2_dpy = malloc(sizeof *dri2_dpy);
 694    if (!dri2_dpy)
 695       return _eglError(EGL_BAD_ALLOC, "eglInitialize");
 696
 697    memset(dri2_dpy, 0, sizeof *dri2_dpy);
 698
 699    disp->DriverData = (void *) dri2_dpy;
 700    dri2_dpy->fd = (int) (intptr_t) disp->PlatformDisplay;
 701
 702    dri2_dpy->driver_name = dri2_get_driver_for_fd(dri2_dpy->fd);
 703    if (dri2_dpy->driver_name == NULL)
 704       return _eglError(EGL_BAD_ALLOC, "DRI2: failed to get driver name");
 705
 706    dri2_dpy->device_name = dri2_get_device_name(dri2_dpy->fd);
 707    if (dri2_dpy->device_name == NULL) {
 708       _eglError(EGL_BAD_ALLOC, "DRI2: failed to get device name");
 709       goto cleanup_driver_name;
 710    }
 711
 712    if (!dri2_load_driver(disp))
 713       goto cleanup_device_name;
 714
 715    dri2_dpy->extensions[0] = &image_lookup_extension.base;
 716    dri2_dpy->extensions[1] = &use_invalidate.base;
 717    dri2_dpy->extensions[2] = NULL;
 718
 719    if (!dri2_create_screen(disp))
 720       goto cleanup_driver;
 721
 722    for (i = 0; dri2_dpy->driver_configs[i]; i++)
 723       dri2_add_config(disp, dri2_dpy->driver_configs[i], i + 1, 0, 0, NULL);
 724
 725 #ifdef HAVE_WAYLAND_PLATFORM
 726    disp->Extensions.WL_bind_wayland_display = EGL_TRUE;
 727 #endif
 728    dri2_dpy->authenticate = dri2_drm_authenticate;
 729
 730    /* we're supporting EGL 1.4 */
 731    disp->VersionMajor = 1;
 732    disp->VersionMinor = 4;
 733
 734    return EGL_TRUE;
 735
 736  cleanup_driver:
 737    dlclose(dri2_dpy->driver);
 738  cleanup_device_name:
 739    free(dri2_dpy->device_name);
 740  cleanup_driver_name:
 741    free(dri2_dpy->driver_name);
 742
 743    return EGL_FALSE;
 744 }
 745
 746 #endif