2 * Copyright (C) 2014-2015 Etnaviv Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Christian Gmeiner <christian.gmeiner@gmail.com>
27 #ifndef ETNAVIV_DRMIF_H_
28 #define ETNAVIV_DRMIF_H_
38 struct etna_cmd_stream
;
40 struct etna_perfmon_domain
;
41 struct etna_perfmon_signal
;
52 ETNA_GPU_REVISION
= 0x2,
53 ETNA_GPU_FEATURES_0
= 0x3,
54 ETNA_GPU_FEATURES_1
= 0x4,
55 ETNA_GPU_FEATURES_2
= 0x5,
56 ETNA_GPU_FEATURES_3
= 0x6,
57 ETNA_GPU_FEATURES_4
= 0x7,
58 ETNA_GPU_FEATURES_5
= 0x8,
59 ETNA_GPU_FEATURES_6
= 0x9,
60 ETNA_GPU_FEATURES_7
= 0xa,
62 ETNA_GPU_STREAM_COUNT
= 0x10,
63 ETNA_GPU_REGISTER_MAX
= 0x11,
64 ETNA_GPU_THREAD_COUNT
= 0x12,
65 ETNA_GPU_VERTEX_CACHE_SIZE
= 0x13,
66 ETNA_GPU_SHADER_CORE_COUNT
= 0x14,
67 ETNA_GPU_PIXEL_PIPES
= 0x15,
68 ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE
= 0x16,
69 ETNA_GPU_BUFFER_SIZE
= 0x17,
70 ETNA_GPU_INSTRUCTION_COUNT
= 0x18,
71 ETNA_GPU_NUM_CONSTANTS
= 0x19,
72 ETNA_GPU_NUM_VARYINGS
= 0x1a
76 #define DRM_ETNA_GEM_CACHE_CACHED 0x00010000
77 #define DRM_ETNA_GEM_CACHE_WC 0x00020000
78 #define DRM_ETNA_GEM_CACHE_UNCACHED 0x00040000
79 #define DRM_ETNA_GEM_CACHE_MASK 0x000f0000
81 #define DRM_ETNA_GEM_FORCE_MMU 0x00100000
83 /* bo access flags: (keep aligned to ETNA_PREP_x) */
84 #define DRM_ETNA_PREP_READ 0x01
85 #define DRM_ETNA_PREP_WRITE 0x02
86 #define DRM_ETNA_PREP_NOSYNC 0x04
91 struct etna_device
*etna_device_new(int fd
);
92 struct etna_device
*etna_device_new_dup(int fd
);
93 struct etna_device
*etna_device_ref(struct etna_device
*dev
);
94 void etna_device_del(struct etna_device
*dev
);
95 int etna_device_fd(struct etna_device
*dev
);
96 bool etnaviv_device_softpin_capable(struct etna_device
*dev
);
101 struct etna_gpu
*etna_gpu_new(struct etna_device
*dev
, unsigned int core
);
102 void etna_gpu_del(struct etna_gpu
*gpu
);
103 int etna_gpu_get_param(struct etna_gpu
*gpu
, enum etna_param_id param
,
110 struct etna_pipe
*etna_pipe_new(struct etna_gpu
*gpu
, enum etna_pipe_id id
);
111 void etna_pipe_del(struct etna_pipe
*pipe
);
112 int etna_pipe_wait(struct etna_pipe
*pipe
, uint32_t timestamp
, uint32_t ms
);
113 int etna_pipe_wait_ns(struct etna_pipe
*pipe
, uint32_t timestamp
, uint64_t ns
);
116 /* buffer-object functions:
119 struct etna_bo
*etna_bo_new(struct etna_device
*dev
,
120 uint32_t size
, uint32_t flags
);
121 struct etna_bo
*etna_bo_from_name(struct etna_device
*dev
, uint32_t name
);
122 struct etna_bo
*etna_bo_from_dmabuf(struct etna_device
*dev
, int fd
);
123 struct etna_bo
*etna_bo_ref(struct etna_bo
*bo
);
124 void etna_bo_del(struct etna_bo
*bo
);
125 int etna_bo_get_name(struct etna_bo
*bo
, uint32_t *name
);
126 uint32_t etna_bo_handle(struct etna_bo
*bo
);
127 int etna_bo_dmabuf(struct etna_bo
*bo
);
128 uint32_t etna_bo_size(struct etna_bo
*bo
);
129 uint32_t etna_bo_gpu_va(struct etna_bo
*bo
);
130 void * etna_bo_map(struct etna_bo
*bo
);
131 int etna_bo_cpu_prep(struct etna_bo
*bo
, uint32_t op
);
132 void etna_bo_cpu_fini(struct etna_bo
*bo
);
135 /* cmd stream functions:
138 struct etna_cmd_stream
{
140 uint32_t offset
; /* in 32-bit words */
141 uint32_t size
; /* in 32-bit words */
144 struct etna_cmd_stream
*etna_cmd_stream_new(struct etna_pipe
*pipe
, uint32_t size
,
145 void (*reset_notify
)(struct etna_cmd_stream
*stream
, void *priv
),
147 void etna_cmd_stream_del(struct etna_cmd_stream
*stream
);
148 uint32_t etna_cmd_stream_timestamp(struct etna_cmd_stream
*stream
);
149 void etna_cmd_stream_flush(struct etna_cmd_stream
*stream
, int in_fence_fd
,
151 void etna_cmd_stream_force_flush(struct etna_cmd_stream
*stream
);
153 static inline uint32_t etna_cmd_stream_avail(struct etna_cmd_stream
*stream
)
155 static const uint32_t END_CLEARANCE
= 2; /* LINK op code */
157 return stream
->size
- stream
->offset
- END_CLEARANCE
;
160 void etna_cmd_stream_realloc(struct etna_cmd_stream
*stream
, size_t n
);
162 static inline void etna_cmd_stream_reserve(struct etna_cmd_stream
*stream
, size_t n
)
164 if (etna_cmd_stream_avail(stream
) < n
)
165 etna_cmd_stream_realloc(stream
, n
);
168 static inline void etna_cmd_stream_emit(struct etna_cmd_stream
*stream
, uint32_t data
)
170 stream
->buffer
[stream
->offset
++] = data
;
173 static inline uint32_t etna_cmd_stream_get(struct etna_cmd_stream
*stream
, uint32_t offset
)
175 return stream
->buffer
[offset
];
178 static inline void etna_cmd_stream_set(struct etna_cmd_stream
*stream
, uint32_t offset
,
181 stream
->buffer
[offset
] = data
;
184 static inline uint32_t etna_cmd_stream_offset(struct etna_cmd_stream
*stream
)
186 return stream
->offset
;
191 #define ETNA_RELOC_READ 0x0001
192 #define ETNA_RELOC_WRITE 0x0002
197 void etna_cmd_stream_reloc(struct etna_cmd_stream
*stream
, const struct etna_reloc
*r
);
198 void etna_cmd_stream_ref_bo(struct etna_cmd_stream
*stream
,
199 struct etna_bo
*bo
, uint32_t flags
);
201 /* performance monitoring functions:
204 struct etna_perfmon
*etna_perfmon_create(struct etna_pipe
*pipe
);
205 void etna_perfmon_del(struct etna_perfmon
*perfmon
);
206 struct etna_perfmon_domain
*etna_perfmon_get_dom_by_name(struct etna_perfmon
*pm
, const char *name
);
207 struct etna_perfmon_signal
*etna_perfmon_get_sig_by_name(struct etna_perfmon_domain
*dom
, const char *name
);
210 #define ETNA_PM_PROCESS_PRE 0x0001
211 #define ETNA_PM_PROCESS_POST 0x0002
214 struct etna_perfmon_signal
*signal
;
219 void etna_cmd_stream_perf(struct etna_cmd_stream
*stream
, const struct etna_perf
*p
);
221 #endif /* ETNAVIV_DRMIF_H_ */