1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Elaboratable
5 from nmutil
.latch
import SRLatch
, latchregister
7 """ Computation Unit (aka "ALU Manager").
9 This module runs a "revolving door" set of three latches, based on
13 where one of them cannot be set on any given cycle.
14 (Note however that opc_l has been inverted (and qn used), due to SRLatch
15 default reset state being "0" rather than "1")
17 * When issue is first raised, a busy signal is sent out.
18 The src1 and src2 registers and the operand can be latched in
21 * Read request is set, which is ackowledged through the Scoreboard
22 to the priority picker, which generates (one and only one) Go_Read
23 at a time. One of those will (eventually) be this Computation Unit.
25 * Once Go_Read is set, the src1/src2/operand latch door shuts (locking
26 src1/src2/operand in place), and the ALU is told to proceed.
28 * As this is currently a "demo" unit, a countdown timer is activated
29 to simulate an ALU "pipeline", which activates "write request release",
30 and the ALU's output is captured into a temporary register.
32 * Write request release will go through a similar process as Read request,
33 resulting (eventually) in Go_Write being asserted.
35 * When Go_Write is asserted, two things happen: (1) the data in the temp
36 register is placed combinatorially onto the output, and (2) the
37 req_l latch is cleared, busy is dropped, and the Comp Unit is back
38 through its revolving door to do another task.
41 class ComputationUnitNoDelay(Elaboratable
):
42 def __init__(self
, rwid
, opwid
, alu
):
46 self
.counter
= Signal(4)
47 self
.go_rd_i
= Signal(reset_less
=True) # go read in
48 self
.go_wr_i
= Signal(reset_less
=True) # go write in
49 self
.issue_i
= Signal(reset_less
=True) # fn issue in
50 self
.shadown_i
= Signal(reset
=1) # shadow function, defaults to ON
51 self
.go_die_i
= Signal() # go die (reset)
53 self
.oper_i
= Signal(opwid
, reset_less
=True) # opcode in
54 self
.src1_i
= Signal(rwid
, reset_less
=True) # oper1 in
55 self
.src2_i
= Signal(rwid
, reset_less
=True) # oper2 in
57 self
.busy_o
= Signal(reset_less
=True) # fn busy out
58 self
.data_o
= Signal(rwid
, reset_less
=True) # Dest out
59 self
.rd_rel_o
= Signal(reset_less
=True) # release src1/src2 request
60 self
.req_rel_o
= Signal(reset_less
=True) # release request out (valid_o)
62 def elaborate(self
, platform
):
64 m
.submodules
.alu
= self
.alu
65 m
.submodules
.src_l
= src_l
= SRLatch(sync
=False)
66 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False)
67 m
.submodules
.req_l
= req_l
= SRLatch(sync
=False)
70 reset_w
= Signal(reset_less
=True)
71 reset_r
= Signal(reset_less
=True)
72 m
.d
.comb
+= reset_w
.eq(self
.go_wr_i | self
.go_die_i
)
73 m
.d
.comb
+= reset_r
.eq(self
.go_rd_i | self
.go_die_i
)
75 # This is fascinating and very important to observe that this
76 # is in effect a "3-way revolving door". At no time may all 3
77 # latches be set at the same time.
79 # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
80 m
.d
.sync
+= opc_l
.s
.eq(self
.issue_i
) # XXX NOTE: INVERTED FROM book!
81 m
.d
.sync
+= opc_l
.r
.eq(reset_w
) # XXX NOTE: INVERTED FROM book!
83 # src operand latch (not using go_wr_i)
84 m
.d
.sync
+= src_l
.s
.eq(self
.issue_i
)
85 m
.d
.sync
+= src_l
.r
.eq(reset_r
)
87 # dest operand latch (not using issue_i)
88 m
.d
.sync
+= req_l
.s
.eq(self
.go_rd_i
)
89 m
.d
.sync
+= req_l
.r
.eq(reset_w
)
92 # XXX NOTE: sync on req_rel_o and data_o due to simulation lock-up
96 m
.d
.comb
+= self
.busy_o
.eq(opc_l
.q
) # busy out
97 m
.d
.comb
+= self
.rd_rel_o
.eq(src_l
.q
& opc_l
.q
) # src1/src2 req rel
99 # the counter is just for demo purposes, to get the ALUs of different
100 # types to take arbitrary completion times
102 m
.d
.sync
+= self
.counter
.eq(0)
103 with m
.If(req_l
.qn
& opc_l
.q
& (self
.counter
== 0)):
104 with m
.If(self
.oper_i
== 2): # MUL, to take 5 instructions
105 m
.d
.sync
+= self
.counter
.eq(5)
106 with m
.Elif(self
.oper_i
== 3): # SHIFT to take 7
107 m
.d
.sync
+= self
.counter
.eq(7)
108 with m
.Else(): # ADD/SUB to take 2
109 m
.d
.sync
+= self
.counter
.eq(2)
110 with m
.If(self
.counter
> 1):
111 m
.d
.sync
+= self
.counter
.eq(self
.counter
- 1)
112 with m
.If(self
.counter
== 1):
113 # write req release out. waits until shadow is dropped.
114 m
.d
.comb
+= self
.req_rel_o
.eq(req_l
.q
& opc_l
.q
& self
.shadown_i
)
116 # create a latch/register for src1/src2
117 latchregister(m
, self
.src1_i
, self
.alu
.a
, src_l
.q
)
118 latchregister(m
, self
.src2_i
, self
.alu
.b
, src_l
.q
)
119 #with m.If(src_l.qn):
120 # m.d.comb += self.alu.op.eq(self.oper_i)
122 # create a latch/register for the operand
123 latchregister(m
, self
.oper_i
, self
.alu
.op
, src_l
.q
)
125 # and one for the output from the ALU
126 data_r
= Signal(self
.rwid
, reset_less
=True) # Dest register
127 latchregister(m
, self
.alu
.o
, data_r
, req_l
.q
)
129 with m
.If(self
.go_wr_i
):
130 m
.d
.comb
+= self
.data_o
.eq(data_r
)
134 def scoreboard_sim(dut
):
135 yield dut
.dest_i
.eq(1)
136 yield dut
.issue_i
.eq(1)
138 yield dut
.issue_i
.eq(0)
140 yield dut
.src1_i
.eq(1)
141 yield dut
.issue_i
.eq(1)
145 yield dut
.issue_i
.eq(0)
147 yield dut
.go_read_i
.eq(1)
149 yield dut
.go_read_i
.eq(0)
151 yield dut
.go_write_i
.eq(1)
153 yield dut
.go_write_i
.eq(0)
156 def test_scoreboard():
157 dut
= Scoreboard(32, 8)
158 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
159 with
open("test_scoreboard.il", "w") as f
:
162 run_simulation(dut
, scoreboard_sim(dut
), vcd_name
='test_scoreboard.vcd')
164 if __name__
== '__main__':