1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Mux
, Cat
, Elaboratable
5 from nmutil
.latch
import SRLatch
, latchregister
7 """ LOAD / STORE Computation Unit. Also capable of doing ADD and ADD immediate
9 This module runs a "revolving door" set of four latches, based on
13 * Go_Write *OR* Go_Store
15 (Note that opc_l has been inverted (and qn used), due to SRLatch
16 default reset state being "0" rather than "1")
19 # internal opcodes. hypothetically this could do more combinations.
21 # * bit 0: 0 = ADD , 1 = SUB
22 # * bit 1: 0 = src1, 1 = IMM
25 LDST_OP_ADDI
= 0b0000 # plain ADD (src1 + src2)
26 LDST_OP_SUBI
= 0b0001 # plain SUB (src1 - src2)
27 LDST_OP_ADD
= 0b0010 # immed ADD (imm + src1)
28 LDST_OP_SUB
= 0b0011 # immed SUB (imm - src1)
29 LDST_OP_ST
= 0b0110 # immed ADD plus LD op. ADD result is address
30 LDST_OP_LD
= 0b1010 # immed ADD plus ST op. ADD result is address
33 class LDSTCompUnit(Elaboratable
):
34 """ LOAD / STORE / ADD / SUB Computation Unit
39 * :rwid: register width
41 * :mem: a Memory Module (read-write capable)
46 * :issue_i: LD/ST is being "issued".
47 * :isalu_i: ADD/SUB is being "issued" (aka issue_alu_i)
48 * :shadown_i: Inverted-shadow is being held (stops STORE *and* WRITE)
49 * :go_rd_i: read is being actioned (latches in src regs)
50 * :go_ad_i: address is being actioned (triggers actual mem LD)
51 * :go_st_i: store is being actioned (triggers actual mem STORE)
52 * :go_die_i: resets the unit back to "wait for issue"
54 def __init__(self
, rwid
, opwid
, alu
, mem
):
59 self
.counter
= Signal(4)
60 self
.go_rd_i
= Signal(reset_less
=True) # go read in
61 self
.go_ad_i
= Signal(reset_less
=True) # go address in
62 self
.go_wr_i
= Signal(reset_less
=True) # go write in
63 self
.go_st_i
= Signal(reset_less
=True) # go store in
64 self
.issue_i
= Signal(reset_less
=True) # fn issue in
65 self
.isalu_i
= Signal(reset_less
=True) # fn issue as ALU in
66 self
.shadown_i
= Signal(reset
=1) # shadow function, defaults to ON
67 self
.go_die_i
= Signal() # go die (reset)
69 self
.oper_i
= Signal(opwid
, reset_less
=True) # opcode in
70 self
.imm_i
= Signal(rwid
, reset_less
=True) # immediate in
71 self
.src1_i
= Signal(rwid
, reset_less
=True) # oper1 in
72 self
.src2_i
= Signal(rwid
, reset_less
=True) # oper2 in
74 self
.busy_o
= Signal(reset_less
=True) # fn busy out
75 self
.rd_rel_o
= Signal(reset_less
=True) # request src1/src2
76 self
.adr_rel_o
= Signal(reset_less
=True) # request address (from mem)
77 self
.sto_rel_o
= Signal(reset_less
=True) # request store (to mem)
78 self
.req_rel_o
= Signal(reset_less
=True) # request write (result)
79 self
.data_o
= Signal(rwid
, reset_less
=True) # Dest out (LD or ALU)
80 self
.load_mem_o
= Signal(reset_less
=True) # activate memory LOAD
81 self
.stwd_mem_o
= Signal(reset_less
=True) # activate memory STORE
83 def elaborate(self
, platform
):
88 m
.submodules
.alu
= self
.alu
89 m
.submodules
.src_l
= src_l
= SRLatch(sync
=False)
90 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False)
91 m
.submodules
.adr_l
= adr_l
= SRLatch(sync
=False)
92 m
.submodules
.req_l
= req_l
= SRLatch(sync
=False)
93 m
.submodules
.sto_l
= sto_l
= SRLatch(sync
=False)
96 reset_b
= Signal(reset_less
=True)
97 reset_w
= Signal(reset_less
=True)
98 reset_a
= Signal(reset_less
=True)
99 reset_s
= Signal(reset_less
=True)
100 reset_r
= Signal(reset_less
=True)
101 comb
+= reset_b
.eq(self
.go_st_i | self
.go_wr_i | self
.go_die_i
)
102 comb
+= reset_w
.eq(self
.go_wr_i | self
.go_die_i
)
103 comb
+= reset_s
.eq(self
.go_st_i | self
.go_die_i
)
104 comb
+= reset_r
.eq(self
.go_rd_i | self
.go_die_i
)
105 # this one is slightly different, issue_alu_i selects go_wr_i)
106 a_sel
= Mux(self
.isalu_i
, self
.go_wr_i
, self
.go_ad_i
)
107 comb
+= reset_a
.eq(a_sel| self
.go_die_i
)
110 op_alu
= Signal(reset_less
=True)
111 op_is_ld
= Signal(reset_less
=True)
112 op_is_st
= Signal(reset_less
=True)
113 op_ldst
= Signal(reset_less
=True)
114 op_is_imm
= Signal(reset_less
=True)
116 comb
+= op_alu
.eq(self
.oper_i
[0])
117 comb
+= op_is_imm
.eq(self
.oper_i
[1])
118 comb
+= op_is_ld
.eq(self
.oper_i
[2])
119 comb
+= op_is_st
.eq(self
.oper_i
[3])
120 comb
+= op_ldst
.eq(op_is_ld | op_is_st
)
121 comb
+= self
.load_mem_o
.eq(op_is_ld
& self
.go_ad_i
)
122 comb
+= self
.stwd_mem_o
.eq(op_is_st
& self
.go_st_i
)
124 # select immediate or src2 reg to add
125 src2_or_imm
= Signal(self
.rwid
, reset_less
=True)
126 src_sel
= Signal(reset_less
=True)
128 # issue can be either issue_i or issue_alu_i (isalu_i)
129 issue_i
= Signal(reset_less
=True)
130 comb
+= issue_i
.eq(self
.issue_i | self
.isalu_i
)
132 # Ripple-down the latches, each one set cancels the previous.
133 # NOTE: use sync to stop combinatorial loops.
135 # opcode latch - inverted so that busy resets to 0
136 sync
+= opc_l
.s
.eq(issue_i
) # XXX NOTE: INVERTED FROM book!
137 sync
+= opc_l
.r
.eq(reset_b
) # XXX NOTE: INVERTED FROM book!
140 sync
+= src_l
.s
.eq(issue_i
)
141 sync
+= src_l
.r
.eq(reset_r
)
144 sync
+= adr_l
.s
.eq(self
.go_rd_i
)
145 sync
+= adr_l
.r
.eq(reset_a
)
148 sync
+= req_l
.s
.eq(self
.go_ad_i
)
149 sync
+= req_l
.r
.eq(reset_w
)
152 sync
+= sto_l
.s
.eq(self
.go_ad_i
)
153 sync
+= sto_l
.r
.eq(reset_s
)
155 # outputs: busy and release signals
157 comb
+= self
.busy_o
.eq(opc_l
.q
) # busy out
158 comb
+= self
.rd_rel_o
.eq(src_l
.q
& busy_o
) # src1/src2 req rel
159 comb
+= self
.sto_rel_o
.eq(sto_l
.q
& busy_o
& self
.shadown_i
)
161 # address release only happens on LD/ST, and is shadowed.
162 comb
+= self
.adr_rel_o
.eq(adr_l
.q
& op_ldst
& busy_o
& self
.shadown_i
)
164 # request release enabled based on if op is a LD/ST or a plain ALU
165 # if op is a LD/ST, req_rel activates from the *address* latch
166 # if op is ADD/SUB, req_rel activates from the *dest* latch
167 wr_q
= Signal(reset_less
=True)
168 comb
+= wr_q
.eq(Mux(op_ldst
, adr_l
.q
, req_l
.q
))
170 # the counter is just for demo purposes, to get the ALUs of different
171 # types to take arbitrary completion times
173 sync
+= self
.counter
.eq(0) # reset counter when not busy
174 with m
.If(req_l
.qn
& busy_o
& (self
.counter
== 0)):
175 sync
+= self
.counter
.eq(2) # take 2 (fake) cycles to respond
176 with m
.If(self
.counter
> 1):
177 sync
+= self
.counter
.eq(self
.counter
- 1)
178 with m
.If(self
.counter
== 1):
179 # write req release out. waits until shadow is dropped.
180 comb
+= self
.req_rel_o
.eq(wr_q
& busy_o
& self
.shadown_i
)
182 # select immediate if opcode says so. however also change the latch
183 # to trigger *from* the opcode latch instead.
184 comb
+= src_sel
.eq(Mux(op_is_imm
, opc_l
.qn
, src_l
.q
))
185 comb
+= src2_or_imm
.eq(Mux(op_is_imm
, self
.imm_i
, self
.src2_i
))
187 # create a latch/register for src1/src2 (include immediate select)
188 latchregister(m
, self
.src1_i
, self
.alu
.a
, src_l
.q
)
189 latchregister(m
, src2_or_imm
, self
.alu
.b
, src_sel
)
191 # create a latch/register for the operand
192 alu_op
= Cat(op_alu
, 0, op_is_imm
) # using alu_hier, here.
193 latchregister(m
, alu_op
, self
.alu
.op
, self
.issue_i
)
195 # and one for the output from the ALU
196 data_r
= Signal(self
.rwid
, reset_less
=True) # Dest register
197 latchregister(m
, self
.alu
.o
, data_r
, req_l
.q
)
199 with m
.If(self
.go_wr_i
):
200 comb
+= self
.data_o
.eq(data_r
)
223 yield self
.load_mem_o
224 yield self
.stwd_mem_o
230 def scoreboard_sim(dut
):
231 yield dut
.dest_i
.eq(1)
232 yield dut
.issue_i
.eq(1)
234 yield dut
.issue_i
.eq(0)
236 yield dut
.src1_i
.eq(1)
237 yield dut
.issue_i
.eq(1)
241 yield dut
.issue_i
.eq(0)
243 yield dut
.go_read_i
.eq(1)
245 yield dut
.go_read_i
.eq(0)
247 yield dut
.go_write_i
.eq(1)
249 yield dut
.go_write_i
.eq(0)
253 def test_scoreboard():
254 from alu_hier
import ALU
257 dut
= LDSTCompUnit(16, 4, alu
, mem
)
258 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
259 with
open("test_ldst_comp.il", "w") as f
:
262 run_simulation(dut
, scoreboard_sim(dut
), vcd_name
='test_ldst_comp.vcd')
264 if __name__
== '__main__':