src/freedreno/computerator/a6xx.c

   1 /*
   2  * Copyright © 2020 Google, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include "ir3/ir3_compiler.h"
  25
  26 #include "util/u_math.h"
  27
  28 #include "registers/adreno_pm4.xml.h"
  29 #include "registers/adreno_common.xml.h"
  30 #include "registers/a6xx.xml.h"
  31
  32 #include "main.h"
  33 #include "ir3_asm.h"
  34
  35 struct a6xx_backend {
  36         struct backend base;
  37
  38         struct ir3_compiler *compiler;
  39         struct fd_device *dev;
  40
  41         unsigned seqno;
  42         struct fd_bo *control_mem;
  43
  44         struct fd_bo *query_mem;
  45         const struct perfcntr *perfcntrs;
  46         unsigned num_perfcntrs;
  47 };
  48 define_cast(backend, a6xx_backend);
  49
  50 /*
  51  * Data structures shared with GPU:
  52  */
  53
  54 /* This struct defines the layout of the fd6_context::control buffer: */
  55 struct fd6_control {
  56         uint32_t seqno;          /* seqno for async CP_EVENT_WRITE, etc */
  57         uint32_t _pad0;
  58         volatile uint32_t vsc_overflow;
  59         uint32_t _pad1;
  60         /* flag set from cmdstream when VSC overflow detected: */
  61         uint32_t vsc_scratch;
  62         uint32_t _pad2;
  63         uint32_t _pad3;
  64         uint32_t _pad4;
  65
  66         /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
  67         struct {
  68                 uint32_t offset;
  69                 uint32_t pad[7];
  70         } flush_base[4];
  71 };
  72
  73 #define control_ptr(a6xx_backend, member)  \
  74         (a6xx_backend)->control_mem, offsetof(struct fd6_control, member), 0, 0
  75
  76
  77 struct PACKED fd6_query_sample {
  78         uint64_t start;
  79         uint64_t result;
  80         uint64_t stop;
  81 };
  82
  83
  84 /* offset of a single field of an array of fd6_query_sample: */
  85 #define query_sample_idx(a6xx_backend, idx, field)    \
  86         (a6xx_backend)->query_mem,                        \
  87         (idx * sizeof(struct fd6_query_sample)) +         \
  88         offsetof(struct fd6_query_sample, field),         \
  89         0, 0
  90
  91
  92 /*
  93  * Backend implementation:
  94  */
  95
  96 static struct kernel *
  97 a6xx_assemble(struct backend *b, FILE *in)
  98 {
  99         struct a6xx_backend *a6xx_backend = to_a6xx_backend(b);
 100         struct ir3_kernel *ir3_kernel =
 101                 ir3_asm_assemble(a6xx_backend->compiler, in);
 102         ir3_kernel->backend = b;
 103         return &ir3_kernel->base;
 104 }
 105
 106 static void
 107 a6xx_disassemble(struct kernel *kernel, FILE *out)
 108 {
 109         ir3_asm_disassemble(to_ir3_kernel(kernel), out);
 110 }
 111
 112 static void
 113 cs_program_emit(struct fd_ringbuffer *ring, struct kernel *kernel)
 114 {
 115         struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
 116         struct ir3_shader_variant *v = ir3_kernel->v;
 117         const struct ir3_info *i = &v->info;
 118         enum a3xx_threadsize thrsz = FOUR_QUADS;
 119
 120         OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
 121         OUT_RING(ring, 0xff);
 122
 123         unsigned constlen = align(v->constlen, 4);
 124         OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL, 1);
 125         OUT_RING(ring, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) |
 126                         A6XX_HLSQ_CS_CNTL_ENABLED);
 127
 128         OUT_PKT4(ring, REG_A6XX_SP_CS_CONFIG, 2);
 129         OUT_RING(ring, A6XX_SP_CS_CONFIG_ENABLED |
 130                 A6XX_SP_CS_CONFIG_NIBO(kernel->num_bufs) |
 131                 A6XX_SP_CS_CONFIG_NTEX(v->num_samp) |
 132                 A6XX_SP_CS_CONFIG_NSAMP(v->num_samp));    /* SP_VS_CONFIG */
 133         OUT_RING(ring, v->instrlen);                      /* SP_VS_INSTRLEN */
 134
 135         OUT_PKT4(ring, REG_A6XX_SP_CS_CTRL_REG0, 1);
 136         OUT_RING(ring, A6XX_SP_CS_CTRL_REG0_THREADSIZE(thrsz) |
 137                 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1) |
 138                 A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(i->max_half_reg + 1) |
 139                 COND(v->mergedregs, A6XX_SP_CS_CTRL_REG0_MERGEDREGS) |
 140                 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) |
 141                 COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE));
 142
 143         OUT_PKT4(ring, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
 144         OUT_RING(ring, 0x41);
 145
 146         uint32_t local_invocation_id, work_group_id;
 147         local_invocation_id = ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
 148         work_group_id = ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
 149
 150         OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL_0, 2);
 151         OUT_RING(ring, A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
 152                 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
 153                 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
 154                 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
 155         OUT_RING(ring, 0x2fc);             /* HLSQ_CS_UNKNOWN_B998 */
 156
 157         OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START_LO, 2);
 158         OUT_RELOC(ring, v->bo, 0, 0, 0);   /* SP_CS_OBJ_START_LO/HI */
 159
 160         OUT_PKT4(ring, REG_A6XX_SP_CS_INSTRLEN, 1);
 161         OUT_RING(ring, v->instrlen);
 162
 163         OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START_LO, 2);
 164         OUT_RELOC(ring, v->bo, 0, 0, 0);
 165
 166         OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3);
 167         OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
 168                 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
 169                 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
 170                 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER) |
 171                 CP_LOAD_STATE6_0_NUM_UNIT(v->instrlen));
 172         OUT_RELOC(ring, v->bo, 0, 0, 0);
 173 }
 174
 175 static void
 176 emit_const(struct fd_ringbuffer *ring, uint32_t regid,
 177                 uint32_t sizedwords, const uint32_t *dwords)
 178 {
 179         uint32_t align_sz;
 180
 181         debug_assert((regid % 4) == 0);
 182
 183         align_sz = align(sizedwords, 4);
 184
 185         OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3 + align_sz);
 186         OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
 187                 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
 188                 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
 189                 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER) |
 190                 CP_LOAD_STATE6_0_NUM_UNIT(DIV_ROUND_UP(sizedwords, 4)));
 191         OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
 192         OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
 193
 194         for (uint32_t i = 0; i < sizedwords; i++) {
 195                 OUT_RING(ring, dwords[i]);
 196         }
 197
 198         /* Zero-pad to multiple of 4 dwords */
 199         for (uint32_t i = sizedwords; i < align_sz; i++) {
 200                 OUT_RING(ring, 0);
 201         }
 202 }
 203
 204
 205 static void
 206 cs_const_emit(struct fd_ringbuffer *ring, struct kernel *kernel, uint32_t grid[3])
 207 {
 208         struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
 209         struct ir3_shader_variant *v = ir3_kernel->v;
 210
 211         const struct ir3_const_state *const_state = ir3_const_state(v);
 212         uint32_t base = const_state->offsets.immediate;
 213         int size = const_state->immediates_count;
 214
 215         if (ir3_kernel->info.numwg != INVALID_REG) {
 216                 assert((ir3_kernel->info.numwg & 0x3) == 0);
 217                 int idx = ir3_kernel->info.numwg >> 2;
 218                 const_state->immediates[idx].val[0] = grid[0];
 219                 const_state->immediates[idx].val[1] = grid[1];
 220                 const_state->immediates[idx].val[2] = grid[2];
 221         }
 222
 223         /* truncate size to avoid writing constants that shader
 224          * does not use:
 225          */
 226         size = MIN2(size + base, v->constlen) - base;
 227
 228         /* convert out of vec4: */
 229         base *= 4;
 230         size *= 4;
 231
 232         if (size > 0) {
 233                 emit_const(ring, base, size, const_state->immediates[0].val);
 234         }
 235 }
 236
 237 static void
 238 cs_ibo_emit(struct fd_ringbuffer *ring, struct fd_submit *submit,
 239                 struct kernel *kernel)
 240 {
 241         struct fd_ringbuffer *state =
 242                 fd_submit_new_ringbuffer(submit,
 243                                 kernel->num_bufs * 16 * 4,
 244                                 FD_RINGBUFFER_STREAMING);
 245
 246         for (unsigned i = 0; i < kernel->num_bufs; i++) {
 247                 /* size is encoded with low 15b in WIDTH and high bits in HEIGHT,
 248                  * in units of elements:
 249                  */
 250                 unsigned sz = kernel->buf_sizes[i];
 251                 unsigned width  = sz & MASK(15);
 252                 unsigned height = sz >> 15;
 253
 254                 OUT_RING(state, A6XX_IBO_0_FMT(FMT6_32_UINT) |
 255                         A6XX_IBO_0_TILE_MODE(0));
 256                 OUT_RING(state, A6XX_IBO_1_WIDTH(width) |
 257                         A6XX_IBO_1_HEIGHT(height));
 258                 OUT_RING(state, A6XX_IBO_2_PITCH(0) |
 259                         A6XX_IBO_2_UNK4 | A6XX_IBO_2_UNK31 |
 260                         A6XX_IBO_2_TYPE(A6XX_TEX_1D));
 261                 OUT_RING(state, A6XX_IBO_3_ARRAY_PITCH(0));
 262                 OUT_RELOC(state, kernel->bufs[i], 0, 0, 0);
 263                 OUT_RING(state, 0x00000000);
 264                 OUT_RING(state, 0x00000000);
 265                 OUT_RING(state, 0x00000000);
 266                 OUT_RING(state, 0x00000000);
 267                 OUT_RING(state, 0x00000000);
 268                 OUT_RING(state, 0x00000000);
 269                 OUT_RING(state, 0x00000000);
 270                 OUT_RING(state, 0x00000000);
 271                 OUT_RING(state, 0x00000000);
 272                 OUT_RING(state, 0x00000000);
 273         }
 274
 275         OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3);
 276         OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
 277                 CP_LOAD_STATE6_0_STATE_TYPE(ST6_IBO) |
 278                 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
 279                 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER) |
 280                 CP_LOAD_STATE6_0_NUM_UNIT(kernel->num_bufs));
 281         OUT_RB(ring, state);
 282
 283         OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_LO, 2);
 284         OUT_RB(ring, state);
 285
 286         OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
 287         OUT_RING(ring, kernel->num_bufs);
 288
 289         fd_ringbuffer_del(state);
 290 }
 291
 292 static inline unsigned
 293 event_write(struct fd_ringbuffer *ring, struct kernel *kernel,
 294                 enum vgt_event_type evt, bool timestamp)
 295 {
 296         unsigned seqno = 0;
 297
 298         OUT_PKT7(ring, CP_EVENT_WRITE, timestamp ? 4 : 1);
 299         OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(evt));
 300         if (timestamp) {
 301                 struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
 302                 struct a6xx_backend *a6xx_backend = to_a6xx_backend(ir3_kernel->backend);
 303                 seqno = ++a6xx_backend->seqno;
 304                 OUT_RELOC(ring, control_ptr(a6xx_backend, seqno));  /* ADDR_LO/HI */
 305                 OUT_RING(ring, seqno);
 306         }
 307
 308         return seqno;
 309 }
 310
 311 static inline void
 312 cache_flush(struct fd_ringbuffer *ring, struct kernel *kernel)
 313 {
 314         struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
 315         struct a6xx_backend *a6xx_backend = to_a6xx_backend(ir3_kernel->backend);
 316         unsigned seqno;
 317
 318         seqno = event_write(ring, kernel, RB_DONE_TS, true);
 319
 320         OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
 321         OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
 322                 CP_WAIT_REG_MEM_0_POLL_MEMORY);
 323         OUT_RELOC(ring, control_ptr(a6xx_backend, seqno));
 324         OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(seqno));
 325         OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(~0));
 326         OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
 327
 328         seqno = event_write(ring, kernel, CACHE_FLUSH_TS, true);
 329
 330         OUT_PKT7(ring, CP_WAIT_MEM_GTE, 4);
 331         OUT_RING(ring, CP_WAIT_MEM_GTE_0_RESERVED(0));
 332         OUT_RELOC(ring, control_ptr(a6xx_backend, seqno));
 333         OUT_RING(ring, CP_WAIT_MEM_GTE_3_REF(seqno));
 334 }
 335
 336 static void
 337 a6xx_emit_grid(struct kernel *kernel, uint32_t grid[3], struct fd_submit *submit)
 338 {
 339         struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
 340         struct a6xx_backend *a6xx_backend = to_a6xx_backend(ir3_kernel->backend);
 341         struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(submit, 0,
 342                         FD_RINGBUFFER_PRIMARY | FD_RINGBUFFER_GROWABLE);
 343
 344         cs_program_emit(ring, kernel);
 345         cs_const_emit(ring, kernel, grid);
 346         cs_ibo_emit(ring, submit, kernel);
 347
 348         OUT_PKT7(ring, CP_SET_MARKER, 1);
 349         OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
 350
 351         const unsigned *local_size = kernel->local_size;
 352         const unsigned *num_groups = grid;
 353
 354         unsigned work_dim = 0;
 355         for (int i = 0; i < 3; i++) {
 356                 if (!grid[i])
 357                         break;
 358                 work_dim++;
 359         }
 360
 361         OUT_PKT4(ring, REG_A6XX_HLSQ_CS_NDRANGE_0, 7);
 362         OUT_RING(ring, A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(work_dim) |
 363                 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) |
 364                 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) |
 365                 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1));
 366         OUT_RING(ring, A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(local_size[0] * num_groups[0]));
 367         OUT_RING(ring, 0);            /* HLSQ_CS_NDRANGE_2_GLOBALOFF_X */
 368         OUT_RING(ring, A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(local_size[1] * num_groups[1]));
 369         OUT_RING(ring, 0);            /* HLSQ_CS_NDRANGE_4_GLOBALOFF_Y */
 370         OUT_RING(ring, A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(local_size[2] * num_groups[2]));
 371         OUT_RING(ring, 0);            /* HLSQ_CS_NDRANGE_6_GLOBALOFF_Z */
 372
 373         OUT_PKT4(ring, REG_A6XX_HLSQ_CS_KERNEL_GROUP_X, 3);
 374         OUT_RING(ring, 1);            /* HLSQ_CS_KERNEL_GROUP_X */
 375         OUT_RING(ring, 1);            /* HLSQ_CS_KERNEL_GROUP_Y */
 376         OUT_RING(ring, 1);            /* HLSQ_CS_KERNEL_GROUP_Z */
 377
 378         if (a6xx_backend->num_perfcntrs > 0) {
 379                 a6xx_backend->query_mem = fd_bo_new(a6xx_backend->dev,
 380                         a6xx_backend->num_perfcntrs * sizeof(struct fd6_query_sample),
 381                         DRM_FREEDRENO_GEM_TYPE_KMEM, "query");
 382
 383                 /* configure the performance counters to count the requested
 384                  * countables:
 385                  */
 386                 for (unsigned i = 0; i < a6xx_backend->num_perfcntrs; i++) {
 387                         const struct perfcntr *counter = &a6xx_backend->perfcntrs[i];
 388
 389                         OUT_PKT4(ring, counter->select_reg, 1);
 390                         OUT_RING(ring, counter->selector);
 391                 }
 392
 393                 OUT_PKT7(ring, CP_WAIT_FOR_IDLE, 0);
 394
 395                 /* and snapshot the start values: */
 396                 for (unsigned i = 0; i < a6xx_backend->num_perfcntrs; i++) {
 397                         const struct perfcntr *counter = &a6xx_backend->perfcntrs[i];
 398
 399                         OUT_PKT7(ring, CP_REG_TO_MEM, 3);
 400                         OUT_RING(ring, CP_REG_TO_MEM_0_64B |
 401                                 CP_REG_TO_MEM_0_REG(counter->counter_reg_lo));
 402                         OUT_RELOC(ring, query_sample_idx(a6xx_backend, i, start));
 403                 }
 404         }
 405
 406         OUT_PKT7(ring, CP_EXEC_CS, 4);
 407         OUT_RING(ring, 0x00000000);
 408         OUT_RING(ring, CP_EXEC_CS_1_NGROUPS_X(grid[0]));
 409         OUT_RING(ring, CP_EXEC_CS_2_NGROUPS_Y(grid[1]));
 410         OUT_RING(ring, CP_EXEC_CS_3_NGROUPS_Z(grid[2]));
 411
 412         OUT_PKT7(ring, CP_WAIT_FOR_IDLE, 0);
 413
 414         if (a6xx_backend->num_perfcntrs > 0) {
 415                 /* snapshot the end values: */
 416                 for (unsigned i = 0; i < a6xx_backend->num_perfcntrs; i++) {
 417                         const struct perfcntr *counter = &a6xx_backend->perfcntrs[i];
 418
 419                         OUT_PKT7(ring, CP_REG_TO_MEM, 3);
 420                         OUT_RING(ring, CP_REG_TO_MEM_0_64B |
 421                                 CP_REG_TO_MEM_0_REG(counter->counter_reg_lo));
 422                         OUT_RELOC(ring, query_sample_idx(a6xx_backend, i, stop));
 423                 }
 424
 425                 /* and compute the result: */
 426                 for (unsigned i = 0; i < a6xx_backend->num_perfcntrs; i++) {
 427                         /* result += stop - start: */
 428                         OUT_PKT7(ring, CP_MEM_TO_MEM, 9);
 429                         OUT_RING(ring, CP_MEM_TO_MEM_0_DOUBLE |
 430                                         CP_MEM_TO_MEM_0_NEG_C);
 431                         OUT_RELOC(ring, query_sample_idx(a6xx_backend, i, result));     /* dst */
 432                         OUT_RELOC(ring, query_sample_idx(a6xx_backend, i, result));      /* srcA */
 433                         OUT_RELOC(ring, query_sample_idx(a6xx_backend, i, stop));        /* srcB */
 434                         OUT_RELOC(ring, query_sample_idx(a6xx_backend, i, start));       /* srcC */
 435                 }
 436         }
 437
 438         cache_flush(ring, kernel);
 439 }
 440
 441 static void
 442 a6xx_set_perfcntrs(struct backend *b, const struct perfcntr *perfcntrs,
 443                 unsigned num_perfcntrs)
 444 {
 445         struct a6xx_backend *a6xx_backend = to_a6xx_backend(b);
 446
 447         a6xx_backend->perfcntrs = perfcntrs;
 448         a6xx_backend->num_perfcntrs = num_perfcntrs;
 449 }
 450
 451 static void
 452 a6xx_read_perfcntrs(struct backend *b, uint64_t *results)
 453 {
 454         struct a6xx_backend *a6xx_backend = to_a6xx_backend(b);
 455
 456         fd_bo_cpu_prep(a6xx_backend->query_mem, NULL, DRM_FREEDRENO_PREP_READ);
 457         struct fd6_query_sample *samples = fd_bo_map(a6xx_backend->query_mem);
 458
 459         for (unsigned i = 0; i < a6xx_backend->num_perfcntrs; i++) {
 460                 results[i] = samples[i].result;
 461         }
 462 }
 463
 464 struct backend *
 465 a6xx_init(struct fd_device *dev, uint32_t gpu_id)
 466 {
 467         struct a6xx_backend *a6xx_backend = calloc(1, sizeof(*a6xx_backend));
 468
 469         a6xx_backend->base = (struct backend) {
 470                 .assemble = a6xx_assemble,
 471                 .disassemble = a6xx_disassemble,
 472                 .emit_grid = a6xx_emit_grid,
 473                 .set_perfcntrs = a6xx_set_perfcntrs,
 474                 .read_perfcntrs = a6xx_read_perfcntrs,
 475         };
 476
 477         a6xx_backend->compiler = ir3_compiler_create(dev, gpu_id);
 478         a6xx_backend->dev = dev;
 479
 480         a6xx_backend->control_mem = fd_bo_new(dev, 0x1000,
 481                 DRM_FREEDRENO_GEM_TYPE_KMEM, "control");
 482
 483         return &a6xx_backend->base;
 484 }