2 * Copyright (C) 2018 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018-2019 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
30 #include "freedreno_layout.h"
33 is_r8g8(struct fdl_layout
*layout
)
35 return layout
->cpp
== 2 &&
36 util_format_get_nr_components(layout
->format
) == 2;
40 fdl6_get_ubwc_blockwidth(struct fdl_layout
*layout
,
41 uint32_t *blockwidth
, uint32_t *blockheight
)
47 { 16, 4 }, /* cpp = 1 */
48 { 16, 4 }, /* cpp = 2 */
49 { 16, 4 }, /* cpp = 4 */
50 { 8, 4, }, /* cpp = 8 */
51 { 4, 4, }, /* cpp = 16 */
52 { 4, 2 }, /* cpp = 32 */
53 { 0, 0 }, /* cpp = 64 (TODO) */
56 /* special case for r8g8: */
57 if (is_r8g8(layout
)) {
63 uint32_t cpp
= fdl_cpp_shift(layout
);
64 assert(cpp
< ARRAY_SIZE(blocksize
));
65 *blockwidth
= blocksize
[cpp
].width
;
66 *blockheight
= blocksize
[cpp
].height
;
70 fdl6_tile_alignment(struct fdl_layout
*layout
, uint32_t *heightalign
)
72 layout
->pitchalign
= fdl_cpp_shift(layout
);
75 if (is_r8g8(layout
) || layout
->cpp
== 1) {
76 layout
->pitchalign
= 1;
78 } else if (layout
->cpp
== 2) {
79 layout
->pitchalign
= 2;
82 /* note: this base_align is *probably* not always right,
83 * it doesn't really get tested. for example with UBWC we might
84 * want 4k alignment, since we align UBWC levels to 4k
87 layout
->base_align
= 64;
88 else if (layout
->cpp
== 2)
89 layout
->base_align
= 128;
91 layout
->base_align
= 256;
94 /* NOTE: good way to test this is: (for example)
95 * piglit/bin/texelFetch fs sampler3D 100x100x8
98 fdl6_layout(struct fdl_layout
*layout
,
99 enum pipe_format format
, uint32_t nr_samples
,
100 uint32_t width0
, uint32_t height0
, uint32_t depth0
,
101 uint32_t mip_levels
, uint32_t array_size
, bool is_3d
,
102 struct fdl_explicit_layout
*explicit_layout
)
104 uint32_t offset
= 0, heightalign
;
105 uint32_t ubwc_blockwidth
, ubwc_blockheight
;
107 assert(nr_samples
> 0);
108 layout
->width0
= width0
;
109 layout
->height0
= height0
;
110 layout
->depth0
= depth0
;
112 layout
->cpp
= util_format_get_blocksize(format
);
113 layout
->cpp
*= nr_samples
;
114 layout
->cpp_shift
= ffs(layout
->cpp
) - 1;
116 layout
->format
= format
;
117 layout
->nr_samples
= nr_samples
;
118 layout
->layer_first
= !is_3d
;
120 fdl6_get_ubwc_blockwidth(layout
, &ubwc_blockwidth
, &ubwc_blockheight
);
122 if (depth0
> 1 || ubwc_blockwidth
== 0)
123 layout
->ubwc
= false;
125 /* in layer_first layout, the level (slice) contains just one
126 * layer (since in fact the layer contains the slices)
128 uint32_t layers_in_level
= layout
->layer_first
? 1 : array_size
;
130 /* note: for tiled+noubwc layouts, we can use a lower pitchalign
131 * which will affect the linear levels only, (the hardware will still
132 * expect the tiled alignment on the tiled levels)
134 if (layout
->tile_mode
) {
135 fdl6_tile_alignment(layout
, &heightalign
);
137 layout
->base_align
= 64;
138 layout
->pitchalign
= 0;
139 /* align pitch to at least 16 pixels:
140 * both turnip and galium assume there is enough alignment for 16x4
141 * aligned gmem store. turnip can use CP_BLIT to work without this
142 * extra alignment, but gallium driver doesn't implement it yet
145 layout
->pitchalign
= fdl_cpp_shift(layout
) - 2;
147 /* when possible, use a bit more alignment than necessary
148 * presumably this is better for performance?
150 if (!explicit_layout
)
151 layout
->pitchalign
= fdl_cpp_shift(layout
);
153 /* not used, avoid "may be used uninitialized" warning */
157 fdl_set_pitchalign(layout
, layout
->pitchalign
+ 6);
159 if (explicit_layout
) {
160 offset
= explicit_layout
->offset
;
161 layout
->pitch0
= explicit_layout
->pitch
;
162 if (align(layout
->pitch0
, 1 << layout
->pitchalign
) != layout
->pitch0
)
166 uint32_t ubwc_width0
= width0
;
167 uint32_t ubwc_height0
= height0
;
168 uint32_t ubwc_tile_height_alignment
= RGB_TILE_HEIGHT_ALIGNMENT
;
169 if (mip_levels
> 1) {
170 /* With mipmapping enabled, UBWC layout is power-of-two sized,
171 * specified in log2 width/height in the descriptors. The height
172 * alignment is 64 for mipmapping, but for buffer sharing (always
173 * single level) other participants expect 16.
175 ubwc_width0
= util_next_power_of_two(width0
);
176 ubwc_height0
= util_next_power_of_two(height0
);
177 ubwc_tile_height_alignment
= 64;
179 layout
->ubwc_width0
= align(DIV_ROUND_UP(ubwc_width0
, ubwc_blockwidth
),
180 RGB_TILE_WIDTH_ALIGNMENT
);
181 ubwc_height0
= align(DIV_ROUND_UP(ubwc_height0
, ubwc_blockheight
),
182 ubwc_tile_height_alignment
);
184 for (uint32_t level
= 0; level
< mip_levels
; level
++) {
185 uint32_t depth
= u_minify(depth0
, level
);
186 struct fdl_slice
*slice
= &layout
->slices
[level
];
187 struct fdl_slice
*ubwc_slice
= &layout
->ubwc_slices
[level
];
188 uint32_t tile_mode
= fdl_tile_mode(layout
, level
);
189 uint32_t pitch
= fdl_pitch(layout
, level
);
192 /* tiled levels of 3D textures are rounded up to PoT dimensions: */
193 if (is_3d
&& tile_mode
) {
194 height
= u_minify(util_next_power_of_two(height0
), level
);
196 height
= u_minify(height0
, level
);
199 uint32_t nblocksy
= util_format_get_nblocksy(format
, height
);
201 nblocksy
= align(nblocksy
, heightalign
);
203 /* The blits used for mem<->gmem work at a granularity of
204 * 16x4, which can cause faults due to over-fetch on the
205 * last level. The simple solution is to over-allocate a
206 * bit the last level to ensure any over-fetch is harmless.
207 * The pitch is already sufficiently aligned, but height
208 * may not be. note this only matters if last level is linear
210 if (level
== mip_levels
- 1)
211 height
= align(nblocksy
, 4);
213 slice
->offset
= offset
+ layout
->size
;
215 /* 1d array and 2d array textures must all have the same layer size
216 * for each miplevel on a6xx. 3d textures can have different layer
217 * sizes for high levels, but the hw auto-sizer is buggy (or at least
218 * different than what this code does), so as soon as the layer size
219 * range gets into range, we stop reducing it.
222 if (level
< 1 || layout
->slices
[level
- 1].size0
> 0xf000) {
223 slice
->size0
= align(nblocksy
* pitch
, 4096);
225 slice
->size0
= layout
->slices
[level
- 1].size0
;
228 slice
->size0
= nblocksy
* pitch
;
231 layout
->size
+= slice
->size0
* depth
* layers_in_level
;
234 /* with UBWC every level is aligned to 4K */
235 layout
->size
= align(layout
->size
, 4096);
237 uint32_t meta_pitch
= fdl_ubwc_pitch(layout
, level
);
238 uint32_t meta_height
= align(u_minify(ubwc_height0
, level
),
239 ubwc_tile_height_alignment
);
241 ubwc_slice
->size0
= align(meta_pitch
* meta_height
, UBWC_PLANE_SIZE_ALIGNMENT
);
242 ubwc_slice
->offset
= offset
+ layout
->ubwc_layer_size
;
243 layout
->ubwc_layer_size
+= ubwc_slice
->size0
;
247 if (layout
->layer_first
) {
248 layout
->layer_size
= align(layout
->size
, 4096);
249 layout
->size
= layout
->layer_size
* array_size
;
252 /* Place the UBWC slices before the uncompressed slices, because the
253 * kernel expects UBWC to be at the start of the buffer. In the HW, we
254 * get to program the UBWC and non-UBWC offset/strides
258 for (uint32_t level
= 0; level
< mip_levels
; level
++)
259 layout
->slices
[level
].offset
+= layout
->ubwc_layer_size
* array_size
;
260 layout
->size
+= layout
->ubwc_layer_size
* array_size
;
263 /* include explicit offset in size */
264 layout
->size
+= offset
;