2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include <util/u_debug.h>
34 #include "instr-a3xx.h"
37 static enum debug_t debug
;
39 #define printf debug_printf
41 static const char *levels
[] = {
60 static const char *component
= "xyzw";
62 static const char *type
[] = {
78 struct shader_stats
*stats
;
80 /* we have to process the dst register after src to avoid tripping up
81 * the read-before-write detection
87 /* current instruction repeat flag: */
89 /* current instruction repeat indx/offset (for --expand): */
92 /* tracking for register usage */
95 regmask_t used_merged
;
96 regmask_t rbw
; /* read before write */
97 regmask_t war
; /* write after read */
102 static const char *float_imms
[] = {
117 static void print_reg(struct disasm_ctx
*ctx
, reg_t reg
, bool full
,
118 bool is_float
, bool r
,
119 bool c
, bool im
, bool neg
, bool abs
, bool addr_rel
)
121 const char type
= c
? 'c' : 'r';
123 // XXX I prefer - and || for neg/abs, but preserving format used
124 // by libllvm-a3xx for easy diffing..
127 fprintf(ctx
->out
, "(absneg)");
129 fprintf(ctx
->out
, "(neg)");
131 fprintf(ctx
->out
, "(abs)");
134 fprintf(ctx
->out
, "(r)");
137 if (is_float
&& full
&& reg
.iim_val
< ARRAY_SIZE(float_imms
)) {
138 fprintf(ctx
->out
, "(%s)", float_imms
[reg
.iim_val
]);
140 fprintf(ctx
->out
, "%d", reg
.iim_val
);
142 } else if (addr_rel
) {
143 /* I would just use %+d but trying to make it diff'able with
147 fprintf(ctx
->out
, "%s%c<a0.x - %d>", full
? "" : "h", type
, -reg
.iim_val
);
148 else if (reg
.iim_val
> 0)
149 fprintf(ctx
->out
, "%s%c<a0.x + %d>", full
? "" : "h", type
, reg
.iim_val
);
151 fprintf(ctx
->out
, "%s%c<a0.x>", full
? "" : "h", type
);
152 } else if ((reg
.num
== REG_A0
) && !c
) {
153 /* This matches libllvm output, the second (scalar) address register
154 * seems to be called a1.x instead of a0.y.
156 fprintf(ctx
->out
, "a%d.x", reg
.comp
);
157 } else if ((reg
.num
== REG_P0
) && !c
) {
158 fprintf(ctx
->out
, "p0.%c", component
[reg
.comp
]);
160 fprintf(ctx
->out
, "%s%c%d.%c", full
? "" : "h", type
, reg
.num
, component
[reg
.comp
]);
161 if (0 && full
&& !c
) {
166 fprintf(ctx
->out
, " (hr%d.%c,hr%d.%c)", hr0
.num
, component
[hr0
.comp
], hr1
.num
, component
[hr1
.comp
]);
171 static void regmask_set(regmask_t
*regmask
, unsigned num
, bool full
)
173 ir3_assert(num
< MAX_REG
);
174 __regmask_set(regmask
, !full
, num
);
177 static void regmask_clear(regmask_t
*regmask
, unsigned num
, bool full
)
179 ir3_assert(num
< MAX_REG
);
180 __regmask_clear(regmask
, !full
, num
);
183 static unsigned regmask_get(regmask_t
*regmask
, unsigned num
, bool full
)
185 ir3_assert(num
< MAX_REG
);
186 return __regmask_get(regmask
, !full
, num
);
189 static unsigned regidx(reg_t reg
)
191 return (4 * reg
.num
) + reg
.comp
;
194 static reg_t
idxreg(unsigned idx
)
202 static void print_sequence(struct disasm_ctx
*ctx
, int first
, int last
)
204 if (first
!= MAX_REG
) {
206 fprintf(ctx
->out
, " %d", first
);
208 fprintf(ctx
->out
, " %d-%d", first
, last
);
213 static int print_regs(struct disasm_ctx
*ctx
, regmask_t
*regmask
, bool full
)
215 int num
, max
= 0, cnt
= 0;
218 first
= last
= MAX_REG
;
220 for (num
= 0; num
< MAX_REG
; num
++) {
221 if (regmask_get(regmask
, num
, full
)) {
222 if (num
!= (last
+ 1)) {
223 print_sequence(ctx
, first
, last
);
233 print_sequence(ctx
, first
, last
);
235 fprintf(ctx
->out
, " (cnt=%d, max=%d)", cnt
, max
);
240 static void print_reg_stats(struct disasm_ctx
*ctx
)
242 int fullreg
, halfreg
;
244 fprintf(ctx
->out
, "%sRegister Stats:\n", levels
[ctx
->level
]);
245 fprintf(ctx
->out
, "%s- used (half):", levels
[ctx
->level
]);
246 halfreg
= print_regs(ctx
, &ctx
->regs
.used
, false);
247 fprintf(ctx
->out
, "\n");
248 fprintf(ctx
->out
, "%s- used (full):", levels
[ctx
->level
]);
249 fullreg
= print_regs(ctx
, &ctx
->regs
.used
, true);
250 fprintf(ctx
->out
, "\n");
251 if (ctx
->gpu_id
>= 600) {
252 fprintf(ctx
->out
, "%s- used (merged):", levels
[ctx
->level
]);
253 print_regs(ctx
, &ctx
->regs
.used_merged
, false);
254 fprintf(ctx
->out
, "\n");
256 fprintf(ctx
->out
, "%s- input (half):", levels
[ctx
->level
]);
257 print_regs(ctx
, &ctx
->regs
.rbw
, false);
258 fprintf(ctx
->out
, "\n");
259 fprintf(ctx
->out
, "%s- input (full):", levels
[ctx
->level
]);
260 print_regs(ctx
, &ctx
->regs
.rbw
, true);
261 fprintf(ctx
->out
, "\n");
262 fprintf(ctx
->out
, "%s- max const: %u\n", levels
[ctx
->level
], ctx
->regs
.max_const
);
263 fprintf(ctx
->out
, "\n");
264 fprintf(ctx
->out
, "%s- output (half):", levels
[ctx
->level
]);
265 print_regs(ctx
, &ctx
->regs
.war
, false);
266 fprintf(ctx
->out
, " (estimated)\n");
267 fprintf(ctx
->out
, "%s- output (full):", levels
[ctx
->level
]);
268 print_regs(ctx
, &ctx
->regs
.war
, true);
269 fprintf(ctx
->out
, " (estimated)\n");
271 /* convert to vec4, which is the granularity that registers are
272 * assigned to shader:
274 fullreg
= (fullreg
+ 3) / 4;
275 halfreg
= (halfreg
+ 3) / 4;
277 // Note this count of instructions includes rptN, which matches
278 // up to how mesa prints this:
279 fprintf(ctx
->out
, "%s- shaderdb: %d instructions, %d nops, %d non-nops, "
280 "(%d instlen), %d half, %d full\n",
281 levels
[ctx
->level
], ctx
->stats
->instructions
, ctx
->stats
->nops
,
282 ctx
->stats
->instructions
- ctx
->stats
->nops
, ctx
->stats
->instlen
,
284 fprintf(ctx
->out
, "%s- shaderdb: %d (ss), %d (sy)\n", levels
[ctx
->level
],
285 ctx
->stats
->ss
, ctx
->stats
->sy
);
288 static void process_reg_dst(struct disasm_ctx
*ctx
)
290 if (!ctx
->last_dst_valid
)
293 /* ignore dummy writes (ie. r63.x): */
294 if (!VALIDREG(ctx
->last_dst
))
297 for (unsigned i
= 0; i
<= ctx
->repeat
; i
++) {
298 unsigned dst
= ctx
->last_dst
+ i
;
300 regmask_set(&ctx
->regs
.war
, dst
, ctx
->last_dst_full
);
301 regmask_set(&ctx
->regs
.used
, dst
, ctx
->last_dst_full
);
303 if (ctx
->gpu_id
>= 600) {
304 if (ctx
->last_dst_full
) {
305 regmask_set(&ctx
->regs
.used_merged
, (dst
*2)+0, false);
306 regmask_set(&ctx
->regs
.used_merged
, (dst
*2)+1, false);
308 regmask_set(&ctx
->regs
.used_merged
, dst
, false);
313 ctx
->last_dst_valid
= false;
315 static void print_reg_dst(struct disasm_ctx
*ctx
, reg_t reg
, bool full
, bool addr_rel
)
317 /* presumably the special registers a0.c and p0.c don't count.. */
318 if (!(addr_rel
|| (reg
.num
== REG_A0
) || (reg
.num
== REG_P0
))) {
319 ctx
->last_dst
= regidx(reg
);
320 ctx
->last_dst_full
= full
;
321 ctx
->last_dst_valid
= true;
323 reg
= idxreg(regidx(reg
) + ctx
->repeatidx
);
324 print_reg(ctx
, reg
, full
, false, false, false, false, false, false, addr_rel
);
327 /* TODO switch to using reginfo struct everywhere, since more readable
328 * than passing a bunch of bools to print_reg_src
336 bool f
; /* src reg is interpreted as float, used for printing immediates */
343 static void print_src(struct disasm_ctx
*ctx
, struct reginfo
*info
)
345 reg_t reg
= info
->reg
;
347 /* presumably the special registers a0.c and p0.c don't count.. */
348 if (!(info
->addr_rel
|| info
->c
|| info
->im
||
349 (reg
.num
== REG_A0
) || (reg
.num
== REG_P0
))) {
350 int i
, num
= regidx(reg
);
351 for (i
= 0; i
<= ctx
->repeat
; i
++) {
352 unsigned src
= num
+ i
;
354 if (!regmask_get(&ctx
->regs
.used
, src
, info
->full
))
355 regmask_set(&ctx
->regs
.rbw
, src
, info
->full
);
357 regmask_clear(&ctx
->regs
.war
, src
, info
->full
);
358 regmask_set(&ctx
->regs
.used
, src
, info
->full
);
361 regmask_set(&ctx
->regs
.used_merged
, (src
*2)+0, false);
362 regmask_set(&ctx
->regs
.used_merged
, (src
*2)+1, false);
364 regmask_set(&ctx
->regs
.used_merged
, src
, false);
370 } else if (info
->c
) {
371 int i
, num
= regidx(reg
);
372 for (i
= 0; i
<= ctx
->repeat
; i
++) {
373 unsigned src
= num
+ i
;
375 ctx
->regs
.max_const
= MAX2(ctx
->regs
.max_const
, src
);
381 unsigned max
= (num
+ ctx
->repeat
+ 1 + 3) / 4;
382 if (max
> ctx
->stats
->constlen
)
383 ctx
->stats
->constlen
= max
;
387 reg
= idxreg(regidx(info
->reg
) + ctx
->repeatidx
);
389 print_reg(ctx
, reg
, info
->full
, info
->f
, info
->r
, info
->c
, info
->im
,
390 info
->neg
, info
->abs
, info
->addr_rel
);
393 //static void print_dst(struct disasm_ctx *ctx, struct reginfo *info)
395 // print_reg_dst(ctx, info->reg, info->full, info->addr_rel);
398 static void print_instr_cat0(struct disasm_ctx
*ctx
, instr_t
*instr
)
400 static const struct {
405 [BRANCH_PLAIN
] = { "r", 1, false },
406 [BRANCH_OR
] = { "rao", 2, false },
407 [BRANCH_AND
] = { "raa", 2, false },
408 [BRANCH_CONST
] = { "rac", 0, true },
409 [BRANCH_ANY
] = { "any", 1, false },
410 [BRANCH_ALL
] = { "all", 1, false },
411 [BRANCH_X
] = { "rax", 0, false },
413 instr_cat0_t
*cat0
= &instr
->cat0
;
415 switch (instr_opc(instr
, ctx
->gpu_id
)) {
419 fprintf(ctx
->out
, " %sp0.%c", cat0
->inv0
? "!" : "",
420 component
[cat0
->comp0
]);
423 fprintf(ctx
->out
, "%s", brinfo
[cat0
->brtype
].suffix
);
424 if (brinfo
[cat0
->brtype
].idx
) {
425 fprintf(ctx
->out
, ".%u", cat0
->idx
);
427 if (brinfo
[cat0
->brtype
].nsrc
>= 1) {
428 fprintf(ctx
->out
, " %sp0.%c,", cat0
->inv0
? "!" : "",
429 component
[cat0
->comp0
]);
431 if (brinfo
[cat0
->brtype
].nsrc
>= 2) {
432 fprintf(ctx
->out
, " %sp0.%c,", cat0
->inv1
? "!" : "",
433 component
[cat0
->comp1
]);
435 fprintf(ctx
->out
, " #%d", cat0
->a3xx
.immed
);
442 fprintf(ctx
->out
, " #%d", cat0
->a3xx
.immed
);
446 if ((debug
& PRINT_VERBOSE
) && (cat0
->dummy3
|cat0
->dummy4
))
447 fprintf(ctx
->out
, "\t{0: %x,%x}", cat0
->dummy3
, cat0
->dummy4
);
450 static void print_instr_cat1(struct disasm_ctx
*ctx
, instr_t
*instr
)
452 instr_cat1_t
*cat1
= &instr
->cat1
;
455 fprintf(ctx
->out
, "(ul)");
457 if (cat1
->src_type
== cat1
->dst_type
) {
458 if ((cat1
->src_type
== TYPE_S16
) && (((reg_t
)cat1
->dst
).num
== REG_A0
)) {
459 /* special case (nmemonic?): */
460 fprintf(ctx
->out
, "mova");
462 fprintf(ctx
->out
, "mov.%s%s", type
[cat1
->src_type
], type
[cat1
->dst_type
]);
465 fprintf(ctx
->out
, "cov.%s%s", type
[cat1
->src_type
], type
[cat1
->dst_type
]);
468 fprintf(ctx
->out
, " ");
471 fprintf(ctx
->out
, "(even)");
474 fprintf(ctx
->out
, "(pos_infinity)");
476 print_reg_dst(ctx
, (reg_t
)(cat1
->dst
), type_size(cat1
->dst_type
) == 32,
479 fprintf(ctx
->out
, ", ");
481 /* ugg, have to special case this.. vs print_reg().. */
483 if (type_float(cat1
->src_type
))
484 fprintf(ctx
->out
, "(%f)", cat1
->fim_val
);
485 else if (type_uint(cat1
->src_type
))
486 fprintf(ctx
->out
, "0x%08x", cat1
->uim_val
);
488 fprintf(ctx
->out
, "%d", cat1
->iim_val
);
489 } else if (cat1
->src_rel
&& !cat1
->src_c
) {
490 /* I would just use %+d but trying to make it diff'able with
493 char type
= cat1
->src_rel_c
? 'c' : 'r';
494 const char *full
= (type_size(cat1
->src_type
) == 32) ? "" : "h";
496 fprintf(ctx
->out
, "%s%c<a0.x - %d>", full
, type
, -cat1
->off
);
497 else if (cat1
->off
> 0)
498 fprintf(ctx
->out
, "%s%c<a0.x + %d>", full
, type
, cat1
->off
);
500 fprintf(ctx
->out
, "%s%c<a0.x>", full
, type
);
502 struct reginfo src
= {
503 .reg
= (reg_t
)cat1
->src
,
504 .full
= type_size(cat1
->src_type
) == 32,
509 print_src(ctx
, &src
);
512 if ((debug
& PRINT_VERBOSE
) && (cat1
->must_be_0
))
513 fprintf(ctx
->out
, "\t{1: %x}", cat1
->must_be_0
);
516 static void print_instr_cat2(struct disasm_ctx
*ctx
, instr_t
*instr
)
518 instr_cat2_t
*cat2
= &instr
->cat2
;
519 int opc
= _OPC(2, cat2
->opc
);
520 static const char *cond
[] = {
537 fprintf(ctx
->out
, ".%s", cond
[cat2
->cond
]);
541 fprintf(ctx
->out
, " ");
543 fprintf(ctx
->out
, "(ei)");
544 print_reg_dst(ctx
, (reg_t
)(cat2
->dst
), cat2
->full
^ cat2
->dst_half
, false);
545 fprintf(ctx
->out
, ", ");
547 struct reginfo src1
= {
549 .r
= cat2
->repeat
? cat2
->src1_r
: 0,
550 .f
= is_cat2_float(opc
),
552 .abs
= cat2
->src1_abs
,
553 .neg
= cat2
->src1_neg
,
556 if (cat2
->c1
.src1_c
) {
557 src1
.reg
= (reg_t
)(cat2
->c1
.src1
);
559 } else if (cat2
->rel1
.src1_rel
) {
560 src1
.reg
= (reg_t
)(cat2
->rel1
.src1
);
561 src1
.c
= cat2
->rel1
.src1_c
;
562 src1
.addr_rel
= true;
564 src1
.reg
= (reg_t
)(cat2
->src1
);
566 print_src(ctx
, &src1
);
568 struct reginfo src2
= {
569 .r
= cat2
->repeat
? cat2
->src2_r
: 0,
571 .f
= is_cat2_float(opc
),
572 .abs
= cat2
->src2_abs
,
573 .neg
= cat2
->src2_neg
,
591 /* these only have one src reg */
594 fprintf(ctx
->out
, ", ");
595 if (cat2
->c2
.src2_c
) {
596 src2
.reg
= (reg_t
)(cat2
->c2
.src2
);
598 } else if (cat2
->rel2
.src2_rel
) {
599 src2
.reg
= (reg_t
)(cat2
->rel2
.src2
);
600 src2
.c
= cat2
->rel2
.src2_c
;
601 src2
.addr_rel
= true;
603 src2
.reg
= (reg_t
)(cat2
->src2
);
605 print_src(ctx
, &src2
);
610 static void print_instr_cat3(struct disasm_ctx
*ctx
, instr_t
*instr
)
612 instr_cat3_t
*cat3
= &instr
->cat3
;
613 bool full
= instr_cat3_full(cat3
);
615 fprintf(ctx
->out
, " ");
616 print_reg_dst(ctx
, (reg_t
)(cat3
->dst
), full
^ cat3
->dst_half
, false);
617 fprintf(ctx
->out
, ", ");
619 struct reginfo src1
= {
620 .r
= cat3
->repeat
? cat3
->src1_r
: 0,
622 .neg
= cat3
->src1_neg
,
624 if (cat3
->c1
.src1_c
) {
625 src1
.reg
= (reg_t
)(cat3
->c1
.src1
);
627 } else if (cat3
->rel1
.src1_rel
) {
628 src1
.reg
= (reg_t
)(cat3
->rel1
.src1
);
629 src1
.c
= cat3
->rel1
.src1_c
;
630 src1
.addr_rel
= true;
632 src1
.reg
= (reg_t
)(cat3
->src1
);
634 print_src(ctx
, &src1
);
636 fprintf(ctx
->out
, ", ");
637 struct reginfo src2
= {
638 .reg
= (reg_t
)cat3
->src2
,
640 .r
= cat3
->repeat
? cat3
->src2_r
: 0,
642 .neg
= cat3
->src2_neg
,
644 print_src(ctx
, &src2
);
646 fprintf(ctx
->out
, ", ");
647 struct reginfo src3
= {
650 .neg
= cat3
->src3_neg
,
652 if (cat3
->c2
.src3_c
) {
653 src3
.reg
= (reg_t
)(cat3
->c2
.src3
);
655 } else if (cat3
->rel2
.src3_rel
) {
656 src3
.reg
= (reg_t
)(cat3
->rel2
.src3
);
657 src3
.c
= cat3
->rel2
.src3_c
;
658 src3
.addr_rel
= true;
660 src3
.reg
= (reg_t
)(cat3
->src3
);
662 print_src(ctx
, &src3
);
665 static void print_instr_cat4(struct disasm_ctx
*ctx
, instr_t
*instr
)
667 instr_cat4_t
*cat4
= &instr
->cat4
;
669 fprintf(ctx
->out
, " ");
670 print_reg_dst(ctx
, (reg_t
)(cat4
->dst
), cat4
->full
^ cat4
->dst_half
, false);
671 fprintf(ctx
->out
, ", ");
673 struct reginfo src
= {
677 .neg
= cat4
->src_neg
,
678 .abs
= cat4
->src_abs
,
681 src
.reg
= (reg_t
)(cat4
->c
.src
);
683 } else if (cat4
->rel
.src_rel
) {
684 src
.reg
= (reg_t
)(cat4
->rel
.src
);
685 src
.c
= cat4
->rel
.src_c
;
688 src
.reg
= (reg_t
)(cat4
->src
);
690 print_src(ctx
, &src
);
692 if ((debug
& PRINT_VERBOSE
) && (cat4
->dummy1
|cat4
->dummy2
))
693 fprintf(ctx
->out
, "\t{4: %x,%x}", cat4
->dummy1
, cat4
->dummy2
);
696 static void print_instr_cat5(struct disasm_ctx
*ctx
, instr_t
*instr
)
698 static const struct {
699 bool src1
, src2
, samp
, tex
;
701 [opc_op(OPC_ISAM
)] = { true, false, true, true, },
702 [opc_op(OPC_ISAML
)] = { true, true, true, true, },
703 [opc_op(OPC_ISAMM
)] = { true, false, true, true, },
704 [opc_op(OPC_SAM
)] = { true, false, true, true, },
705 [opc_op(OPC_SAMB
)] = { true, true, true, true, },
706 [opc_op(OPC_SAML
)] = { true, true, true, true, },
707 [opc_op(OPC_SAMGQ
)] = { true, false, true, true, },
708 [opc_op(OPC_GETLOD
)] = { true, false, true, true, },
709 [opc_op(OPC_CONV
)] = { true, true, true, true, },
710 [opc_op(OPC_CONVM
)] = { true, true, true, true, },
711 [opc_op(OPC_GETSIZE
)] = { true, false, false, true, },
712 [opc_op(OPC_GETBUF
)] = { false, false, false, true, },
713 [opc_op(OPC_GETPOS
)] = { true, false, false, true, },
714 [opc_op(OPC_GETINFO
)] = { false, false, false, true, },
715 [opc_op(OPC_DSX
)] = { true, false, false, false, },
716 [opc_op(OPC_DSY
)] = { true, false, false, false, },
717 [opc_op(OPC_GATHER4R
)] = { true, false, true, true, },
718 [opc_op(OPC_GATHER4G
)] = { true, false, true, true, },
719 [opc_op(OPC_GATHER4B
)] = { true, false, true, true, },
720 [opc_op(OPC_GATHER4A
)] = { true, false, true, true, },
721 [opc_op(OPC_SAMGP0
)] = { true, false, true, true, },
722 [opc_op(OPC_SAMGP1
)] = { true, false, true, true, },
723 [opc_op(OPC_SAMGP2
)] = { true, false, true, true, },
724 [opc_op(OPC_SAMGP3
)] = { true, false, true, true, },
725 [opc_op(OPC_DSXPP_1
)] = { true, false, false, false, },
726 [opc_op(OPC_DSYPP_1
)] = { true, false, false, false, },
727 [opc_op(OPC_RGETPOS
)] = { true, false, false, false, },
728 [opc_op(OPC_RGETINFO
)] = { false, false, false, false, },
731 static const struct {
736 } desc_features
[8] = {
737 [CAT5_NONUNIFORM
] = { .indirect
= true, },
738 [CAT5_UNIFORM
] = { .indirect
= true, .uniform
= true, },
739 [CAT5_BINDLESS_IMM
] = { .bindless
= true, },
740 [CAT5_BINDLESS_UNIFORM
] = {
745 [CAT5_BINDLESS_NONUNIFORM
] = {
749 [CAT5_BINDLESS_A1_IMM
] = {
753 [CAT5_BINDLESS_A1_UNIFORM
] = {
759 [CAT5_BINDLESS_A1_NONUNIFORM
] = {
766 instr_cat5_t
*cat5
= &instr
->cat5
;
770 cat5
->is_s2en_bindless
&&
771 desc_features
[cat5
->s2en_bindless
.desc_mode
].indirect
;
773 cat5
->is_s2en_bindless
&&
774 desc_features
[cat5
->s2en_bindless
.desc_mode
].bindless
;
776 cat5
->is_s2en_bindless
&&
777 desc_features
[cat5
->s2en_bindless
.desc_mode
].use_a1
;
779 cat5
->is_s2en_bindless
&&
780 desc_features
[cat5
->s2en_bindless
.desc_mode
].uniform
;
782 if (cat5
->is_3d
) fprintf(ctx
->out
, ".3d");
783 if (cat5
->is_a
) fprintf(ctx
->out
, ".a");
784 if (cat5
->is_o
) fprintf(ctx
->out
, ".o");
785 if (cat5
->is_p
) fprintf(ctx
->out
, ".p");
786 if (cat5
->is_s
) fprintf(ctx
->out
, ".s");
787 if (desc_indirect
) fprintf(ctx
->out
, ".s2en");
788 if (uniform
) fprintf(ctx
->out
, ".uniform");
791 unsigned base
= (cat5
->s2en_bindless
.base_hi
<< 1) | cat5
->base_lo
;
792 fprintf(ctx
->out
, ".base%d", base
);
795 fprintf(ctx
->out
, " ");
797 switch (_OPC(5, cat5
->opc
)) {
802 fprintf(ctx
->out
, "(%s)", type
[cat5
->type
]);
806 fprintf(ctx
->out
, "(");
807 for (i
= 0; i
< 4; i
++)
808 if (cat5
->wrmask
& (1 << i
))
809 fprintf(ctx
->out
, "%c", "xyzw"[i
]);
810 fprintf(ctx
->out
, ")");
812 print_reg_dst(ctx
, (reg_t
)(cat5
->dst
), type_size(cat5
->type
) == 32, false);
814 if (info
[cat5
->opc
].src1
) {
815 fprintf(ctx
->out
, ", ");
816 struct reginfo src
= { .reg
= (reg_t
)(cat5
->src1
), .full
= cat5
->full
};
817 print_src(ctx
, &src
);
820 if (cat5
->is_o
|| info
[cat5
->opc
].src2
) {
821 fprintf(ctx
->out
, ", ");
822 struct reginfo src
= { .reg
= (reg_t
)(cat5
->src2
), .full
= cat5
->full
};
823 print_src(ctx
, &src
);
825 if (cat5
->is_s2en_bindless
) {
826 if (!desc_indirect
) {
827 if (info
[cat5
->opc
].samp
) {
829 fprintf(ctx
->out
, ", s#%d", cat5
->s2en_bindless
.src3
);
831 fprintf(ctx
->out
, ", s#%d", cat5
->s2en_bindless
.src3
& 0xf);
834 if (info
[cat5
->opc
].tex
&& !use_a1
) {
835 fprintf(ctx
->out
, ", t#%d", cat5
->s2en_bindless
.src3
>> 4);
839 if (info
[cat5
->opc
].samp
)
840 fprintf(ctx
->out
, ", s#%d", cat5
->norm
.samp
);
841 if (info
[cat5
->opc
].tex
)
842 fprintf(ctx
->out
, ", t#%d", cat5
->norm
.tex
);
846 fprintf(ctx
->out
, ", ");
847 struct reginfo src
= { .reg
= (reg_t
)(cat5
->s2en_bindless
.src3
), .full
= bindless
};
848 print_src(ctx
, &src
);
852 fprintf(ctx
->out
, ", a1.x");
854 if (debug
& PRINT_VERBOSE
) {
855 if (cat5
->is_s2en_bindless
) {
856 if ((debug
& PRINT_VERBOSE
) && cat5
->s2en_bindless
.dummy1
)
857 fprintf(ctx
->out
, "\t{5: %x}", cat5
->s2en_bindless
.dummy1
);
859 if ((debug
& PRINT_VERBOSE
) && cat5
->norm
.dummy1
)
860 fprintf(ctx
->out
, "\t{5: %x}", cat5
->norm
.dummy1
);
865 static void print_instr_cat6_a3xx(struct disasm_ctx
*ctx
, instr_t
*instr
)
867 instr_cat6_t
*cat6
= &instr
->cat6
;
868 char sd
= 0, ss
= 0; /* dst/src address space */
870 struct reginfo dst
, src1
, src2
, ssbo
;
873 memset(&dst
, 0, sizeof(dst
));
874 memset(&src1
, 0, sizeof(src1
));
875 memset(&src2
, 0, sizeof(src2
));
876 memset(&ssbo
, 0, sizeof(ssbo
));
878 switch (_OPC(6, cat6
->opc
)) {
881 dst
.full
= type_size(cat6
->type
) == 32;
882 src1
.full
= type_size(cat6
->type
) == 32;
883 src2
.full
= type_size(cat6
->type
) == 32;
896 dst
.full
= type_size(cat6
->type
) == 32;
897 src1
.full
= type_size(cat6
->type
) == 32;
898 src2
.full
= type_size(cat6
->type
) == 32;
901 dst
.full
= type_size(cat6
->type
) == 32;
907 switch (_OPC(6, cat6
->opc
)) {
911 fprintf(ctx
->out
, ".%dd", cat6
->ldgb
.d
+ 1);
914 fprintf(ctx
->out
, ".%s", cat6
->ldgb
.typed
? "typed" : "untyped");
915 fprintf(ctx
->out
, ".%dd", cat6
->ldgb
.d
+ 1);
916 fprintf(ctx
->out
, ".%s", type
[cat6
->type
]);
917 fprintf(ctx
->out
, ".%d", cat6
->ldgb
.type_size
+ 1);
921 fprintf(ctx
->out
, ".%s", cat6
->stgb
.typed
? "typed" : "untyped");
922 fprintf(ctx
->out
, ".%dd", cat6
->stgb
.d
+ 1);
923 fprintf(ctx
->out
, ".%s", type
[cat6
->type
]);
924 fprintf(ctx
->out
, ".%d", cat6
->stgb
.type_size
+ 1);
928 case OPC_ATOMIC_XCHG
:
931 case OPC_ATOMIC_CMPXCHG
:
937 ss
= cat6
->g
? 'g' : 'l';
938 fprintf(ctx
->out
, ".%s", cat6
->ldgb
.typed
? "typed" : "untyped");
939 fprintf(ctx
->out
, ".%dd", cat6
->ldgb
.d
+ 1);
940 fprintf(ctx
->out
, ".%s", type
[cat6
->type
]);
941 fprintf(ctx
->out
, ".%d", cat6
->ldgb
.type_size
+ 1);
942 fprintf(ctx
->out
, ".%c", ss
);
945 dst
.im
= cat6
->g
&& !cat6
->dst_off
;
946 fprintf(ctx
->out
, ".%s", type
[cat6
->type
]);
949 fprintf(ctx
->out
, " ");
951 switch (_OPC(6, cat6
->opc
)) {
992 if ((_OPC(6, cat6
->opc
) == OPC_STGB
) || (_OPC(6, cat6
->opc
) == OPC_STIB
)) {
995 memset(&src3
, 0, sizeof(src3
));
997 src1
.reg
= (reg_t
)(cat6
->stgb
.src1
);
998 src2
.reg
= (reg_t
)(cat6
->stgb
.src2
);
999 src2
.im
= cat6
->stgb
.src2_im
;
1000 src3
.reg
= (reg_t
)(cat6
->stgb
.src3
);
1001 src3
.im
= cat6
->stgb
.src3_im
;
1004 fprintf(ctx
->out
, "g[%u], ", cat6
->stgb
.dst_ssbo
);
1005 print_src(ctx
, &src1
);
1006 fprintf(ctx
->out
, ", ");
1007 print_src(ctx
, &src2
);
1008 fprintf(ctx
->out
, ", ");
1009 print_src(ctx
, &src3
);
1011 if (debug
& PRINT_VERBOSE
)
1012 fprintf(ctx
->out
, " (pad0=%x, pad3=%x)", cat6
->stgb
.pad0
, cat6
->stgb
.pad3
);
1017 if (is_atomic(_OPC(6, cat6
->opc
))) {
1019 src1
.reg
= (reg_t
)(cat6
->ldgb
.src1
);
1020 src1
.im
= cat6
->ldgb
.src1_im
;
1021 src2
.reg
= (reg_t
)(cat6
->ldgb
.src2
);
1022 src2
.im
= cat6
->ldgb
.src2_im
;
1023 dst
.reg
= (reg_t
)(cat6
->ldgb
.dst
);
1025 print_src(ctx
, &dst
);
1026 fprintf(ctx
->out
, ", ");
1028 struct reginfo src3
;
1029 memset(&src3
, 0, sizeof(src3
));
1031 src3
.reg
= (reg_t
)(cat6
->ldgb
.src3
);
1034 /* For images, the ".typed" variant is used and src2 is
1035 * the ivecN coordinates, ie ivec2 for 2d.
1037 * For SSBOs, the ".untyped" variant is used and src2 is
1038 * a simple dword offset.. src3 appears to be
1039 * uvec2(offset * 4, 0). Not sure the point of that.
1042 fprintf(ctx
->out
, "g[%u], ", cat6
->ldgb
.src_ssbo
);
1043 print_src(ctx
, &src1
); /* value */
1044 fprintf(ctx
->out
, ", ");
1045 print_src(ctx
, &src2
); /* offset/coords */
1046 fprintf(ctx
->out
, ", ");
1047 print_src(ctx
, &src3
); /* 64b byte offset.. */
1049 if (debug
& PRINT_VERBOSE
) {
1050 fprintf(ctx
->out
, " (pad0=%x, mustbe0=%x)", cat6
->ldgb
.pad0
,
1051 cat6
->ldgb
.mustbe0
);
1053 } else { /* ss == 'l' */
1054 fprintf(ctx
->out
, "l[");
1055 print_src(ctx
, &src1
); /* simple byte offset */
1056 fprintf(ctx
->out
, "], ");
1057 print_src(ctx
, &src2
); /* value */
1059 if (debug
& PRINT_VERBOSE
) {
1060 fprintf(ctx
->out
, " (src3=%x, pad0=%x, src_ssbo_im=%x, mustbe0=%x)",
1061 cat6
->ldgb
.src3
, cat6
->ldgb
.pad0
,
1062 cat6
->ldgb
.src_ssbo_im
, cat6
->ldgb
.mustbe0
);
1067 } else if (_OPC(6, cat6
->opc
) == OPC_RESINFO
) {
1068 dst
.reg
= (reg_t
)(cat6
->ldgb
.dst
);
1069 ssbo
.reg
= (reg_t
)(cat6
->ldgb
.src_ssbo
);
1070 ssbo
.im
= cat6
->ldgb
.src_ssbo_im
;
1072 print_src(ctx
, &dst
);
1073 fprintf(ctx
->out
, ", ");
1075 fprintf(ctx
->out
, "g[");
1076 print_src(ctx
, &ssbo
);
1077 fprintf(ctx
->out
, "]");
1080 } else if (_OPC(6, cat6
->opc
) == OPC_LDGB
) {
1082 src1
.reg
= (reg_t
)(cat6
->ldgb
.src1
);
1083 src1
.im
= cat6
->ldgb
.src1_im
;
1084 src2
.reg
= (reg_t
)(cat6
->ldgb
.src2
);
1085 src2
.im
= cat6
->ldgb
.src2_im
;
1086 ssbo
.reg
= (reg_t
)(cat6
->ldgb
.src_ssbo
);
1087 ssbo
.im
= cat6
->ldgb
.src_ssbo_im
;
1088 dst
.reg
= (reg_t
)(cat6
->ldgb
.dst
);
1090 print_src(ctx
, &dst
);
1091 fprintf(ctx
->out
, ", ");
1093 fprintf(ctx
->out
, "g[");
1094 print_src(ctx
, &ssbo
);
1095 fprintf(ctx
->out
, "], ");
1097 print_src(ctx
, &src1
);
1098 fprintf(ctx
->out
, ", ");
1099 print_src(ctx
, &src2
);
1101 if (debug
& PRINT_VERBOSE
)
1102 fprintf(ctx
->out
, " (pad0=%x, ssbo_im=%x, mustbe0=%x)", cat6
->ldgb
.pad0
, cat6
->ldgb
.src_ssbo_im
, cat6
->ldgb
.mustbe0
);
1105 } else if (_OPC(6, cat6
->opc
) == OPC_LDG
&& cat6
->a
.src1_im
&& cat6
->a
.src2_im
) {
1106 struct reginfo src3
;
1108 memset(&src3
, 0, sizeof(src3
));
1109 src1
.reg
= (reg_t
)(cat6
->a
.src1
);
1110 src2
.reg
= (reg_t
)(cat6
->a
.src2
);
1111 src2
.im
= cat6
->a
.src2_im
;
1112 src3
.reg
= (reg_t
)(cat6
->a
.off
);
1114 dst
.reg
= (reg_t
)(cat6
->d
.dst
);
1116 print_src(ctx
, &dst
);
1117 fprintf(ctx
->out
, ", g[");
1118 print_src(ctx
, &src1
);
1119 fprintf(ctx
->out
, "+");
1120 print_src(ctx
, &src3
);
1121 fprintf(ctx
->out
, "], ");
1122 print_src(ctx
, &src2
);
1127 if (cat6
->src_off
) {
1128 src1
.reg
= (reg_t
)(cat6
->a
.src1
);
1129 src1
.im
= cat6
->a
.src1_im
;
1130 src2
.reg
= (reg_t
)(cat6
->a
.src2
);
1131 src2
.im
= cat6
->a
.src2_im
;
1132 src1off
= cat6
->a
.off
;
1134 src1
.reg
= (reg_t
)(cat6
->b
.src1
);
1135 src1
.im
= cat6
->b
.src1_im
;
1136 src2
.reg
= (reg_t
)(cat6
->b
.src2
);
1137 src2
.im
= cat6
->b
.src2_im
;
1142 fprintf(ctx
->out
, "%c[", sd
);
1143 /* note: dst might actually be a src (ie. address to store to) */
1144 if (cat6
->dst_off
) {
1145 dst
.reg
= (reg_t
)(cat6
->c
.dst
);
1146 print_src(ctx
, &dst
);
1148 struct reginfo dstoff_reg
= {
1149 .reg
= (reg_t
) cat6
->c
.off
,
1152 fprintf(ctx
->out
, "+");
1153 print_src(ctx
, &dstoff_reg
);
1154 } else if (cat6
->c
.off
|| cat6
->c
.off_high
) {
1155 fprintf(ctx
->out
, "%+d", ((uint32_t)cat6
->c
.off_high
<< 8) | cat6
->c
.off
);
1158 dst
.reg
= (reg_t
)(cat6
->d
.dst
);
1159 print_src(ctx
, &dst
);
1162 fprintf(ctx
->out
, "]");
1163 fprintf(ctx
->out
, ", ");
1167 fprintf(ctx
->out
, "%c[", ss
);
1169 /* can have a larger than normal immed, so hack: */
1171 fprintf(ctx
->out
, "%u", src1
.reg
.dummy13
);
1173 print_src(ctx
, &src1
);
1176 if (cat6
->src_off
&& cat6
->g
)
1177 print_src(ctx
, &src2
);
1179 fprintf(ctx
->out
, "%+d", src1off
);
1181 fprintf(ctx
->out
, "]");
1183 switch (_OPC(6, cat6
->opc
)) {
1188 fprintf(ctx
->out
, ", ");
1189 print_src(ctx
, &src2
);
1194 static void print_instr_cat6_a6xx(struct disasm_ctx
*ctx
, instr_t
*instr
)
1196 instr_cat6_a6xx_t
*cat6
= &instr
->cat6_a6xx
;
1197 struct reginfo src1
, src2
, ssbo
;
1198 uint32_t opc
= _OPC(6, cat6
->opc
);
1199 bool uses_type
= opc
!= OPC_LDC
;
1201 static const struct {
1205 } desc_features
[8] = {
1213 [CAT6_NONUNIFORM
] = {
1215 .name
= "nonuniform"
1217 [CAT6_BINDLESS_IMM
] = {
1221 [CAT6_BINDLESS_UNIFORM
] = {
1226 [CAT6_BINDLESS_NONUNIFORM
] = {
1229 .name
= "nonuniform"
1233 bool indirect_ssbo
= desc_features
[cat6
->desc_mode
].indirect
;
1234 bool bindless
= desc_features
[cat6
->desc_mode
].bindless
;
1235 bool type_full
= cat6
->type
!= TYPE_U16
;
1238 memset(&src1
, 0, sizeof(src1
));
1239 memset(&src2
, 0, sizeof(src2
));
1240 memset(&ssbo
, 0, sizeof(ssbo
));
1243 fprintf(ctx
->out
, ".%s", cat6
->typed
? "typed" : "untyped");
1244 fprintf(ctx
->out
, ".%dd", cat6
->d
+ 1);
1245 fprintf(ctx
->out
, ".%s", type
[cat6
->type
]);
1247 fprintf(ctx
->out
, ".offset%d", cat6
->d
);
1249 fprintf(ctx
->out
, ".%u", cat6
->type_size
+ 1);
1251 fprintf(ctx
->out
, ".%s", desc_features
[cat6
->desc_mode
].name
);
1253 fprintf(ctx
->out
, ".base%d", cat6
->base
);
1254 fprintf(ctx
->out
, " ");
1256 src2
.reg
= (reg_t
)(cat6
->src2
);
1257 src2
.full
= type_full
;
1258 print_src(ctx
, &src2
);
1259 fprintf(ctx
->out
, ", ");
1261 if (opc
!= OPC_RESINFO
) {
1262 src1
.reg
= (reg_t
)(cat6
->src1
);
1263 src1
.full
= true; // XXX
1264 print_src(ctx
, &src1
);
1265 fprintf(ctx
->out
, ", ");
1268 ssbo
.reg
= (reg_t
)(cat6
->ssbo
);
1269 ssbo
.im
= !indirect_ssbo
;
1271 print_src(ctx
, &ssbo
);
1273 if (debug
& PRINT_VERBOSE
) {
1274 fprintf(ctx
->out
, " (pad1=%x, pad2=%x, pad3=%x, pad4=%x, pad5=%x)",
1275 cat6
->pad1
, cat6
->pad2
, cat6
->pad3
, cat6
->pad4
, cat6
->pad5
);
1279 static void print_instr_cat6(struct disasm_ctx
*ctx
, instr_t
*instr
)
1281 if (!is_cat6_legacy(instr
, ctx
->gpu_id
)) {
1282 print_instr_cat6_a6xx(ctx
, instr
);
1283 if (debug
& PRINT_VERBOSE
)
1284 fprintf(ctx
->out
, " NEW");
1286 print_instr_cat6_a3xx(ctx
, instr
);
1287 if (debug
& PRINT_VERBOSE
)
1288 fprintf(ctx
->out
, " LEGACY");
1291 static void print_instr_cat7(struct disasm_ctx
*ctx
, instr_t
*instr
)
1293 instr_cat7_t
*cat7
= &instr
->cat7
;
1296 fprintf(ctx
->out
, ".g");
1298 fprintf(ctx
->out
, ".l");
1300 if (_OPC(7, cat7
->opc
) == OPC_FENCE
) {
1302 fprintf(ctx
->out
, ".r");
1304 fprintf(ctx
->out
, ".w");
1308 /* size of largest OPC field of all the instruction categories: */
1311 static const struct opc_info
{
1315 void (*print
)(struct disasm_ctx
*ctx
, instr_t
*instr
);
1316 } opcs
[1 << (3+NOPC_BITS
)] = {
1317 #define OPC(cat, opc, name) [(opc)] = { (cat), (opc), #name, print_instr_cat##cat }
1319 OPC(0, OPC_NOP
, nop
),
1321 OPC(0, OPC_JUMP
, jump
),
1322 OPC(0, OPC_CALL
, call
),
1323 OPC(0, OPC_RET
, ret
),
1324 OPC(0, OPC_KILL
, kill
),
1325 OPC(0, OPC_END
, end
),
1326 OPC(0, OPC_EMIT
, emit
),
1327 OPC(0, OPC_CUT
, cut
),
1328 OPC(0, OPC_CHMASK
, chmask
),
1329 OPC(0, OPC_CHSH
, chsh
),
1330 OPC(0, OPC_FLOW_REV
, flow_rev
),
1331 OPC(0, OPC_PREDT
, predt
),
1332 OPC(0, OPC_PREDF
, predf
),
1333 OPC(0, OPC_PREDE
, prede
),
1334 OPC(0, OPC_BKT
, bkt
),
1335 OPC(0, OPC_STKS
, stks
),
1336 OPC(0, OPC_STKR
, stkr
),
1337 OPC(0, OPC_XSET
, xset
),
1338 OPC(0, OPC_XCLR
, xclr
),
1339 OPC(0, OPC_GETONE
, getone
),
1340 OPC(0, OPC_DBG
, dbg
),
1341 OPC(0, OPC_SHPS
, shps
),
1342 OPC(0, OPC_SHPE
, shpe
),
1348 OPC(2, OPC_ADD_F
, add
.f
),
1349 OPC(2, OPC_MIN_F
, min
.f
),
1350 OPC(2, OPC_MAX_F
, max
.f
),
1351 OPC(2, OPC_MUL_F
, mul
.f
),
1352 OPC(2, OPC_SIGN_F
, sign
.f
),
1353 OPC(2, OPC_CMPS_F
, cmps
.f
),
1354 OPC(2, OPC_ABSNEG_F
, absneg
.f
),
1355 OPC(2, OPC_CMPV_F
, cmpv
.f
),
1356 OPC(2, OPC_FLOOR_F
, floor
.f
),
1357 OPC(2, OPC_CEIL_F
, ceil
.f
),
1358 OPC(2, OPC_RNDNE_F
, rndne
.f
),
1359 OPC(2, OPC_RNDAZ_F
, rndaz
.f
),
1360 OPC(2, OPC_TRUNC_F
, trunc
.f
),
1361 OPC(2, OPC_ADD_U
, add
.u
),
1362 OPC(2, OPC_ADD_S
, add
.s
),
1363 OPC(2, OPC_SUB_U
, sub
.u
),
1364 OPC(2, OPC_SUB_S
, sub
.s
),
1365 OPC(2, OPC_CMPS_U
, cmps
.u
),
1366 OPC(2, OPC_CMPS_S
, cmps
.s
),
1367 OPC(2, OPC_MIN_U
, min
.u
),
1368 OPC(2, OPC_MIN_S
, min
.s
),
1369 OPC(2, OPC_MAX_U
, max
.u
),
1370 OPC(2, OPC_MAX_S
, max
.s
),
1371 OPC(2, OPC_ABSNEG_S
, absneg
.s
),
1372 OPC(2, OPC_AND_B
, and.b
),
1373 OPC(2, OPC_OR_B
, or.b
),
1374 OPC(2, OPC_NOT_B
, not.b
),
1375 OPC(2, OPC_XOR_B
, xor.b
),
1376 OPC(2, OPC_CMPV_U
, cmpv
.u
),
1377 OPC(2, OPC_CMPV_S
, cmpv
.s
),
1378 OPC(2, OPC_MUL_U24
, mul
.u24
),
1379 OPC(2, OPC_MUL_S24
, mul
.s24
),
1380 OPC(2, OPC_MULL_U
, mull
.u
),
1381 OPC(2, OPC_BFREV_B
, bfrev
.b
),
1382 OPC(2, OPC_CLZ_S
, clz
.s
),
1383 OPC(2, OPC_CLZ_B
, clz
.b
),
1384 OPC(2, OPC_SHL_B
, shl
.b
),
1385 OPC(2, OPC_SHR_B
, shr
.b
),
1386 OPC(2, OPC_ASHR_B
, ashr
.b
),
1387 OPC(2, OPC_BARY_F
, bary
.f
),
1388 OPC(2, OPC_MGEN_B
, mgen
.b
),
1389 OPC(2, OPC_GETBIT_B
, getbit
.b
),
1390 OPC(2, OPC_SETRM
, setrm
),
1391 OPC(2, OPC_CBITS_B
, cbits
.b
),
1392 OPC(2, OPC_SHB
, shb
),
1393 OPC(2, OPC_MSAD
, msad
),
1396 OPC(3, OPC_MAD_U16
, mad
.u16
),
1397 OPC(3, OPC_MADSH_U16
, madsh
.u16
),
1398 OPC(3, OPC_MAD_S16
, mad
.s16
),
1399 OPC(3, OPC_MADSH_M16
, madsh
.m16
),
1400 OPC(3, OPC_MAD_U24
, mad
.u24
),
1401 OPC(3, OPC_MAD_S24
, mad
.s24
),
1402 OPC(3, OPC_MAD_F16
, mad
.f16
),
1403 OPC(3, OPC_MAD_F32
, mad
.f32
),
1404 OPC(3, OPC_SEL_B16
, sel
.b16
),
1405 OPC(3, OPC_SEL_B32
, sel
.b32
),
1406 OPC(3, OPC_SEL_S16
, sel
.s16
),
1407 OPC(3, OPC_SEL_S32
, sel
.s32
),
1408 OPC(3, OPC_SEL_F16
, sel
.f16
),
1409 OPC(3, OPC_SEL_F32
, sel
.f32
),
1410 OPC(3, OPC_SAD_S16
, sad
.s16
),
1411 OPC(3, OPC_SAD_S32
, sad
.s32
),
1414 OPC(4, OPC_RCP
, rcp
),
1415 OPC(4, OPC_RSQ
, rsq
),
1416 OPC(4, OPC_LOG2
, log2
),
1417 OPC(4, OPC_EXP2
, exp2
),
1418 OPC(4, OPC_SIN
, sin
),
1419 OPC(4, OPC_COS
, cos
),
1420 OPC(4, OPC_SQRT
, sqrt
),
1421 OPC(4, OPC_HRSQ
, hrsq
),
1422 OPC(4, OPC_HLOG2
, hlog2
),
1423 OPC(4, OPC_HEXP2
, hexp2
),
1426 OPC(5, OPC_ISAM
, isam
),
1427 OPC(5, OPC_ISAML
, isaml
),
1428 OPC(5, OPC_ISAMM
, isamm
),
1429 OPC(5, OPC_SAM
, sam
),
1430 OPC(5, OPC_SAMB
, samb
),
1431 OPC(5, OPC_SAML
, saml
),
1432 OPC(5, OPC_SAMGQ
, samgq
),
1433 OPC(5, OPC_GETLOD
, getlod
),
1434 OPC(5, OPC_CONV
, conv
),
1435 OPC(5, OPC_CONVM
, convm
),
1436 OPC(5, OPC_GETSIZE
, getsize
),
1437 OPC(5, OPC_GETBUF
, getbuf
),
1438 OPC(5, OPC_GETPOS
, getpos
),
1439 OPC(5, OPC_GETINFO
, getinfo
),
1440 OPC(5, OPC_DSX
, dsx
),
1441 OPC(5, OPC_DSY
, dsy
),
1442 OPC(5, OPC_GATHER4R
, gather4r
),
1443 OPC(5, OPC_GATHER4G
, gather4g
),
1444 OPC(5, OPC_GATHER4B
, gather4b
),
1445 OPC(5, OPC_GATHER4A
, gather4a
),
1446 OPC(5, OPC_SAMGP0
, samgp0
),
1447 OPC(5, OPC_SAMGP1
, samgp1
),
1448 OPC(5, OPC_SAMGP2
, samgp2
),
1449 OPC(5, OPC_SAMGP3
, samgp3
),
1450 OPC(5, OPC_DSXPP_1
, dsxpp
.1),
1451 OPC(5, OPC_DSYPP_1
, dsypp
.1),
1452 OPC(5, OPC_RGETPOS
, rgetpos
),
1453 OPC(5, OPC_RGETINFO
, rgetinfo
),
1454 /* macros are needed here for ir3_print */
1455 OPC(5, OPC_DSXPP_MACRO
, dsxpp
.macro
),
1456 OPC(5, OPC_DSYPP_MACRO
, dsypp
.macro
),
1460 OPC(6, OPC_LDG
, ldg
),
1461 OPC(6, OPC_LDL
, ldl
),
1462 OPC(6, OPC_LDP
, ldp
),
1463 OPC(6, OPC_STG
, stg
),
1464 OPC(6, OPC_STL
, stl
),
1465 OPC(6, OPC_STP
, stp
),
1466 OPC(6, OPC_LDIB
, ldib
),
1467 OPC(6, OPC_G2L
, g2l
),
1468 OPC(6, OPC_L2G
, l2g
),
1469 OPC(6, OPC_PREFETCH
, prefetch
),
1470 OPC(6, OPC_LDLW
, ldlw
),
1471 OPC(6, OPC_STLW
, stlw
),
1472 OPC(6, OPC_RESFMT
, resfmt
),
1473 OPC(6, OPC_RESINFO
, resinfo
),
1474 OPC(6, OPC_ATOMIC_ADD
, atomic
.add
),
1475 OPC(6, OPC_ATOMIC_SUB
, atomic
.sub
),
1476 OPC(6, OPC_ATOMIC_XCHG
, atomic
.xchg
),
1477 OPC(6, OPC_ATOMIC_INC
, atomic
.inc
),
1478 OPC(6, OPC_ATOMIC_DEC
, atomic
.dec
),
1479 OPC(6, OPC_ATOMIC_CMPXCHG
, atomic
.cmpxchg
),
1480 OPC(6, OPC_ATOMIC_MIN
, atomic
.min
),
1481 OPC(6, OPC_ATOMIC_MAX
, atomic
.max
),
1482 OPC(6, OPC_ATOMIC_AND
, atomic
.and),
1483 OPC(6, OPC_ATOMIC_OR
, atomic
.or),
1484 OPC(6, OPC_ATOMIC_XOR
, atomic
.xor),
1485 OPC(6, OPC_LDGB
, ldgb
),
1486 OPC(6, OPC_STGB
, stgb
),
1487 OPC(6, OPC_STIB
, stib
),
1488 OPC(6, OPC_LDC
, ldc
),
1489 OPC(6, OPC_LDLV
, ldlv
),
1491 OPC(7, OPC_BAR
, bar
),
1492 OPC(7, OPC_FENCE
, fence
),
1497 #define GETINFO(instr) (&(opcs[((instr)->opc_cat << NOPC_BITS) | instr_opc(instr, ctx->gpu_id)]))
1499 const char *disasm_a3xx_instr_name(opc_t opc
)
1501 if (opc_cat(opc
) == -1) return "??meta??";
1502 return opcs
[opc
].name
;
1505 static void print_single_instr(struct disasm_ctx
*ctx
, instr_t
*instr
)
1507 const char *name
= GETINFO(instr
)->name
;
1508 uint32_t opc
= instr_opc(instr
, ctx
->gpu_id
);
1511 fprintf(ctx
->out
, "%s", name
);
1512 GETINFO(instr
)->print(ctx
, instr
);
1514 fprintf(ctx
->out
, "unknown(%d,%d)", instr
->opc_cat
, opc
);
1516 switch (instr
->opc_cat
) {
1517 case 0: print_instr_cat0(ctx
, instr
); break;
1518 case 1: print_instr_cat1(ctx
, instr
); break;
1519 case 2: print_instr_cat2(ctx
, instr
); break;
1520 case 3: print_instr_cat3(ctx
, instr
); break;
1521 case 4: print_instr_cat4(ctx
, instr
); break;
1522 case 5: print_instr_cat5(ctx
, instr
); break;
1523 case 6: print_instr_cat6(ctx
, instr
); break;
1524 case 7: print_instr_cat7(ctx
, instr
); break;
1529 static bool print_instr(struct disasm_ctx
*ctx
, uint32_t *dwords
, int n
)
1531 instr_t
*instr
= (instr_t
*)dwords
;
1532 uint32_t opc
= instr_opc(instr
, ctx
->gpu_id
);
1534 unsigned cycles
= ctx
->stats
->instructions
;
1536 if (debug
& PRINT_RAW
) {
1537 fprintf(ctx
->out
, "%s:%d:%04d:%04d[%08xx_%08xx] ", levels
[ctx
->level
],
1538 instr
->opc_cat
, n
, cycles
++, dwords
[1], dwords
[0]);
1541 /* NOTE: order flags are printed is a bit fugly.. but for now I
1542 * try to match the order in llvm-a3xx disassembler for easy
1546 ctx
->repeat
= instr_repeat(instr
);
1547 ctx
->stats
->instructions
+= 1 + ctx
->repeat
;
1548 ctx
->stats
->instlen
++;
1551 fprintf(ctx
->out
, "(sy)");
1554 if (instr
->ss
&& ((instr
->opc_cat
<= 4) || (instr
->opc_cat
== 7))) {
1555 fprintf(ctx
->out
, "(ss)");
1559 fprintf(ctx
->out
, "(jp)");
1560 if ((instr
->opc_cat
== 0) && instr
->cat0
.eq
)
1561 fprintf(ctx
->out
, "(eq)");
1562 if (instr_sat(instr
))
1563 fprintf(ctx
->out
, "(sat)");
1565 fprintf(ctx
->out
, "(rpt%d)", ctx
->repeat
);
1566 else if ((instr
->opc_cat
== 2) && (instr
->cat2
.src1_r
|| instr
->cat2
.src2_r
))
1567 nop
= (instr
->cat2
.src2_r
* 2) + instr
->cat2
.src1_r
;
1568 else if ((instr
->opc_cat
== 3) && (instr
->cat3
.src1_r
|| instr
->cat3
.src2_r
))
1569 nop
= (instr
->cat3
.src2_r
* 2) + instr
->cat3
.src1_r
;
1570 ctx
->stats
->instructions
+= nop
;
1571 ctx
->stats
->nops
+= nop
;
1573 ctx
->stats
->nops
+= 1 + ctx
->repeat
;
1575 fprintf(ctx
->out
, "(nop%d) ", nop
);
1577 if (instr
->ul
&& ((2 <= instr
->opc_cat
) && (instr
->opc_cat
<= 4)))
1578 fprintf(ctx
->out
, "(ul)");
1580 print_single_instr(ctx
, instr
);
1581 fprintf(ctx
->out
, "\n");
1583 process_reg_dst(ctx
);
1585 if ((instr
->opc_cat
<= 4) && (debug
& EXPAND_REPEAT
)) {
1587 for (i
= 0; i
< nop
; i
++) {
1588 if (debug
& PRINT_VERBOSE
) {
1589 fprintf(ctx
->out
, "%s:%d:%04d:%04d[ ] ",
1590 levels
[ctx
->level
], instr
->opc_cat
, n
, cycles
++);
1592 fprintf(ctx
->out
, "nop\n");
1594 for (i
= 0; i
< ctx
->repeat
; i
++) {
1595 ctx
->repeatidx
= i
+ 1;
1596 if (debug
& PRINT_VERBOSE
) {
1597 fprintf(ctx
->out
, "%s:%d:%04d:%04d[ ] ",
1598 levels
[ctx
->level
], instr
->opc_cat
, n
, cycles
++);
1600 print_single_instr(ctx
, instr
);
1601 fprintf(ctx
->out
, "\n");
1606 return (instr
->opc_cat
== 0) &&
1607 ((opc
== OPC_END
) || (opc
== OPC_CHSH
));
1610 int disasm_a3xx(uint32_t *dwords
, int sizedwords
, int level
, FILE *out
, unsigned gpu_id
)
1612 struct shader_stats stats
;
1613 return disasm_a3xx_stat(dwords
, sizedwords
, level
, out
, gpu_id
, &stats
);
1616 int disasm_a3xx_stat(uint32_t *dwords
, int sizedwords
, int level
, FILE *out
,
1617 unsigned gpu_id
, struct shader_stats
*stats
)
1619 struct disasm_ctx ctx
;
1622 bool has_end
= false;
1624 ir3_assert((sizedwords
% 2) == 0);
1626 memset(&ctx
, 0, sizeof(ctx
));
1629 ctx
.gpu_id
= gpu_id
;
1631 memset(ctx
.stats
, 0, sizeof(*ctx
.stats
));
1633 for (i
= 0; i
< sizedwords
; i
+= 2) {
1634 has_end
|= print_instr(&ctx
, &dwords
[i
], i
/2);
1637 if (dwords
[i
] == 0 && dwords
[i
+ 1] == 0)
1645 if (debug
& PRINT_STATS
)
1646 print_reg_stats(&ctx
);
1651 void disasm_a3xx_set_debug(enum debug_t d
)