2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include <util/u_debug.h>
33 #include "instr-a3xx.h"
35 /* bitmask of debug flags */
37 PRINT_RAW
= 0x1, /* dump raw hexdump */
42 static enum debug_t debug
;
44 #define printf debug_printf
46 static const char *levels
[] = {
65 static const char *component
= "xyzw";
67 static const char *type
[] = {
83 /* current instruction repeat flag: */
85 /* current instruction repeat indx/offset (for --expand): */
88 unsigned instructions
;
91 static void print_reg(struct disasm_ctx
*ctx
, reg_t reg
, bool full
, bool r
,
92 bool c
, bool im
, bool neg
, bool abs
, bool addr_rel
)
94 const char type
= c
? 'c' : 'r';
96 // XXX I prefer - and || for neg/abs, but preserving format used
97 // by libllvm-a3xx for easy diffing..
100 fprintf(ctx
->out
, "(absneg)");
102 fprintf(ctx
->out
, "(neg)");
104 fprintf(ctx
->out
, "(abs)");
107 fprintf(ctx
->out
, "(r)");
110 fprintf(ctx
->out
, "%d", reg
.iim_val
);
111 } else if (addr_rel
) {
112 /* I would just use %+d but trying to make it diff'able with
116 fprintf(ctx
->out
, "%s%c<a0.x - %d>", full
? "" : "h", type
, -reg
.iim_val
);
117 else if (reg
.iim_val
> 0)
118 fprintf(ctx
->out
, "%s%c<a0.x + %d>", full
? "" : "h", type
, reg
.iim_val
);
120 fprintf(ctx
->out
, "%s%c<a0.x>", full
? "" : "h", type
);
121 } else if ((reg
.num
== REG_A0
) && !c
) {
122 /* This matches libllvm output, the second (scalar) address register
123 * seems to be called a1.x instead of a0.y.
125 fprintf(ctx
->out
, "a%d.x", reg
.comp
);
126 } else if ((reg
.num
== REG_P0
) && !c
) {
127 fprintf(ctx
->out
, "p0.%c", component
[reg
.comp
]);
129 fprintf(ctx
->out
, "%s%c%d.%c", full
? "" : "h", type
, reg
.num
, component
[reg
.comp
]);
133 static unsigned regidx(reg_t reg
)
135 return (4 * reg
.num
) + reg
.comp
;
138 static reg_t
idxreg(unsigned idx
)
146 static void print_reg_dst(struct disasm_ctx
*ctx
, reg_t reg
, bool full
, bool addr_rel
)
148 reg
= idxreg(regidx(reg
) + ctx
->repeatidx
);
149 print_reg(ctx
, reg
, full
, false, false, false, false, false, addr_rel
);
152 /* TODO switch to using reginfo struct everywhere, since more readable
153 * than passing a bunch of bools to print_reg_src
167 static void print_src(struct disasm_ctx
*ctx
, struct reginfo
*info
)
169 reg_t reg
= info
->reg
;
172 reg
= idxreg(regidx(info
->reg
) + ctx
->repeatidx
);
174 print_reg(ctx
, reg
, info
->full
, info
->r
, info
->c
, info
->im
,
175 info
->neg
, info
->abs
, info
->addr_rel
);
178 //static void print_dst(struct disasm_ctx *ctx, struct reginfo *info)
180 // print_reg_dst(ctx, info->reg, info->full, info->addr_rel);
183 static void print_instr_cat0(struct disasm_ctx
*ctx
, instr_t
*instr
)
185 instr_cat0_t
*cat0
= &instr
->cat0
;
190 fprintf(ctx
->out
, " %sp0.%c", cat0
->inv
? "!" : "",
191 component
[cat0
->comp
]);
194 fprintf(ctx
->out
, " %sp0.%c, #%d", cat0
->inv
? "!" : "",
195 component
[cat0
->comp
], cat0
->a3xx
.immed
);
199 fprintf(ctx
->out
, " #%d", cat0
->a3xx
.immed
);
203 if ((debug
& PRINT_VERBOSE
) && (cat0
->dummy2
|cat0
->dummy3
|cat0
->dummy4
))
204 fprintf(ctx
->out
, "\t{0: %x,%x,%x}", cat0
->dummy2
, cat0
->dummy3
, cat0
->dummy4
);
207 static void print_instr_cat1(struct disasm_ctx
*ctx
, instr_t
*instr
)
209 instr_cat1_t
*cat1
= &instr
->cat1
;
212 fprintf(ctx
->out
, "(ul)");
214 if (cat1
->src_type
== cat1
->dst_type
) {
215 if ((cat1
->src_type
== TYPE_S16
) && (((reg_t
)cat1
->dst
).num
== REG_A0
)) {
216 /* special case (nmemonic?): */
217 fprintf(ctx
->out
, "mova");
219 fprintf(ctx
->out
, "mov.%s%s", type
[cat1
->src_type
], type
[cat1
->dst_type
]);
222 fprintf(ctx
->out
, "cov.%s%s", type
[cat1
->src_type
], type
[cat1
->dst_type
]);
225 fprintf(ctx
->out
, " ");
228 fprintf(ctx
->out
, "(even)");
231 fprintf(ctx
->out
, "(pos_infinity)");
233 print_reg_dst(ctx
, (reg_t
)(cat1
->dst
), type_size(cat1
->dst_type
) == 32,
236 fprintf(ctx
->out
, ", ");
238 /* ugg, have to special case this.. vs print_reg().. */
240 if (type_float(cat1
->src_type
))
241 fprintf(ctx
->out
, "(%f)", cat1
->fim_val
);
242 else if (type_uint(cat1
->src_type
))
243 fprintf(ctx
->out
, "0x%08x", cat1
->uim_val
);
245 fprintf(ctx
->out
, "%d", cat1
->iim_val
);
246 } else if (cat1
->src_rel
&& !cat1
->src_c
) {
247 /* I would just use %+d but trying to make it diff'able with
250 char type
= cat1
->src_rel_c
? 'c' : 'r';
251 const char *full
= (type_size(cat1
->src_type
) == 32) ? "" : "h";
253 fprintf(ctx
->out
, "%s%c<a0.x - %d>", full
, type
, -cat1
->off
);
254 else if (cat1
->off
> 0)
255 fprintf(ctx
->out
, "%s%c<a0.x + %d>", full
, type
, cat1
->off
);
257 fprintf(ctx
->out
, "%s%c<a0.x>", full
, type
);
259 struct reginfo src
= {
260 .reg
= (reg_t
)cat1
->src
,
261 .full
= type_size(cat1
->src_type
) == 32,
266 print_src(ctx
, &src
);
269 if ((debug
& PRINT_VERBOSE
) && (cat1
->must_be_0
))
270 fprintf(ctx
->out
, "\t{1: %x}", cat1
->must_be_0
);
273 static void print_instr_cat2(struct disasm_ctx
*ctx
, instr_t
*instr
)
275 instr_cat2_t
*cat2
= &instr
->cat2
;
276 static const char *cond
[] = {
286 switch (_OPC(2, cat2
->opc
)) {
293 fprintf(ctx
->out
, ".%s", cond
[cat2
->cond
]);
297 fprintf(ctx
->out
, " ");
299 fprintf(ctx
->out
, "(ei)");
300 print_reg_dst(ctx
, (reg_t
)(cat2
->dst
), cat2
->full
^ cat2
->dst_half
, false);
301 fprintf(ctx
->out
, ", ");
303 struct reginfo src1
= {
305 .r
= cat2
->repeat
? cat2
->src1_r
: 0,
307 .abs
= cat2
->src1_abs
,
308 .neg
= cat2
->src1_neg
,
311 if (cat2
->c1
.src1_c
) {
312 src1
.reg
= (reg_t
)(cat2
->c1
.src1
);
314 } else if (cat2
->rel1
.src1_rel
) {
315 src1
.reg
= (reg_t
)(cat2
->rel1
.src1
);
316 src1
.c
= cat2
->rel1
.src1_c
;
317 src1
.addr_rel
= true;
319 src1
.reg
= (reg_t
)(cat2
->src1
);
321 print_src(ctx
, &src1
);
323 struct reginfo src2
= {
324 .r
= cat2
->repeat
? cat2
->src2_r
: 0,
326 .abs
= cat2
->src2_abs
,
327 .neg
= cat2
->src2_neg
,
330 switch (_OPC(2, cat2
->opc
)) {
345 /* these only have one src reg */
348 fprintf(ctx
->out
, ", ");
349 if (cat2
->c2
.src2_c
) {
350 src2
.reg
= (reg_t
)(cat2
->c2
.src2
);
352 } else if (cat2
->rel2
.src2_rel
) {
353 src2
.reg
= (reg_t
)(cat2
->rel2
.src2
);
354 src2
.c
= cat2
->rel2
.src2_c
;
355 src2
.addr_rel
= true;
357 src2
.reg
= (reg_t
)(cat2
->src2
);
359 print_src(ctx
, &src2
);
364 static void print_instr_cat3(struct disasm_ctx
*ctx
, instr_t
*instr
)
366 instr_cat3_t
*cat3
= &instr
->cat3
;
367 bool full
= instr_cat3_full(cat3
);
369 fprintf(ctx
->out
, " ");
370 print_reg_dst(ctx
, (reg_t
)(cat3
->dst
), full
^ cat3
->dst_half
, false);
371 fprintf(ctx
->out
, ", ");
373 struct reginfo src1
= {
374 .r
= cat3
->repeat
? cat3
->src1_r
: 0,
376 .neg
= cat3
->src1_neg
,
378 if (cat3
->c1
.src1_c
) {
379 src1
.reg
= (reg_t
)(cat3
->c1
.src1
);
381 } else if (cat3
->rel1
.src1_rel
) {
382 src1
.reg
= (reg_t
)(cat3
->rel1
.src1
);
383 src1
.c
= cat3
->rel1
.src1_c
;
384 src1
.addr_rel
= true;
386 src1
.reg
= (reg_t
)(cat3
->src1
);
388 print_src(ctx
, &src1
);
390 fprintf(ctx
->out
, ", ");
391 struct reginfo src2
= {
392 .reg
= (reg_t
)cat3
->src2
,
394 .r
= cat3
->repeat
? cat3
->src2_r
: 0,
396 .neg
= cat3
->src2_neg
,
398 print_src(ctx
, &src2
);
400 fprintf(ctx
->out
, ", ");
401 struct reginfo src3
= {
404 .neg
= cat3
->src3_neg
,
406 if (cat3
->c2
.src3_c
) {
407 src3
.reg
= (reg_t
)(cat3
->c2
.src3
);
409 } else if (cat3
->rel2
.src3_rel
) {
410 src3
.reg
= (reg_t
)(cat3
->rel2
.src3
);
411 src3
.c
= cat3
->rel2
.src3_c
;
412 src3
.addr_rel
= true;
414 src3
.reg
= (reg_t
)(cat3
->src3
);
416 print_src(ctx
, &src3
);
419 static void print_instr_cat4(struct disasm_ctx
*ctx
, instr_t
*instr
)
421 instr_cat4_t
*cat4
= &instr
->cat4
;
423 fprintf(ctx
->out
, " ");
424 print_reg_dst(ctx
, (reg_t
)(cat4
->dst
), cat4
->full
^ cat4
->dst_half
, false);
425 fprintf(ctx
->out
, ", ");
427 struct reginfo src
= {
431 .neg
= cat4
->src_neg
,
432 .abs
= cat4
->src_abs
,
435 src
.reg
= (reg_t
)(cat4
->c
.src
);
437 } else if (cat4
->rel
.src_rel
) {
438 src
.reg
= (reg_t
)(cat4
->rel
.src
);
439 src
.c
= cat4
->rel
.src_c
;
442 src
.reg
= (reg_t
)(cat4
->src
);
444 print_src(ctx
, &src
);
446 if ((debug
& PRINT_VERBOSE
) && (cat4
->dummy1
|cat4
->dummy2
))
447 fprintf(ctx
->out
, "\t{4: %x,%x}", cat4
->dummy1
, cat4
->dummy2
);
450 static void print_instr_cat5(struct disasm_ctx
*ctx
, instr_t
*instr
)
452 static const struct {
453 bool src1
, src2
, samp
, tex
;
455 [opc_op(OPC_ISAM
)] = { true, false, true, true, },
456 [opc_op(OPC_ISAML
)] = { true, true, true, true, },
457 [opc_op(OPC_ISAMM
)] = { true, false, true, true, },
458 [opc_op(OPC_SAM
)] = { true, false, true, true, },
459 [opc_op(OPC_SAMB
)] = { true, true, true, true, },
460 [opc_op(OPC_SAML
)] = { true, true, true, true, },
461 [opc_op(OPC_SAMGQ
)] = { true, false, true, true, },
462 [opc_op(OPC_GETLOD
)] = { true, false, true, true, },
463 [opc_op(OPC_CONV
)] = { true, true, true, true, },
464 [opc_op(OPC_CONVM
)] = { true, true, true, true, },
465 [opc_op(OPC_GETSIZE
)] = { true, false, false, true, },
466 [opc_op(OPC_GETBUF
)] = { false, false, false, true, },
467 [opc_op(OPC_GETPOS
)] = { true, false, false, true, },
468 [opc_op(OPC_GETINFO
)] = { false, false, false, true, },
469 [opc_op(OPC_DSX
)] = { true, false, false, false, },
470 [opc_op(OPC_DSY
)] = { true, false, false, false, },
471 [opc_op(OPC_GATHER4R
)] = { true, false, true, true, },
472 [opc_op(OPC_GATHER4G
)] = { true, false, true, true, },
473 [opc_op(OPC_GATHER4B
)] = { true, false, true, true, },
474 [opc_op(OPC_GATHER4A
)] = { true, false, true, true, },
475 [opc_op(OPC_SAMGP0
)] = { true, false, true, true, },
476 [opc_op(OPC_SAMGP1
)] = { true, false, true, true, },
477 [opc_op(OPC_SAMGP2
)] = { true, false, true, true, },
478 [opc_op(OPC_SAMGP3
)] = { true, false, true, true, },
479 [opc_op(OPC_DSXPP_1
)] = { true, false, false, false, },
480 [opc_op(OPC_DSYPP_1
)] = { true, false, false, false, },
481 [opc_op(OPC_RGETPOS
)] = { true, false, false, false, },
482 [opc_op(OPC_RGETINFO
)] = { false, false, false, false, },
485 static const struct {
490 } desc_features
[8] = {
491 [CAT5_NONUNIFORM
] = { .indirect
= true, },
492 [CAT5_UNIFORM
] = { .indirect
= true, .uniform
= true, },
493 [CAT5_BINDLESS_IMM
] = { .bindless
= true, },
494 [CAT5_BINDLESS_UNIFORM
] = {
499 [CAT5_BINDLESS_NONUNIFORM
] = {
503 [CAT5_BINDLESS_A1_IMM
] = {
507 [CAT5_BINDLESS_A1_UNIFORM
] = {
513 [CAT5_BINDLESS_A1_NONUNIFORM
] = {
520 instr_cat5_t
*cat5
= &instr
->cat5
;
524 cat5
->is_s2en_bindless
&&
525 desc_features
[cat5
->s2en_bindless
.desc_mode
].indirect
;
527 cat5
->is_s2en_bindless
&&
528 desc_features
[cat5
->s2en_bindless
.desc_mode
].bindless
;
530 cat5
->is_s2en_bindless
&&
531 desc_features
[cat5
->s2en_bindless
.desc_mode
].use_a1
;
533 cat5
->is_s2en_bindless
&&
534 desc_features
[cat5
->s2en_bindless
.desc_mode
].uniform
;
536 if (cat5
->is_3d
) fprintf(ctx
->out
, ".3d");
537 if (cat5
->is_a
) fprintf(ctx
->out
, ".a");
538 if (cat5
->is_o
) fprintf(ctx
->out
, ".o");
539 if (cat5
->is_p
) fprintf(ctx
->out
, ".p");
540 if (cat5
->is_s
) fprintf(ctx
->out
, ".s");
541 if (desc_indirect
) fprintf(ctx
->out
, ".s2en");
542 if (uniform
) fprintf(ctx
->out
, ".uniform");
545 unsigned base
= (cat5
->s2en_bindless
.base_hi
<< 1) | cat5
->base_lo
;
546 fprintf(ctx
->out
, ".base%d", base
);
549 fprintf(ctx
->out
, " ");
551 switch (_OPC(5, cat5
->opc
)) {
556 fprintf(ctx
->out
, "(%s)", type
[cat5
->type
]);
560 fprintf(ctx
->out
, "(");
561 for (i
= 0; i
< 4; i
++)
562 if (cat5
->wrmask
& (1 << i
))
563 fprintf(ctx
->out
, "%c", "xyzw"[i
]);
564 fprintf(ctx
->out
, ")");
566 print_reg_dst(ctx
, (reg_t
)(cat5
->dst
), type_size(cat5
->type
) == 32, false);
568 if (info
[cat5
->opc
].src1
) {
569 fprintf(ctx
->out
, ", ");
570 struct reginfo src
= { .reg
= (reg_t
)(cat5
->src1
), .full
= cat5
->full
};
571 print_src(ctx
, &src
);
574 if (cat5
->is_o
|| info
[cat5
->opc
].src2
) {
575 fprintf(ctx
->out
, ", ");
576 struct reginfo src
= { .reg
= (reg_t
)(cat5
->src2
), .full
= cat5
->full
};
577 print_src(ctx
, &src
);
579 if (cat5
->is_s2en_bindless
) {
580 if (!desc_indirect
) {
581 if (info
[cat5
->opc
].samp
) {
583 fprintf(ctx
->out
, ", s#%d", cat5
->s2en_bindless
.src3
);
585 fprintf(ctx
->out
, ", s#%d", cat5
->s2en_bindless
.src3
& 0xf);
588 if (info
[cat5
->opc
].tex
&& !use_a1
) {
589 fprintf(ctx
->out
, ", t#%d", cat5
->s2en_bindless
.src3
>> 4);
593 if (info
[cat5
->opc
].samp
)
594 fprintf(ctx
->out
, ", s#%d", cat5
->norm
.samp
);
595 if (info
[cat5
->opc
].tex
)
596 fprintf(ctx
->out
, ", t#%d", cat5
->norm
.tex
);
600 fprintf(ctx
->out
, ", ");
601 struct reginfo src
= { .reg
= (reg_t
)(cat5
->s2en_bindless
.src3
), .full
= bindless
};
602 print_src(ctx
, &src
);
606 fprintf(ctx
->out
, ", a1.x");
608 if (debug
& PRINT_VERBOSE
) {
609 if (cat5
->is_s2en_bindless
) {
610 if ((debug
& PRINT_VERBOSE
) && cat5
->s2en_bindless
.dummy1
)
611 fprintf(ctx
->out
, "\t{5: %x}", cat5
->s2en_bindless
.dummy1
);
613 if ((debug
& PRINT_VERBOSE
) && cat5
->norm
.dummy1
)
614 fprintf(ctx
->out
, "\t{5: %x}", cat5
->norm
.dummy1
);
619 static void print_instr_cat6_a3xx(struct disasm_ctx
*ctx
, instr_t
*instr
)
621 instr_cat6_t
*cat6
= &instr
->cat6
;
622 char sd
= 0, ss
= 0; /* dst/src address space */
624 struct reginfo dst
, src1
, src2
;
625 int src1off
= 0, dstoff
= 0;
627 memset(&dst
, 0, sizeof(dst
));
628 memset(&src1
, 0, sizeof(src1
));
629 memset(&src2
, 0, sizeof(src2
));
631 switch (_OPC(6, cat6
->opc
)) {
634 dst
.full
= type_size(cat6
->type
) == 32;
635 src1
.full
= type_size(cat6
->type
) == 32;
636 src2
.full
= type_size(cat6
->type
) == 32;
649 dst
.full
= type_size(cat6
->type
) == 32;
650 src1
.full
= type_size(cat6
->type
) == 32;
651 src2
.full
= type_size(cat6
->type
) == 32;
654 dst
.full
= type_size(cat6
->type
) == 32;
660 switch (_OPC(6, cat6
->opc
)) {
664 fprintf(ctx
->out
, ".%dd", cat6
->ldgb
.d
+ 1);
667 fprintf(ctx
->out
, ".%s", cat6
->ldgb
.typed
? "typed" : "untyped");
668 fprintf(ctx
->out
, ".%dd", cat6
->ldgb
.d
+ 1);
669 fprintf(ctx
->out
, ".%s", type
[cat6
->type
]);
670 fprintf(ctx
->out
, ".%d", cat6
->ldgb
.type_size
+ 1);
674 fprintf(ctx
->out
, ".%s", cat6
->stgb
.typed
? "typed" : "untyped");
675 fprintf(ctx
->out
, ".%dd", cat6
->stgb
.d
+ 1);
676 fprintf(ctx
->out
, ".%s", type
[cat6
->type
]);
677 fprintf(ctx
->out
, ".%d", cat6
->stgb
.type_size
+ 1);
681 case OPC_ATOMIC_XCHG
:
684 case OPC_ATOMIC_CMPXCHG
:
690 ss
= cat6
->g
? 'g' : 'l';
691 fprintf(ctx
->out
, ".%s", cat6
->ldgb
.typed
? "typed" : "untyped");
692 fprintf(ctx
->out
, ".%dd", cat6
->ldgb
.d
+ 1);
693 fprintf(ctx
->out
, ".%s", type
[cat6
->type
]);
694 fprintf(ctx
->out
, ".%d", cat6
->ldgb
.type_size
+ 1);
695 fprintf(ctx
->out
, ".%c", ss
);
698 dst
.im
= cat6
->g
&& !cat6
->dst_off
;
699 fprintf(ctx
->out
, ".%s", type
[cat6
->type
]);
702 fprintf(ctx
->out
, " ");
704 switch (_OPC(6, cat6
->opc
)) {
745 if ((_OPC(6, cat6
->opc
) == OPC_STGB
) || (_OPC(6, cat6
->opc
) == OPC_STIB
)) {
748 memset(&src3
, 0, sizeof(src3
));
750 src1
.reg
= (reg_t
)(cat6
->stgb
.src1
);
751 src2
.reg
= (reg_t
)(cat6
->stgb
.src2
);
752 src2
.im
= cat6
->stgb
.src2_im
;
753 src3
.reg
= (reg_t
)(cat6
->stgb
.src3
);
754 src3
.im
= cat6
->stgb
.src3_im
;
757 fprintf(ctx
->out
, "g[%u], ", cat6
->stgb
.dst_ssbo
);
758 print_src(ctx
, &src1
);
759 fprintf(ctx
->out
, ", ");
760 print_src(ctx
, &src2
);
761 fprintf(ctx
->out
, ", ");
762 print_src(ctx
, &src3
);
764 if (debug
& PRINT_VERBOSE
)
765 fprintf(ctx
->out
, " (pad0=%x, pad3=%x)", cat6
->stgb
.pad0
, cat6
->stgb
.pad3
);
770 if (is_atomic(_OPC(6, cat6
->opc
))) {
772 src1
.reg
= (reg_t
)(cat6
->ldgb
.src1
);
773 src1
.im
= cat6
->ldgb
.src1_im
;
774 src2
.reg
= (reg_t
)(cat6
->ldgb
.src2
);
775 src2
.im
= cat6
->ldgb
.src2_im
;
776 dst
.reg
= (reg_t
)(cat6
->ldgb
.dst
);
778 print_src(ctx
, &dst
);
779 fprintf(ctx
->out
, ", ");
782 memset(&src3
, 0, sizeof(src3
));
784 src3
.reg
= (reg_t
)(cat6
->ldgb
.src3
);
787 /* For images, the ".typed" variant is used and src2 is
788 * the ivecN coordinates, ie ivec2 for 2d.
790 * For SSBOs, the ".untyped" variant is used and src2 is
791 * a simple dword offset.. src3 appears to be
792 * uvec2(offset * 4, 0). Not sure the point of that.
795 fprintf(ctx
->out
, "g[%u], ", cat6
->ldgb
.src_ssbo
);
796 print_src(ctx
, &src1
); /* value */
797 fprintf(ctx
->out
, ", ");
798 print_src(ctx
, &src2
); /* offset/coords */
799 fprintf(ctx
->out
, ", ");
800 print_src(ctx
, &src3
); /* 64b byte offset.. */
802 if (debug
& PRINT_VERBOSE
) {
803 fprintf(ctx
->out
, " (pad0=%x, pad3=%x, mustbe0=%x)", cat6
->ldgb
.pad0
,
804 cat6
->ldgb
.pad3
, cat6
->ldgb
.mustbe0
);
806 } else { /* ss == 'l' */
807 fprintf(ctx
->out
, "l[");
808 print_src(ctx
, &src1
); /* simple byte offset */
809 fprintf(ctx
->out
, "], ");
810 print_src(ctx
, &src2
); /* value */
812 if (debug
& PRINT_VERBOSE
) {
813 fprintf(ctx
->out
, " (src3=%x, pad0=%x, pad3=%x, mustbe0=%x)",
814 cat6
->ldgb
.src3
, cat6
->ldgb
.pad0
,
815 cat6
->ldgb
.pad3
, cat6
->ldgb
.mustbe0
);
820 } else if (_OPC(6, cat6
->opc
) == OPC_RESINFO
) {
821 dst
.reg
= (reg_t
)(cat6
->ldgb
.dst
);
823 print_src(ctx
, &dst
);
824 fprintf(ctx
->out
, ", ");
825 fprintf(ctx
->out
, "g[%u]", cat6
->ldgb
.src_ssbo
);
828 } else if (_OPC(6, cat6
->opc
) == OPC_LDGB
) {
830 src1
.reg
= (reg_t
)(cat6
->ldgb
.src1
);
831 src1
.im
= cat6
->ldgb
.src1_im
;
832 src2
.reg
= (reg_t
)(cat6
->ldgb
.src2
);
833 src2
.im
= cat6
->ldgb
.src2_im
;
834 dst
.reg
= (reg_t
)(cat6
->ldgb
.dst
);
836 print_src(ctx
, &dst
);
837 fprintf(ctx
->out
, ", ");
838 fprintf(ctx
->out
, "g[%u], ", cat6
->ldgb
.src_ssbo
);
839 print_src(ctx
, &src1
);
840 fprintf(ctx
->out
, ", ");
841 print_src(ctx
, &src2
);
843 if (debug
& PRINT_VERBOSE
)
844 fprintf(ctx
->out
, " (pad0=%x, pad3=%x, mustbe0=%x)", cat6
->ldgb
.pad0
, cat6
->ldgb
.pad3
, cat6
->ldgb
.mustbe0
);
847 } else if (_OPC(6, cat6
->opc
) == OPC_LDG
&& cat6
->a
.src1_im
&& cat6
->a
.src2_im
) {
850 memset(&src3
, 0, sizeof(src3
));
851 src1
.reg
= (reg_t
)(cat6
->a
.src1
);
852 src2
.reg
= (reg_t
)(cat6
->a
.src2
);
853 src2
.im
= cat6
->a
.src2_im
;
854 src3
.reg
= (reg_t
)(cat6
->a
.off
);
856 dst
.reg
= (reg_t
)(cat6
->d
.dst
);
858 print_src(ctx
, &dst
);
859 fprintf(ctx
->out
, ", g[");
860 print_src(ctx
, &src1
);
861 fprintf(ctx
->out
, "+");
862 print_src(ctx
, &src3
);
863 fprintf(ctx
->out
, "], ");
864 print_src(ctx
, &src2
);
869 dst
.reg
= (reg_t
)(cat6
->c
.dst
);
870 dstoff
= cat6
->c
.off
;
872 dst
.reg
= (reg_t
)(cat6
->d
.dst
);
876 src1
.reg
= (reg_t
)(cat6
->a
.src1
);
877 src1
.im
= cat6
->a
.src1_im
;
878 src2
.reg
= (reg_t
)(cat6
->a
.src2
);
879 src2
.im
= cat6
->a
.src2_im
;
880 src1off
= cat6
->a
.off
;
882 src1
.reg
= (reg_t
)(cat6
->b
.src1
);
883 src1
.im
= cat6
->b
.src1_im
;
884 src2
.reg
= (reg_t
)(cat6
->b
.src2
);
885 src2
.im
= cat6
->b
.src2_im
;
890 fprintf(ctx
->out
, "%c[", sd
);
891 /* note: dst might actually be a src (ie. address to store to) */
892 print_src(ctx
, &dst
);
893 if (cat6
->dst_off
&& cat6
->g
) {
894 struct reginfo dstoff_reg
= {0};
895 dstoff_reg
.reg
= (reg_t
) cat6
->c
.off
;
896 dstoff_reg
.full
= true;
897 fprintf(ctx
->out
, "+");
898 print_src(ctx
, &dstoff_reg
);
900 fprintf(ctx
->out
, "%+d", dstoff
);
902 fprintf(ctx
->out
, "]");
903 fprintf(ctx
->out
, ", ");
907 fprintf(ctx
->out
, "%c[", ss
);
909 /* can have a larger than normal immed, so hack: */
911 fprintf(ctx
->out
, "%u", src1
.reg
.dummy13
);
913 print_src(ctx
, &src1
);
916 if (cat6
->src_off
&& cat6
->g
)
917 print_src(ctx
, &src2
);
919 fprintf(ctx
->out
, "%+d", src1off
);
921 fprintf(ctx
->out
, "]");
923 switch (_OPC(6, cat6
->opc
)) {
928 fprintf(ctx
->out
, ", ");
929 print_src(ctx
, &src2
);
934 static void print_instr_cat6_a6xx(struct disasm_ctx
*ctx
, instr_t
*instr
)
936 instr_cat6_a6xx_t
*cat6
= &instr
->cat6_a6xx
;
937 struct reginfo src1
, src2
, ssbo
;
938 bool uses_type
= _OPC(6, cat6
->opc
) != OPC_LDC
;
940 static const struct {
944 } desc_features
[8] = {
945 [CAT6_IMM
] = { false },
946 [CAT6_BINDLESS_IMM
] = { .bindless
= true, },
947 [CAT6_BINDLESS_UNIFORM
] = {
952 [CAT6_BINDLESS_NONUNIFORM
] = {
958 bool indirect_ssbo
= desc_features
[cat6
->desc_mode
].indirect
;
959 bool bindless
= desc_features
[cat6
->desc_mode
].bindless
;
960 bool uniform
= desc_features
[cat6
->desc_mode
].uniform
;
961 bool type_full
= cat6
->type
!= TYPE_U16
;
964 memset(&src1
, 0, sizeof(src1
));
965 memset(&src2
, 0, sizeof(src2
));
966 memset(&ssbo
, 0, sizeof(ssbo
));
969 fprintf(ctx
->out
, ".%s", cat6
->typed
? "typed" : "untyped");
970 fprintf(ctx
->out
, ".%dd", cat6
->d
+ 1);
971 fprintf(ctx
->out
, ".%s", type
[cat6
->type
]);
973 fprintf(ctx
->out
, ".offset%d", cat6
->d
);
975 fprintf(ctx
->out
, ".%u", cat6
->type_size
+ 1);
978 fprintf(ctx
->out
, ".base%d", cat6
->base
);
980 fprintf(ctx
->out
, ".uniform");
981 fprintf(ctx
->out
, " ");
983 src2
.reg
= (reg_t
)(cat6
->src2
);
984 src2
.full
= type_full
;
985 print_src(ctx
, &src2
);
986 fprintf(ctx
->out
, ", ");
988 src1
.reg
= (reg_t
)(cat6
->src1
);
989 src1
.full
= true; // XXX
990 print_src(ctx
, &src1
);
991 fprintf(ctx
->out
, ", ");
992 ssbo
.reg
= (reg_t
)(cat6
->ssbo
);
993 ssbo
.im
= !indirect_ssbo
;
995 print_src(ctx
, &ssbo
);
997 if (debug
& PRINT_VERBOSE
) {
998 fprintf(ctx
->out
, " (pad1=%x, pad2=%x, pad3=%x, pad4=%x, pad5=%x)",
999 cat6
->pad1
, cat6
->pad2
, cat6
->pad3
, cat6
->pad4
, cat6
->pad5
);
1003 static void print_instr_cat6(struct disasm_ctx
*ctx
, instr_t
*instr
)
1005 if (!is_cat6_legacy(instr
, ctx
->gpu_id
)) {
1006 print_instr_cat6_a6xx(ctx
, instr
);
1007 if (debug
& PRINT_VERBOSE
)
1008 fprintf(ctx
->out
, " NEW");
1010 print_instr_cat6_a3xx(ctx
, instr
);
1011 if (debug
& PRINT_VERBOSE
)
1012 fprintf(ctx
->out
, " LEGACY");
1015 static void print_instr_cat7(struct disasm_ctx
*ctx
, instr_t
*instr
)
1017 instr_cat7_t
*cat7
= &instr
->cat7
;
1020 fprintf(ctx
->out
, ".g");
1022 fprintf(ctx
->out
, ".l");
1024 if (_OPC(7, cat7
->opc
) == OPC_FENCE
) {
1026 fprintf(ctx
->out
, ".r");
1028 fprintf(ctx
->out
, ".w");
1032 /* size of largest OPC field of all the instruction categories: */
1035 static const struct opc_info
{
1039 void (*print
)(struct disasm_ctx
*ctx
, instr_t
*instr
);
1040 } opcs
[1 << (3+NOPC_BITS
)] = {
1041 #define OPC(cat, opc, name) [(opc)] = { (cat), (opc), #name, print_instr_cat##cat }
1043 OPC(0, OPC_NOP
, nop
),
1045 OPC(0, OPC_JUMP
, jump
),
1046 OPC(0, OPC_CALL
, call
),
1047 OPC(0, OPC_RET
, ret
),
1048 OPC(0, OPC_KILL
, kill
),
1049 OPC(0, OPC_END
, end
),
1050 OPC(0, OPC_EMIT
, emit
),
1051 OPC(0, OPC_CUT
, cut
),
1052 OPC(0, OPC_CHMASK
, chmask
),
1053 OPC(0, OPC_CHSH
, chsh
),
1054 OPC(0, OPC_FLOW_REV
, flow_rev
),
1056 OPC(0, OPC_ELSE
, else),
1057 OPC(0, OPC_ENDIF
, endif
),
1063 OPC(2, OPC_ADD_F
, add
.f
),
1064 OPC(2, OPC_MIN_F
, min
.f
),
1065 OPC(2, OPC_MAX_F
, max
.f
),
1066 OPC(2, OPC_MUL_F
, mul
.f
),
1067 OPC(2, OPC_SIGN_F
, sign
.f
),
1068 OPC(2, OPC_CMPS_F
, cmps
.f
),
1069 OPC(2, OPC_ABSNEG_F
, absneg
.f
),
1070 OPC(2, OPC_CMPV_F
, cmpv
.f
),
1071 OPC(2, OPC_FLOOR_F
, floor
.f
),
1072 OPC(2, OPC_CEIL_F
, ceil
.f
),
1073 OPC(2, OPC_RNDNE_F
, rndne
.f
),
1074 OPC(2, OPC_RNDAZ_F
, rndaz
.f
),
1075 OPC(2, OPC_TRUNC_F
, trunc
.f
),
1076 OPC(2, OPC_ADD_U
, add
.u
),
1077 OPC(2, OPC_ADD_S
, add
.s
),
1078 OPC(2, OPC_SUB_U
, sub
.u
),
1079 OPC(2, OPC_SUB_S
, sub
.s
),
1080 OPC(2, OPC_CMPS_U
, cmps
.u
),
1081 OPC(2, OPC_CMPS_S
, cmps
.s
),
1082 OPC(2, OPC_MIN_U
, min
.u
),
1083 OPC(2, OPC_MIN_S
, min
.s
),
1084 OPC(2, OPC_MAX_U
, max
.u
),
1085 OPC(2, OPC_MAX_S
, max
.s
),
1086 OPC(2, OPC_ABSNEG_S
, absneg
.s
),
1087 OPC(2, OPC_AND_B
, and.b
),
1088 OPC(2, OPC_OR_B
, or.b
),
1089 OPC(2, OPC_NOT_B
, not.b
),
1090 OPC(2, OPC_XOR_B
, xor.b
),
1091 OPC(2, OPC_CMPV_U
, cmpv
.u
),
1092 OPC(2, OPC_CMPV_S
, cmpv
.s
),
1093 OPC(2, OPC_MUL_U24
, mul
.u24
),
1094 OPC(2, OPC_MUL_S24
, mul
.s24
),
1095 OPC(2, OPC_MULL_U
, mull
.u
),
1096 OPC(2, OPC_BFREV_B
, bfrev
.b
),
1097 OPC(2, OPC_CLZ_S
, clz
.s
),
1098 OPC(2, OPC_CLZ_B
, clz
.b
),
1099 OPC(2, OPC_SHL_B
, shl
.b
),
1100 OPC(2, OPC_SHR_B
, shr
.b
),
1101 OPC(2, OPC_ASHR_B
, ashr
.b
),
1102 OPC(2, OPC_BARY_F
, bary
.f
),
1103 OPC(2, OPC_MGEN_B
, mgen
.b
),
1104 OPC(2, OPC_GETBIT_B
, getbit
.b
),
1105 OPC(2, OPC_SETRM
, setrm
),
1106 OPC(2, OPC_CBITS_B
, cbits
.b
),
1107 OPC(2, OPC_SHB
, shb
),
1108 OPC(2, OPC_MSAD
, msad
),
1111 OPC(3, OPC_MAD_U16
, mad
.u16
),
1112 OPC(3, OPC_MADSH_U16
, madsh
.u16
),
1113 OPC(3, OPC_MAD_S16
, mad
.s16
),
1114 OPC(3, OPC_MADSH_M16
, madsh
.m16
),
1115 OPC(3, OPC_MAD_U24
, mad
.u24
),
1116 OPC(3, OPC_MAD_S24
, mad
.s24
),
1117 OPC(3, OPC_MAD_F16
, mad
.f16
),
1118 OPC(3, OPC_MAD_F32
, mad
.f32
),
1119 OPC(3, OPC_SEL_B16
, sel
.b16
),
1120 OPC(3, OPC_SEL_B32
, sel
.b32
),
1121 OPC(3, OPC_SEL_S16
, sel
.s16
),
1122 OPC(3, OPC_SEL_S32
, sel
.s32
),
1123 OPC(3, OPC_SEL_F16
, sel
.f16
),
1124 OPC(3, OPC_SEL_F32
, sel
.f32
),
1125 OPC(3, OPC_SAD_S16
, sad
.s16
),
1126 OPC(3, OPC_SAD_S32
, sad
.s32
),
1129 OPC(4, OPC_RCP
, rcp
),
1130 OPC(4, OPC_RSQ
, rsq
),
1131 OPC(4, OPC_LOG2
, log2
),
1132 OPC(4, OPC_EXP2
, exp2
),
1133 OPC(4, OPC_SIN
, sin
),
1134 OPC(4, OPC_COS
, cos
),
1135 OPC(4, OPC_SQRT
, sqrt
),
1136 OPC(4, OPC_HRSQ
, hrsq
),
1137 OPC(4, OPC_HLOG2
, hlog2
),
1138 OPC(4, OPC_HEXP2
, hexp2
),
1141 OPC(5, OPC_ISAM
, isam
),
1142 OPC(5, OPC_ISAML
, isaml
),
1143 OPC(5, OPC_ISAMM
, isamm
),
1144 OPC(5, OPC_SAM
, sam
),
1145 OPC(5, OPC_SAMB
, samb
),
1146 OPC(5, OPC_SAML
, saml
),
1147 OPC(5, OPC_SAMGQ
, samgq
),
1148 OPC(5, OPC_GETLOD
, getlod
),
1149 OPC(5, OPC_CONV
, conv
),
1150 OPC(5, OPC_CONVM
, convm
),
1151 OPC(5, OPC_GETSIZE
, getsize
),
1152 OPC(5, OPC_GETBUF
, getbuf
),
1153 OPC(5, OPC_GETPOS
, getpos
),
1154 OPC(5, OPC_GETINFO
, getinfo
),
1155 OPC(5, OPC_DSX
, dsx
),
1156 OPC(5, OPC_DSY
, dsy
),
1157 OPC(5, OPC_GATHER4R
, gather4r
),
1158 OPC(5, OPC_GATHER4G
, gather4g
),
1159 OPC(5, OPC_GATHER4B
, gather4b
),
1160 OPC(5, OPC_GATHER4A
, gather4a
),
1161 OPC(5, OPC_SAMGP0
, samgp0
),
1162 OPC(5, OPC_SAMGP1
, samgp1
),
1163 OPC(5, OPC_SAMGP2
, samgp2
),
1164 OPC(5, OPC_SAMGP3
, samgp3
),
1165 OPC(5, OPC_DSXPP_1
, dsxpp
.1),
1166 OPC(5, OPC_DSYPP_1
, dsypp
.1),
1167 OPC(5, OPC_RGETPOS
, rgetpos
),
1168 OPC(5, OPC_RGETINFO
, rgetinfo
),
1172 OPC(6, OPC_LDG
, ldg
),
1173 OPC(6, OPC_LDL
, ldl
),
1174 OPC(6, OPC_LDP
, ldp
),
1175 OPC(6, OPC_STG
, stg
),
1176 OPC(6, OPC_STL
, stl
),
1177 OPC(6, OPC_STP
, stp
),
1178 OPC(6, OPC_LDIB
, ldib
),
1179 OPC(6, OPC_G2L
, g2l
),
1180 OPC(6, OPC_L2G
, l2g
),
1181 OPC(6, OPC_PREFETCH
, prefetch
),
1182 OPC(6, OPC_LDLW
, ldlw
),
1183 OPC(6, OPC_STLW
, stlw
),
1184 OPC(6, OPC_RESFMT
, resfmt
),
1185 OPC(6, OPC_RESINFO
, resinfo
),
1186 OPC(6, OPC_ATOMIC_ADD
, atomic
.add
),
1187 OPC(6, OPC_ATOMIC_SUB
, atomic
.sub
),
1188 OPC(6, OPC_ATOMIC_XCHG
, atomic
.xchg
),
1189 OPC(6, OPC_ATOMIC_INC
, atomic
.inc
),
1190 OPC(6, OPC_ATOMIC_DEC
, atomic
.dec
),
1191 OPC(6, OPC_ATOMIC_CMPXCHG
, atomic
.cmpxchg
),
1192 OPC(6, OPC_ATOMIC_MIN
, atomic
.min
),
1193 OPC(6, OPC_ATOMIC_MAX
, atomic
.max
),
1194 OPC(6, OPC_ATOMIC_AND
, atomic
.and),
1195 OPC(6, OPC_ATOMIC_OR
, atomic
.or),
1196 OPC(6, OPC_ATOMIC_XOR
, atomic
.xor),
1197 OPC(6, OPC_LDGB
, ldgb
),
1198 OPC(6, OPC_STGB
, stgb
),
1199 OPC(6, OPC_STIB
, stib
),
1200 OPC(6, OPC_LDC
, ldc
),
1201 OPC(6, OPC_LDLV
, ldlv
),
1203 OPC(7, OPC_BAR
, bar
),
1204 OPC(7, OPC_FENCE
, fence
),
1209 #define GETINFO(instr) (&(opcs[((instr)->opc_cat << NOPC_BITS) | instr_opc(instr, ctx->gpu_id)]))
1211 // XXX hack.. probably should move this table somewhere common:
1213 const char *ir3_instr_name(struct ir3_instruction
*instr
)
1215 if (opc_cat(instr
->opc
) == -1) return "??meta??";
1216 return opcs
[instr
->opc
].name
;
1219 static void print_single_instr(struct disasm_ctx
*ctx
, instr_t
*instr
)
1221 const char *name
= GETINFO(instr
)->name
;
1222 uint32_t opc
= instr_opc(instr
, ctx
->gpu_id
);
1225 fprintf(ctx
->out
, "%s", name
);
1226 GETINFO(instr
)->print(ctx
, instr
);
1228 fprintf(ctx
->out
, "unknown(%d,%d)", instr
->opc_cat
, opc
);
1230 switch (instr
->opc_cat
) {
1231 case 0: print_instr_cat0(ctx
, instr
); break;
1232 case 1: print_instr_cat1(ctx
, instr
); break;
1233 case 2: print_instr_cat2(ctx
, instr
); break;
1234 case 3: print_instr_cat3(ctx
, instr
); break;
1235 case 4: print_instr_cat4(ctx
, instr
); break;
1236 case 5: print_instr_cat5(ctx
, instr
); break;
1237 case 6: print_instr_cat6(ctx
, instr
); break;
1238 case 7: print_instr_cat7(ctx
, instr
); break;
1243 static bool print_instr(struct disasm_ctx
*ctx
, uint32_t *dwords
, int n
)
1245 instr_t
*instr
= (instr_t
*)dwords
;
1246 uint32_t opc
= instr_opc(instr
, ctx
->gpu_id
);
1248 unsigned cycles
= ctx
->instructions
;
1250 if (debug
& PRINT_VERBOSE
) {
1251 fprintf(ctx
->out
, "%s%04d:%04d[%08xx_%08xx] ", levels
[ctx
->level
],
1252 n
, cycles
++, dwords
[1], dwords
[0]);
1255 /* NOTE: order flags are printed is a bit fugly.. but for now I
1256 * try to match the order in llvm-a3xx disassembler for easy
1260 ctx
->repeat
= instr_repeat(instr
);
1261 ctx
->instructions
+= 1 + ctx
->repeat
;
1264 fprintf(ctx
->out
, "(sy)");
1266 if (instr
->ss
&& ((instr
->opc_cat
<= 4) || (instr
->opc_cat
== 7))) {
1267 fprintf(ctx
->out
, "(ss)");
1270 fprintf(ctx
->out
, "(jp)");
1271 if (instr_sat(instr
))
1272 fprintf(ctx
->out
, "(sat)");
1274 fprintf(ctx
->out
, "(rpt%d)", ctx
->repeat
);
1275 else if ((instr
->opc_cat
== 2) && (instr
->cat2
.src1_r
|| instr
->cat2
.src2_r
))
1276 nop
= (instr
->cat2
.src2_r
* 2) + instr
->cat2
.src1_r
;
1277 else if ((instr
->opc_cat
== 3) && (instr
->cat3
.src1_r
|| instr
->cat3
.src2_r
))
1278 nop
= (instr
->cat3
.src2_r
* 2) + instr
->cat3
.src1_r
;
1279 ctx
->instructions
+= nop
;
1281 fprintf(ctx
->out
, "(nop%d) ", nop
);
1283 if (instr
->ul
&& ((2 <= instr
->opc_cat
) && (instr
->opc_cat
<= 4)))
1284 fprintf(ctx
->out
, "(ul)");
1286 print_single_instr(ctx
, instr
);
1287 fprintf(ctx
->out
, "\n");
1289 if ((instr
->opc_cat
<= 4) && (debug
& EXPAND_REPEAT
)) {
1291 for (i
= 0; i
< nop
; i
++) {
1292 if (debug
& PRINT_VERBOSE
) {
1293 fprintf(ctx
->out
, "%s%04d:%04d[ ] ",
1294 levels
[ctx
->level
], n
, cycles
++);
1296 fprintf(ctx
->out
, "nop\n");
1298 for (i
= 0; i
< ctx
->repeat
; i
++) {
1299 ctx
->repeatidx
= i
+ 1;
1300 if (debug
& PRINT_VERBOSE
) {
1301 fprintf(ctx
->out
, "%s%04d:%04d[ ] ",
1302 levels
[ctx
->level
], n
, cycles
++);
1304 print_single_instr(ctx
, instr
);
1305 fprintf(ctx
->out
, "\n");
1310 return (instr
->opc_cat
== 0) && (opc
== OPC_END
);
1313 int disasm_a3xx(uint32_t *dwords
, int sizedwords
, int level
, FILE *out
, unsigned gpu_id
)
1315 struct disasm_ctx ctx
;
1319 assert((sizedwords
% 2) == 0);
1321 memset(&ctx
, 0, sizeof(ctx
));
1324 ctx
.gpu_id
= gpu_id
;
1326 for (i
= 0; i
< sizedwords
; i
+= 2) {
1327 print_instr(&ctx
, &dwords
[i
], i
/2);
1328 if (dwords
[i
] == 0 && dwords
[i
+ 1] == 0)