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freedreno/ir3: fix valgrind complaint with STLW
[mesa.git] / src / freedreno / ir3 / ir3.c
1 /*
2 * Copyright (c) 2012 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include "ir3.h"
25
26 #include <stdlib.h>
27 #include <stdio.h>
28 #include <string.h>
29 #include <assert.h>
30 #include <stdbool.h>
31 #include <errno.h>
32
33 #include "util/bitscan.h"
34 #include "util/ralloc.h"
35 #include "util/u_math.h"
36
37 #include "instr-a3xx.h"
38 #include "ir3_compiler.h"
39
40 /* simple allocator to carve allocations out of an up-front allocated heap,
41 * so that we can free everything easily in one shot.
42 */
43 void * ir3_alloc(struct ir3 *shader, int sz)
44 {
45 return rzalloc_size(shader, sz); /* TODO: don't use rzalloc */
46 }
47
48 struct ir3 * ir3_create(struct ir3_compiler *compiler,
49 gl_shader_stage type, unsigned nin, unsigned nout)
50 {
51 struct ir3 *shader = rzalloc(NULL, struct ir3);
52
53 shader->compiler = compiler;
54 shader->type = type;
55 shader->ninputs = nin;
56 shader->inputs = ir3_alloc(shader, sizeof(shader->inputs[0]) * nin);
57
58 shader->noutputs = nout;
59 shader->outputs = ir3_alloc(shader, sizeof(shader->outputs[0]) * nout);
60
61 list_inithead(&shader->block_list);
62 list_inithead(&shader->array_list);
63
64 return shader;
65 }
66
67 void ir3_destroy(struct ir3 *shader)
68 {
69 ralloc_free(shader);
70 }
71
72 #define iassert(cond) do { \
73 if (!(cond)) { \
74 debug_assert(cond); \
75 return -1; \
76 } } while (0)
77
78 #define iassert_type(reg, full) do { \
79 if ((full)) { \
80 iassert(!((reg)->flags & IR3_REG_HALF)); \
81 } else { \
82 iassert((reg)->flags & IR3_REG_HALF); \
83 } } while (0);
84
85 static uint32_t reg(struct ir3_register *reg, struct ir3_info *info,
86 uint32_t repeat, uint32_t valid_flags)
87 {
88 reg_t val = { .dummy32 = 0 };
89
90 if (reg->flags & ~valid_flags) {
91 debug_printf("INVALID FLAGS: %x vs %x\n",
92 reg->flags, valid_flags);
93 }
94
95 if (!(reg->flags & IR3_REG_R))
96 repeat = 0;
97
98 if (reg->flags & IR3_REG_IMMED) {
99 val.iim_val = reg->iim_val;
100 } else {
101 unsigned components;
102 int16_t max;
103
104 if (reg->flags & IR3_REG_RELATIV) {
105 components = reg->size;
106 val.idummy10 = reg->array.offset;
107 max = (reg->array.offset + repeat + components - 1);
108 } else {
109 components = util_last_bit(reg->wrmask);
110 val.comp = reg->num & 0x3;
111 val.num = reg->num >> 2;
112 max = (reg->num + repeat + components - 1);
113 }
114
115 if (reg->flags & IR3_REG_CONST) {
116 info->max_const = MAX2(info->max_const, max >> 2);
117 } else if (val.num == 63) {
118 /* ignore writes to dummy register r63.x */
119 } else if (max < regid(48, 0)) {
120 if (reg->flags & IR3_REG_HALF) {
121 if (info->gpu_id >= 600) {
122 /* starting w/ a6xx, half regs conflict with full regs: */
123 info->max_reg = MAX2(info->max_reg, max >> 3);
124 } else {
125 info->max_half_reg = MAX2(info->max_half_reg, max >> 2);
126 }
127 } else {
128 info->max_reg = MAX2(info->max_reg, max >> 2);
129 }
130 }
131 }
132
133 return val.dummy32;
134 }
135
136 static int emit_cat0(struct ir3_instruction *instr, void *ptr,
137 struct ir3_info *info)
138 {
139 instr_cat0_t *cat0 = ptr;
140
141 if (info->gpu_id >= 500) {
142 cat0->a5xx.immed = instr->cat0.immed;
143 } else if (info->gpu_id >= 400) {
144 cat0->a4xx.immed = instr->cat0.immed;
145 } else {
146 cat0->a3xx.immed = instr->cat0.immed;
147 }
148 cat0->repeat = instr->repeat;
149 cat0->ss = !!(instr->flags & IR3_INSTR_SS);
150 cat0->inv = instr->cat0.inv;
151 cat0->comp = instr->cat0.comp;
152 cat0->opc = instr->opc;
153 cat0->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
154 cat0->sync = !!(instr->flags & IR3_INSTR_SY);
155 cat0->opc_cat = 0;
156
157 if (instr->opc == OPC_CONDEND || instr->opc == OPC_ENDPATCH)
158 cat0->dummy4 = 16;
159
160 return 0;
161 }
162
163 static int emit_cat1(struct ir3_instruction *instr, void *ptr,
164 struct ir3_info *info)
165 {
166 struct ir3_register *dst = instr->regs[0];
167 struct ir3_register *src = instr->regs[1];
168 instr_cat1_t *cat1 = ptr;
169
170 iassert(instr->regs_count == 2);
171 iassert_type(dst, type_size(instr->cat1.dst_type) == 32);
172 if (!(src->flags & IR3_REG_IMMED))
173 iassert_type(src, type_size(instr->cat1.src_type) == 32);
174
175 if (src->flags & IR3_REG_IMMED) {
176 cat1->iim_val = src->iim_val;
177 cat1->src_im = 1;
178 } else if (src->flags & IR3_REG_RELATIV) {
179 cat1->off = reg(src, info, instr->repeat,
180 IR3_REG_R | IR3_REG_CONST | IR3_REG_HALF | IR3_REG_RELATIV);
181 cat1->src_rel = 1;
182 cat1->src_rel_c = !!(src->flags & IR3_REG_CONST);
183 } else {
184 cat1->src = reg(src, info, instr->repeat,
185 IR3_REG_R | IR3_REG_CONST | IR3_REG_HALF);
186 cat1->src_c = !!(src->flags & IR3_REG_CONST);
187 }
188
189 cat1->dst = reg(dst, info, instr->repeat,
190 IR3_REG_RELATIV | IR3_REG_EVEN |
191 IR3_REG_R | IR3_REG_POS_INF | IR3_REG_HALF);
192 cat1->repeat = instr->repeat;
193 cat1->src_r = !!(src->flags & IR3_REG_R);
194 cat1->ss = !!(instr->flags & IR3_INSTR_SS);
195 cat1->ul = !!(instr->flags & IR3_INSTR_UL);
196 cat1->dst_type = instr->cat1.dst_type;
197 cat1->dst_rel = !!(dst->flags & IR3_REG_RELATIV);
198 cat1->src_type = instr->cat1.src_type;
199 cat1->even = !!(dst->flags & IR3_REG_EVEN);
200 cat1->pos_inf = !!(dst->flags & IR3_REG_POS_INF);
201 cat1->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
202 cat1->sync = !!(instr->flags & IR3_INSTR_SY);
203 cat1->opc_cat = 1;
204
205 return 0;
206 }
207
208 static int emit_cat2(struct ir3_instruction *instr, void *ptr,
209 struct ir3_info *info)
210 {
211 struct ir3_register *dst = instr->regs[0];
212 struct ir3_register *src1 = instr->regs[1];
213 struct ir3_register *src2 = instr->regs[2];
214 instr_cat2_t *cat2 = ptr;
215 unsigned absneg = ir3_cat2_absneg(instr->opc);
216
217 iassert((instr->regs_count == 2) || (instr->regs_count == 3));
218
219 if (instr->nop) {
220 iassert(!instr->repeat);
221 iassert(instr->nop <= 3);
222
223 cat2->src1_r = instr->nop & 0x1;
224 cat2->src2_r = (instr->nop >> 1) & 0x1;
225 } else {
226 cat2->src1_r = !!(src1->flags & IR3_REG_R);
227 if (src2)
228 cat2->src2_r = !!(src2->flags & IR3_REG_R);
229 }
230
231 if (src1->flags & IR3_REG_RELATIV) {
232 iassert(src1->array.offset < (1 << 10));
233 cat2->rel1.src1 = reg(src1, info, instr->repeat,
234 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
235 IR3_REG_HALF | absneg);
236 cat2->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
237 cat2->rel1.src1_rel = 1;
238 } else if (src1->flags & IR3_REG_CONST) {
239 iassert(src1->num < (1 << 12));
240 cat2->c1.src1 = reg(src1, info, instr->repeat,
241 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF |
242 absneg);
243 cat2->c1.src1_c = 1;
244 } else {
245 iassert(src1->num < (1 << 11));
246 cat2->src1 = reg(src1, info, instr->repeat,
247 IR3_REG_IMMED | IR3_REG_R | IR3_REG_HALF |
248 absneg);
249 }
250 cat2->src1_im = !!(src1->flags & IR3_REG_IMMED);
251 cat2->src1_neg = !!(src1->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
252 cat2->src1_abs = !!(src1->flags & (IR3_REG_FABS | IR3_REG_SABS));
253
254 if (src2) {
255 iassert((src2->flags & IR3_REG_IMMED) ||
256 !((src1->flags ^ src2->flags) & IR3_REG_HALF));
257
258 if (src2->flags & IR3_REG_RELATIV) {
259 iassert(src2->array.offset < (1 << 10));
260 cat2->rel2.src2 = reg(src2, info, instr->repeat,
261 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
262 IR3_REG_HALF | absneg);
263 cat2->rel2.src2_c = !!(src2->flags & IR3_REG_CONST);
264 cat2->rel2.src2_rel = 1;
265 } else if (src2->flags & IR3_REG_CONST) {
266 iassert(src2->num < (1 << 12));
267 cat2->c2.src2 = reg(src2, info, instr->repeat,
268 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF |
269 absneg);
270 cat2->c2.src2_c = 1;
271 } else {
272 iassert(src2->num < (1 << 11));
273 cat2->src2 = reg(src2, info, instr->repeat,
274 IR3_REG_IMMED | IR3_REG_R | IR3_REG_HALF |
275 absneg);
276 }
277
278 cat2->src2_im = !!(src2->flags & IR3_REG_IMMED);
279 cat2->src2_neg = !!(src2->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
280 cat2->src2_abs = !!(src2->flags & (IR3_REG_FABS | IR3_REG_SABS));
281 }
282
283 cat2->dst = reg(dst, info, instr->repeat,
284 IR3_REG_R | IR3_REG_EI | IR3_REG_HALF);
285 cat2->repeat = instr->repeat;
286 cat2->sat = !!(instr->flags & IR3_INSTR_SAT);
287 cat2->ss = !!(instr->flags & IR3_INSTR_SS);
288 cat2->ul = !!(instr->flags & IR3_INSTR_UL);
289 cat2->dst_half = !!((src1->flags ^ dst->flags) & IR3_REG_HALF);
290 cat2->ei = !!(dst->flags & IR3_REG_EI);
291 cat2->cond = instr->cat2.condition;
292 cat2->full = ! (src1->flags & IR3_REG_HALF);
293 cat2->opc = instr->opc;
294 cat2->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
295 cat2->sync = !!(instr->flags & IR3_INSTR_SY);
296 cat2->opc_cat = 2;
297
298 return 0;
299 }
300
301 static int emit_cat3(struct ir3_instruction *instr, void *ptr,
302 struct ir3_info *info)
303 {
304 struct ir3_register *dst = instr->regs[0];
305 struct ir3_register *src1 = instr->regs[1];
306 struct ir3_register *src2 = instr->regs[2];
307 struct ir3_register *src3 = instr->regs[3];
308 unsigned absneg = ir3_cat3_absneg(instr->opc);
309 instr_cat3_t *cat3 = ptr;
310 uint32_t src_flags = 0;
311
312 switch (instr->opc) {
313 case OPC_MAD_F16:
314 case OPC_MAD_U16:
315 case OPC_MAD_S16:
316 case OPC_SEL_B16:
317 case OPC_SEL_S16:
318 case OPC_SEL_F16:
319 case OPC_SAD_S16:
320 case OPC_SAD_S32: // really??
321 src_flags |= IR3_REG_HALF;
322 break;
323 default:
324 break;
325 }
326
327 iassert(instr->regs_count == 4);
328 iassert(!((src1->flags ^ src_flags) & IR3_REG_HALF));
329 iassert(!((src2->flags ^ src_flags) & IR3_REG_HALF));
330 iassert(!((src3->flags ^ src_flags) & IR3_REG_HALF));
331
332 if (instr->nop) {
333 iassert(!instr->repeat);
334 iassert(instr->nop <= 3);
335
336 cat3->src1_r = instr->nop & 0x1;
337 cat3->src2_r = (instr->nop >> 1) & 0x1;
338 } else {
339 cat3->src1_r = !!(src1->flags & IR3_REG_R);
340 cat3->src2_r = !!(src2->flags & IR3_REG_R);
341 }
342
343 if (src1->flags & IR3_REG_RELATIV) {
344 iassert(src1->array.offset < (1 << 10));
345 cat3->rel1.src1 = reg(src1, info, instr->repeat,
346 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
347 IR3_REG_HALF | absneg);
348 cat3->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
349 cat3->rel1.src1_rel = 1;
350 } else if (src1->flags & IR3_REG_CONST) {
351 iassert(src1->num < (1 << 12));
352 cat3->c1.src1 = reg(src1, info, instr->repeat,
353 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF | absneg);
354 cat3->c1.src1_c = 1;
355 } else {
356 iassert(src1->num < (1 << 11));
357 cat3->src1 = reg(src1, info, instr->repeat,
358 IR3_REG_R | IR3_REG_HALF | absneg);
359 }
360
361 cat3->src1_neg = !!(src1->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
362
363 cat3->src2 = reg(src2, info, instr->repeat,
364 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF | absneg);
365 cat3->src2_c = !!(src2->flags & IR3_REG_CONST);
366 cat3->src2_neg = !!(src2->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
367
368 if (src3->flags & IR3_REG_RELATIV) {
369 iassert(src3->array.offset < (1 << 10));
370 cat3->rel2.src3 = reg(src3, info, instr->repeat,
371 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_R |
372 IR3_REG_HALF | absneg);
373 cat3->rel2.src3_c = !!(src3->flags & IR3_REG_CONST);
374 cat3->rel2.src3_rel = 1;
375 } else if (src3->flags & IR3_REG_CONST) {
376 iassert(src3->num < (1 << 12));
377 cat3->c2.src3 = reg(src3, info, instr->repeat,
378 IR3_REG_CONST | IR3_REG_R | IR3_REG_HALF | absneg);
379 cat3->c2.src3_c = 1;
380 } else {
381 iassert(src3->num < (1 << 11));
382 cat3->src3 = reg(src3, info, instr->repeat,
383 IR3_REG_R | IR3_REG_HALF | absneg);
384 }
385
386 cat3->src3_neg = !!(src3->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT));
387 cat3->src3_r = !!(src3->flags & IR3_REG_R);
388
389 cat3->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
390 cat3->repeat = instr->repeat;
391 cat3->sat = !!(instr->flags & IR3_INSTR_SAT);
392 cat3->ss = !!(instr->flags & IR3_INSTR_SS);
393 cat3->ul = !!(instr->flags & IR3_INSTR_UL);
394 cat3->dst_half = !!((src_flags ^ dst->flags) & IR3_REG_HALF);
395 cat3->opc = instr->opc;
396 cat3->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
397 cat3->sync = !!(instr->flags & IR3_INSTR_SY);
398 cat3->opc_cat = 3;
399
400 return 0;
401 }
402
403 static int emit_cat4(struct ir3_instruction *instr, void *ptr,
404 struct ir3_info *info)
405 {
406 struct ir3_register *dst = instr->regs[0];
407 struct ir3_register *src = instr->regs[1];
408 instr_cat4_t *cat4 = ptr;
409
410 iassert(instr->regs_count == 2);
411
412 if (src->flags & IR3_REG_RELATIV) {
413 iassert(src->array.offset < (1 << 10));
414 cat4->rel.src = reg(src, info, instr->repeat,
415 IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_FNEG |
416 IR3_REG_FABS | IR3_REG_R | IR3_REG_HALF);
417 cat4->rel.src_c = !!(src->flags & IR3_REG_CONST);
418 cat4->rel.src_rel = 1;
419 } else if (src->flags & IR3_REG_CONST) {
420 iassert(src->num < (1 << 12));
421 cat4->c.src = reg(src, info, instr->repeat,
422 IR3_REG_CONST | IR3_REG_FNEG | IR3_REG_FABS |
423 IR3_REG_R | IR3_REG_HALF);
424 cat4->c.src_c = 1;
425 } else {
426 iassert(src->num < (1 << 11));
427 cat4->src = reg(src, info, instr->repeat,
428 IR3_REG_IMMED | IR3_REG_FNEG | IR3_REG_FABS |
429 IR3_REG_R | IR3_REG_HALF);
430 }
431
432 cat4->src_im = !!(src->flags & IR3_REG_IMMED);
433 cat4->src_neg = !!(src->flags & IR3_REG_FNEG);
434 cat4->src_abs = !!(src->flags & IR3_REG_FABS);
435 cat4->src_r = !!(src->flags & IR3_REG_R);
436
437 cat4->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
438 cat4->repeat = instr->repeat;
439 cat4->sat = !!(instr->flags & IR3_INSTR_SAT);
440 cat4->ss = !!(instr->flags & IR3_INSTR_SS);
441 cat4->ul = !!(instr->flags & IR3_INSTR_UL);
442 cat4->dst_half = !!((src->flags ^ dst->flags) & IR3_REG_HALF);
443 cat4->full = ! (src->flags & IR3_REG_HALF);
444 cat4->opc = instr->opc;
445 cat4->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
446 cat4->sync = !!(instr->flags & IR3_INSTR_SY);
447 cat4->opc_cat = 4;
448
449 return 0;
450 }
451
452 static int emit_cat5(struct ir3_instruction *instr, void *ptr,
453 struct ir3_info *info)
454 {
455 struct ir3_register *dst = instr->regs[0];
456 /* To simplify things when there could be zero, one, or two args other
457 * than tex/sampler idx, we use the first src reg in the ir to hold
458 * samp_tex hvec2:
459 */
460 struct ir3_register *src1;
461 struct ir3_register *src2;
462 instr_cat5_t *cat5 = ptr;
463
464 iassert((instr->regs_count == 2) ||
465 (instr->regs_count == 3) || (instr->regs_count == 4));
466
467 switch (instr->opc) {
468 case OPC_DSX:
469 case OPC_DSXPP_1:
470 case OPC_DSY:
471 case OPC_DSYPP_1:
472 case OPC_RGETPOS:
473 case OPC_RGETINFO:
474 iassert((instr->flags & IR3_INSTR_S2EN) == 0);
475 src1 = instr->regs[1];
476 src2 = instr->regs_count > 2 ? instr->regs[2] : NULL;
477 break;
478 default:
479 src1 = instr->regs[2];
480 src2 = instr->regs_count > 3 ? instr->regs[3] : NULL;
481 break;
482 }
483
484 assume(src1 || !src2);
485
486 if (src1) {
487 cat5->full = ! (src1->flags & IR3_REG_HALF);
488 cat5->src1 = reg(src1, info, instr->repeat, IR3_REG_HALF);
489 }
490
491 if (instr->flags & IR3_INSTR_S2EN) {
492 struct ir3_register *samp_tex = instr->regs[1];
493 if (src2) {
494 iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
495 cat5->s2en.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
496 }
497 iassert(samp_tex->flags & IR3_REG_HALF);
498 cat5->s2en.src3 = reg(samp_tex, info, instr->repeat, IR3_REG_HALF);
499 iassert(!(instr->cat5.samp | instr->cat5.tex));
500 } else {
501 if (src2) {
502 iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
503 cat5->norm.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
504 }
505 cat5->norm.samp = instr->cat5.samp;
506 cat5->norm.tex = instr->cat5.tex;
507 }
508
509 cat5->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
510 cat5->wrmask = dst->wrmask;
511 cat5->type = instr->cat5.type;
512 cat5->is_3d = !!(instr->flags & IR3_INSTR_3D);
513 cat5->is_a = !!(instr->flags & IR3_INSTR_A);
514 cat5->is_s = !!(instr->flags & IR3_INSTR_S);
515 cat5->is_s2en = !!(instr->flags & IR3_INSTR_S2EN);
516 cat5->is_o = !!(instr->flags & IR3_INSTR_O);
517 cat5->is_p = !!(instr->flags & IR3_INSTR_P);
518 cat5->opc = instr->opc;
519 cat5->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
520 cat5->sync = !!(instr->flags & IR3_INSTR_SY);
521 cat5->opc_cat = 5;
522
523 return 0;
524 }
525
526 static int emit_cat6_a6xx(struct ir3_instruction *instr, void *ptr,
527 struct ir3_info *info)
528 {
529 struct ir3_register *src1, *src2;
530 instr_cat6_a6xx_t *cat6 = ptr;
531 bool has_dest = (instr->opc == OPC_LDIB);
532
533 /* first reg should be SSBO binding point: */
534 iassert(instr->regs[1]->flags & IR3_REG_IMMED);
535
536 src1 = instr->regs[2];
537
538 if (has_dest) {
539 /* the src2 field in the instruction is actually the destination
540 * register for load instructions:
541 */
542 src2 = instr->regs[0];
543 } else {
544 src2 = instr->regs[3];
545 }
546
547 cat6->type = instr->cat6.type;
548 cat6->d = instr->cat6.d - 1;
549 cat6->typed = instr->cat6.typed;
550 cat6->type_size = instr->cat6.iim_val - 1;
551 cat6->opc = instr->opc;
552 cat6->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
553 cat6->sync = !!(instr->flags & IR3_INSTR_SY);
554 cat6->opc_cat = 6;
555
556 cat6->src1 = reg(src1, info, instr->repeat, 0);
557 cat6->src2 = reg(src2, info, instr->repeat, 0);
558 cat6->ssbo = instr->regs[1]->iim_val;
559
560 switch (instr->opc) {
561 case OPC_ATOMIC_ADD:
562 case OPC_ATOMIC_SUB:
563 case OPC_ATOMIC_XCHG:
564 case OPC_ATOMIC_INC:
565 case OPC_ATOMIC_DEC:
566 case OPC_ATOMIC_CMPXCHG:
567 case OPC_ATOMIC_MIN:
568 case OPC_ATOMIC_MAX:
569 case OPC_ATOMIC_AND:
570 case OPC_ATOMIC_OR:
571 case OPC_ATOMIC_XOR:
572 cat6->pad1 = 0x1;
573 cat6->pad2 = 0xc;
574 cat6->pad3 = 0x0;
575 cat6->pad4 = 0x3;
576 break;
577 case OPC_STIB:
578 cat6->pad1 = 0x0;
579 cat6->pad2 = 0xc;
580 cat6->pad3 = 0x0;
581 cat6->pad4 = 0x2;
582 break;
583 case OPC_LDIB:
584 cat6->pad1 = 0x1;
585 cat6->pad2 = 0xc;
586 cat6->pad3 = 0x0;
587 cat6->pad4 = 0x2;
588 break;
589 case OPC_LDC:
590 cat6->pad1 = 0x0;
591 cat6->pad2 = 0x8;
592 cat6->pad3 = 0x0;
593 cat6->pad4 = 0x2;
594 break;
595 default:
596 iassert(0);
597 }
598
599 return 0;
600 }
601
602 static int emit_cat6(struct ir3_instruction *instr, void *ptr,
603 struct ir3_info *info)
604 {
605 struct ir3_register *dst, *src1, *src2;
606 instr_cat6_t *cat6 = ptr;
607
608 /* In a6xx we start using a new instruction encoding for some of
609 * these instructions:
610 */
611 if (info->gpu_id >= 600) {
612 switch (instr->opc) {
613 case OPC_ATOMIC_ADD:
614 case OPC_ATOMIC_SUB:
615 case OPC_ATOMIC_XCHG:
616 case OPC_ATOMIC_INC:
617 case OPC_ATOMIC_DEC:
618 case OPC_ATOMIC_CMPXCHG:
619 case OPC_ATOMIC_MIN:
620 case OPC_ATOMIC_MAX:
621 case OPC_ATOMIC_AND:
622 case OPC_ATOMIC_OR:
623 case OPC_ATOMIC_XOR:
624 /* The shared variants of these still use the old encoding: */
625 if (!(instr->flags & IR3_INSTR_G))
626 break;
627 /* fallthrough */
628 case OPC_STIB:
629 case OPC_LDIB:
630 case OPC_LDC:
631 return emit_cat6_a6xx(instr, ptr, info);
632 default:
633 break;
634 }
635 }
636
637 bool type_full = type_size(instr->cat6.type) == 32;
638
639 cat6->type = instr->cat6.type;
640 cat6->opc = instr->opc;
641 cat6->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
642 cat6->sync = !!(instr->flags & IR3_INSTR_SY);
643 cat6->g = !!(instr->flags & IR3_INSTR_G);
644 cat6->opc_cat = 6;
645
646 switch (instr->opc) {
647 case OPC_RESINFO:
648 case OPC_RESFMT:
649 iassert_type(instr->regs[0], type_full); /* dst */
650 iassert_type(instr->regs[1], type_full); /* src1 */
651 break;
652 case OPC_L2G:
653 case OPC_G2L:
654 iassert_type(instr->regs[0], true); /* dst */
655 iassert_type(instr->regs[1], true); /* src1 */
656 break;
657 case OPC_STG:
658 case OPC_STL:
659 case OPC_STP:
660 case OPC_STLW:
661 case OPC_STIB:
662 /* no dst, so regs[0] is dummy */
663 iassert_type(instr->regs[1], true); /* dst */
664 iassert_type(instr->regs[2], type_full); /* src1 */
665 iassert_type(instr->regs[3], true); /* src2 */
666 break;
667 default:
668 iassert_type(instr->regs[0], type_full); /* dst */
669 iassert_type(instr->regs[1], true); /* src1 */
670 if (instr->regs_count > 2)
671 iassert_type(instr->regs[2], true); /* src1 */
672 break;
673 }
674
675 /* the "dst" for a store instruction is (from the perspective
676 * of data flow in the shader, ie. register use/def, etc) in
677 * fact a register that is read by the instruction, rather
678 * than written:
679 */
680 if (is_store(instr)) {
681 iassert(instr->regs_count >= 3);
682
683 dst = instr->regs[1];
684 src1 = instr->regs[2];
685 src2 = (instr->regs_count >= 4) ? instr->regs[3] : NULL;
686 } else {
687 iassert(instr->regs_count >= 2);
688
689 dst = instr->regs[0];
690 src1 = instr->regs[1];
691 src2 = (instr->regs_count >= 3) ? instr->regs[2] : NULL;
692 }
693
694 /* TODO we need a more comprehensive list about which instructions
695 * can be encoded which way. Or possibly use IR3_INSTR_0 flag to
696 * indicate to use the src_off encoding even if offset is zero
697 * (but then what to do about dst_off?)
698 */
699 if (is_atomic(instr->opc)) {
700 instr_cat6ldgb_t *ldgb = ptr;
701
702 /* maybe these two bits both determine the instruction encoding? */
703 cat6->src_off = false;
704
705 ldgb->d = instr->cat6.d - 1;
706 ldgb->typed = instr->cat6.typed;
707 ldgb->type_size = instr->cat6.iim_val - 1;
708
709 ldgb->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
710
711 if (ldgb->g) {
712 struct ir3_register *src3 = instr->regs[3];
713 struct ir3_register *src4 = instr->regs[4];
714
715 /* first src is src_ssbo: */
716 iassert(src1->flags & IR3_REG_IMMED);
717 ldgb->src_ssbo = src1->uim_val;
718
719 ldgb->src1 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
720 ldgb->src1_im = !!(src2->flags & IR3_REG_IMMED);
721 ldgb->src2 = reg(src3, info, instr->repeat, IR3_REG_IMMED);
722 ldgb->src2_im = !!(src3->flags & IR3_REG_IMMED);
723
724 ldgb->src3 = reg(src4, info, instr->repeat, 0);
725 ldgb->pad0 = 0x1;
726 ldgb->pad3 = 0x1;
727 } else {
728 ldgb->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED);
729 ldgb->src1_im = !!(src1->flags & IR3_REG_IMMED);
730 ldgb->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
731 ldgb->src2_im = !!(src2->flags & IR3_REG_IMMED);
732 ldgb->pad0 = 0x1;
733 ldgb->pad3 = 0x0;
734 }
735
736 return 0;
737 } else if (instr->opc == OPC_LDGB) {
738 struct ir3_register *src3 = instr->regs[3];
739 instr_cat6ldgb_t *ldgb = ptr;
740
741 /* maybe these two bits both determine the instruction encoding? */
742 cat6->src_off = false;
743
744 ldgb->d = instr->cat6.d - 1;
745 ldgb->typed = instr->cat6.typed;
746 ldgb->type_size = instr->cat6.iim_val - 1;
747
748 ldgb->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
749
750 /* first src is src_ssbo: */
751 iassert(src1->flags & IR3_REG_IMMED);
752 ldgb->src_ssbo = src1->uim_val;
753
754 /* then next two are src1/src2: */
755 ldgb->src1 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
756 ldgb->src1_im = !!(src2->flags & IR3_REG_IMMED);
757 ldgb->src2 = reg(src3, info, instr->repeat, IR3_REG_IMMED);
758 ldgb->src2_im = !!(src3->flags & IR3_REG_IMMED);
759
760 ldgb->pad0 = 0x0;
761 ldgb->pad3 = 0x1;
762
763 return 0;
764 } else if (instr->opc == OPC_RESINFO) {
765 instr_cat6ldgb_t *ldgb = ptr;
766
767 ldgb->d = instr->cat6.d - 1;
768
769 ldgb->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
770
771 /* first src is src_ssbo: */
772 iassert(src1->flags & IR3_REG_IMMED);
773 ldgb->src_ssbo = src1->uim_val;
774
775 return 0;
776 } else if ((instr->opc == OPC_STGB) || (instr->opc == OPC_STIB)) {
777 struct ir3_register *src3 = instr->regs[4];
778 instr_cat6stgb_t *stgb = ptr;
779
780 /* maybe these two bits both determine the instruction encoding? */
781 cat6->src_off = true;
782 stgb->pad3 = 0x2;
783
784 stgb->d = instr->cat6.d - 1;
785 stgb->typed = instr->cat6.typed;
786 stgb->type_size = instr->cat6.iim_val - 1;
787
788 /* first src is dst_ssbo: */
789 iassert(dst->flags & IR3_REG_IMMED);
790 stgb->dst_ssbo = dst->uim_val;
791
792 /* then src1/src2/src3: */
793 stgb->src1 = reg(src1, info, instr->repeat, 0);
794 stgb->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
795 stgb->src2_im = !!(src2->flags & IR3_REG_IMMED);
796 stgb->src3 = reg(src3, info, instr->repeat, IR3_REG_IMMED);
797 stgb->src3_im = !!(src3->flags & IR3_REG_IMMED);
798
799 return 0;
800 } else if (instr->cat6.src_offset || (instr->opc == OPC_LDG) ||
801 (instr->opc == OPC_LDL) || (instr->opc == OPC_LDLW)) {
802 struct ir3_register *src3 = instr->regs[3];
803 instr_cat6a_t *cat6a = ptr;
804
805 cat6->src_off = true;
806
807 if (instr->opc == OPC_LDG) {
808 /* For LDG src1 can not be immediate, so src1_imm is redundant and
809 * instead used to signal whether (when true) 'off' is a 32 bit
810 * register or an immediate offset.
811 */
812 cat6a->src1 = reg(src1, info, instr->repeat, 0);
813 cat6a->src1_im = !(src3->flags & IR3_REG_IMMED);
814 cat6a->off = reg(src3, info, instr->repeat, IR3_REG_IMMED);
815 } else {
816 cat6a->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED);
817 cat6a->src1_im = !!(src1->flags & IR3_REG_IMMED);
818 cat6a->off = reg(src3, info, instr->repeat, IR3_REG_IMMED);
819 iassert(src3->flags & IR3_REG_IMMED);
820 }
821
822 /* Num components */
823 cat6a->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
824 cat6a->src2_im = true;
825 } else {
826 instr_cat6b_t *cat6b = ptr;
827
828 cat6->src_off = false;
829
830 cat6b->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED | IR3_REG_HALF);
831 cat6b->src1_im = !!(src1->flags & IR3_REG_IMMED);
832 if (src2) {
833 cat6b->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
834 cat6b->src2_im = !!(src2->flags & IR3_REG_IMMED);
835 }
836 }
837
838 if (instr->cat6.dst_offset || (instr->opc == OPC_STG) ||
839 (instr->opc == OPC_STL) || (instr->opc == OPC_STLW)) {
840 instr_cat6c_t *cat6c = ptr;
841 cat6->dst_off = true;
842 cat6c->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
843
844 if (instr->flags & IR3_INSTR_G) {
845 struct ir3_register *src3 = instr->regs[4];
846 cat6c->off = reg(src3, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
847 if (src3->flags & IR3_REG_IMMED) {
848 /* Immediate offsets are in bytes... */
849 cat6->g = false;
850 cat6c->off *= 4;
851 }
852 } else {
853 cat6c->off = instr->cat6.dst_offset;
854 }
855 } else {
856 instr_cat6d_t *cat6d = ptr;
857 cat6->dst_off = false;
858 cat6d->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
859 }
860
861 return 0;
862 }
863
864 static int emit_cat7(struct ir3_instruction *instr, void *ptr,
865 struct ir3_info *info)
866 {
867 instr_cat7_t *cat7 = ptr;
868
869 cat7->ss = !!(instr->flags & IR3_INSTR_SS);
870 cat7->w = instr->cat7.w;
871 cat7->r = instr->cat7.r;
872 cat7->l = instr->cat7.l;
873 cat7->g = instr->cat7.g;
874 cat7->opc = instr->opc;
875 cat7->jmp_tgt = !!(instr->flags & IR3_INSTR_JP);
876 cat7->sync = !!(instr->flags & IR3_INSTR_SY);
877 cat7->opc_cat = 7;
878
879 return 0;
880 }
881
882 static int (*emit[])(struct ir3_instruction *instr, void *ptr,
883 struct ir3_info *info) = {
884 emit_cat0, emit_cat1, emit_cat2, emit_cat3, emit_cat4, emit_cat5, emit_cat6,
885 emit_cat7,
886 };
887
888 void * ir3_assemble(struct ir3 *shader, struct ir3_info *info,
889 uint32_t gpu_id)
890 {
891 uint32_t *ptr, *dwords;
892
893 info->gpu_id = gpu_id;
894 info->max_reg = -1;
895 info->max_half_reg = -1;
896 info->max_const = -1;
897 info->instrs_count = 0;
898 info->sizedwords = 0;
899 info->ss = info->sy = 0;
900
901 list_for_each_entry (struct ir3_block, block, &shader->block_list, node) {
902 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
903 info->sizedwords += 2;
904 }
905 }
906
907 /* need an integer number of instruction "groups" (sets of 16
908 * instructions on a4xx or sets of 4 instructions on a3xx),
909 * so pad out w/ NOPs if needed: (NOTE each instruction is 64bits)
910 */
911 if (gpu_id >= 400) {
912 info->sizedwords = align(info->sizedwords, 16 * 2);
913 } else {
914 info->sizedwords = align(info->sizedwords, 4 * 2);
915 }
916
917 ptr = dwords = calloc(4, info->sizedwords);
918
919 list_for_each_entry (struct ir3_block, block, &shader->block_list, node) {
920 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
921 int ret = emit[opc_cat(instr->opc)](instr, dwords, info);
922 if (ret)
923 goto fail;
924 info->instrs_count += 1 + instr->repeat + instr->nop;
925 info->nops_count += instr->nop;
926 if (instr->opc == OPC_NOP)
927 info->nops_count += 1 + instr->repeat;
928 dwords += 2;
929
930 if (instr->flags & IR3_INSTR_SS)
931 info->ss++;
932
933 if (instr->flags & IR3_INSTR_SY)
934 info->sy++;
935 }
936 }
937
938 return ptr;
939
940 fail:
941 free(ptr);
942 return NULL;
943 }
944
945 static struct ir3_register * reg_create(struct ir3 *shader,
946 int num, int flags)
947 {
948 struct ir3_register *reg =
949 ir3_alloc(shader, sizeof(struct ir3_register));
950 reg->wrmask = 1;
951 reg->flags = flags;
952 reg->num = num;
953 if (shader->compiler->gpu_id >= 600)
954 reg->merged = true;
955 return reg;
956 }
957
958 static void insert_instr(struct ir3_block *block,
959 struct ir3_instruction *instr)
960 {
961 struct ir3 *shader = block->shader;
962 #ifdef DEBUG
963 instr->serialno = ++shader->instr_count;
964 #endif
965 list_addtail(&instr->node, &block->instr_list);
966
967 if (is_input(instr))
968 array_insert(shader, shader->baryfs, instr);
969 }
970
971 struct ir3_block * ir3_block_create(struct ir3 *shader)
972 {
973 struct ir3_block *block = ir3_alloc(shader, sizeof(*block));
974 #ifdef DEBUG
975 block->serialno = ++shader->block_count;
976 #endif
977 block->shader = shader;
978 list_inithead(&block->node);
979 list_inithead(&block->instr_list);
980 return block;
981 }
982
983 static struct ir3_instruction *instr_create(struct ir3_block *block, int nreg)
984 {
985 struct ir3_instruction *instr;
986 unsigned sz = sizeof(*instr) + (nreg * sizeof(instr->regs[0]));
987 char *ptr = ir3_alloc(block->shader, sz);
988
989 instr = (struct ir3_instruction *)ptr;
990 ptr += sizeof(*instr);
991 instr->regs = (struct ir3_register **)ptr;
992
993 #ifdef DEBUG
994 instr->regs_max = nreg;
995 #endif
996
997 return instr;
998 }
999
1000 struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
1001 opc_t opc, int nreg)
1002 {
1003 struct ir3_instruction *instr = instr_create(block, nreg);
1004 instr->block = block;
1005 instr->opc = opc;
1006 insert_instr(block, instr);
1007 return instr;
1008 }
1009
1010 struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc)
1011 {
1012 /* NOTE: we could be slightly more clever, at least for non-meta,
1013 * and choose # of regs based on category.
1014 */
1015 return ir3_instr_create2(block, opc, 4);
1016 }
1017
1018 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr)
1019 {
1020 struct ir3_instruction *new_instr = instr_create(instr->block,
1021 instr->regs_count);
1022 struct ir3_register **regs;
1023 unsigned i;
1024
1025 regs = new_instr->regs;
1026 *new_instr = *instr;
1027 new_instr->regs = regs;
1028
1029 insert_instr(instr->block, new_instr);
1030
1031 /* clone registers: */
1032 new_instr->regs_count = 0;
1033 for (i = 0; i < instr->regs_count; i++) {
1034 struct ir3_register *reg = instr->regs[i];
1035 struct ir3_register *new_reg =
1036 ir3_reg_create(new_instr, reg->num, reg->flags);
1037 *new_reg = *reg;
1038 }
1039
1040 return new_instr;
1041 }
1042
1043 /* Add a false dependency to instruction, to ensure it is scheduled first: */
1044 void ir3_instr_add_dep(struct ir3_instruction *instr, struct ir3_instruction *dep)
1045 {
1046 array_insert(instr, instr->deps, dep);
1047 }
1048
1049 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
1050 int num, int flags)
1051 {
1052 struct ir3 *shader = instr->block->shader;
1053 struct ir3_register *reg = reg_create(shader, num, flags);
1054 #ifdef DEBUG
1055 debug_assert(instr->regs_count < instr->regs_max);
1056 #endif
1057 instr->regs[instr->regs_count++] = reg;
1058 return reg;
1059 }
1060
1061 struct ir3_register * ir3_reg_clone(struct ir3 *shader,
1062 struct ir3_register *reg)
1063 {
1064 struct ir3_register *new_reg = reg_create(shader, 0, 0);
1065 *new_reg = *reg;
1066 return new_reg;
1067 }
1068
1069 void
1070 ir3_instr_set_address(struct ir3_instruction *instr,
1071 struct ir3_instruction *addr)
1072 {
1073 if (instr->address != addr) {
1074 struct ir3 *ir = instr->block->shader;
1075
1076 debug_assert(!instr->address);
1077 debug_assert(instr->block == addr->block);
1078
1079 instr->address = addr;
1080 array_insert(ir, ir->indirects, instr);
1081 }
1082 }
1083
1084 void
1085 ir3_block_clear_mark(struct ir3_block *block)
1086 {
1087 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node)
1088 instr->flags &= ~IR3_INSTR_MARK;
1089 }
1090
1091 void
1092 ir3_clear_mark(struct ir3 *ir)
1093 {
1094 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
1095 ir3_block_clear_mark(block);
1096 }
1097 }
1098
1099 /* note: this will destroy instr->depth, don't do it until after sched! */
1100 unsigned
1101 ir3_count_instructions(struct ir3 *ir)
1102 {
1103 unsigned cnt = 0;
1104 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
1105 block->start_ip = cnt;
1106 block->end_ip = cnt;
1107 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
1108 instr->ip = cnt++;
1109 block->end_ip = instr->ip;
1110 }
1111 }
1112 return cnt;
1113 }
1114
1115 struct ir3_array *
1116 ir3_lookup_array(struct ir3 *ir, unsigned id)
1117 {
1118 list_for_each_entry (struct ir3_array, arr, &ir->array_list, node)
1119 if (arr->id == id)
1120 return arr;
1121 return NULL;
1122 }