2 * Copyright (c) 2012 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include "util/bitscan.h"
34 #include "util/ralloc.h"
35 #include "util/u_math.h"
37 #include "instr-a3xx.h"
38 #include "ir3_shader.h"
40 /* simple allocator to carve allocations out of an up-front allocated heap,
41 * so that we can free everything easily in one shot.
43 void * ir3_alloc(struct ir3
*shader
, int sz
)
45 return rzalloc_size(shader
, sz
); /* TODO: don't use rzalloc */
48 struct ir3
* ir3_create(struct ir3_compiler
*compiler
,
49 struct ir3_shader_variant
*v
)
51 struct ir3
*shader
= rzalloc(v
, struct ir3
);
53 shader
->compiler
= compiler
;
54 shader
->type
= v
->type
;
56 list_inithead(&shader
->block_list
);
57 list_inithead(&shader
->array_list
);
62 void ir3_destroy(struct ir3
*shader
)
67 #define iassert(cond) do { \
73 #define iassert_type(reg, full) do { \
75 iassert(!((reg)->flags & IR3_REG_HALF)); \
77 iassert((reg)->flags & IR3_REG_HALF); \
80 static uint32_t reg(struct ir3_register
*reg
, struct ir3_info
*info
,
81 uint32_t repeat
, uint32_t valid_flags
)
83 struct ir3_shader_variant
*v
= info
->data
;
84 reg_t val
= { .dummy32
= 0 };
86 if (reg
->flags
& ~valid_flags
) {
87 debug_printf("INVALID FLAGS: %x vs %x\n",
88 reg
->flags
, valid_flags
);
91 if (!(reg
->flags
& IR3_REG_R
))
94 if (reg
->flags
& IR3_REG_IMMED
) {
95 val
.iim_val
= reg
->iim_val
;
100 if (reg
->flags
& IR3_REG_RELATIV
) {
101 components
= reg
->size
;
102 val
.idummy10
= reg
->array
.offset
;
103 max
= (reg
->array
.offset
+ repeat
+ components
- 1);
105 components
= util_last_bit(reg
->wrmask
);
106 val
.comp
= reg
->num
& 0x3;
107 val
.num
= reg
->num
>> 2;
108 max
= (reg
->num
+ repeat
+ components
- 1);
111 if (reg
->flags
& IR3_REG_CONST
) {
112 info
->max_const
= MAX2(info
->max_const
, max
>> 2);
113 } else if (val
.num
== 63) {
114 /* ignore writes to dummy register r63.x */
115 } else if (max
< regid(48, 0)) {
116 if (reg
->flags
& IR3_REG_HALF
) {
118 /* starting w/ a6xx, half regs conflict with full regs: */
119 info
->max_reg
= MAX2(info
->max_reg
, max
>> 3);
121 info
->max_half_reg
= MAX2(info
->max_half_reg
, max
>> 2);
124 info
->max_reg
= MAX2(info
->max_reg
, max
>> 2);
132 static int emit_cat0(struct ir3_instruction
*instr
, void *ptr
,
133 struct ir3_info
*info
)
135 struct ir3_shader_variant
*v
= info
->data
;
136 instr_cat0_t
*cat0
= ptr
;
138 if (v
->shader
->compiler
->gpu_id
>= 500) {
139 cat0
->a5xx
.immed
= instr
->cat0
.immed
;
140 } else if (v
->shader
->compiler
->gpu_id
>= 400) {
141 cat0
->a4xx
.immed
= instr
->cat0
.immed
;
143 cat0
->a3xx
.immed
= instr
->cat0
.immed
;
145 cat0
->repeat
= instr
->repeat
;
146 cat0
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
147 cat0
->inv0
= instr
->cat0
.inv
;
148 cat0
->comp0
= instr
->cat0
.comp
;
149 cat0
->opc
= instr
->opc
;
150 cat0
->opc_hi
= instr
->opc
>= 16;
151 cat0
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
152 cat0
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
158 static int emit_cat1(struct ir3_instruction
*instr
, void *ptr
,
159 struct ir3_info
*info
)
161 struct ir3_register
*dst
= instr
->regs
[0];
162 struct ir3_register
*src
= instr
->regs
[1];
163 instr_cat1_t
*cat1
= ptr
;
165 iassert(instr
->regs_count
== 2);
166 iassert_type(dst
, type_size(instr
->cat1
.dst_type
) == 32);
167 if (!(src
->flags
& IR3_REG_IMMED
))
168 iassert_type(src
, type_size(instr
->cat1
.src_type
) == 32);
170 if (src
->flags
& IR3_REG_IMMED
) {
171 cat1
->iim_val
= src
->iim_val
;
173 } else if (src
->flags
& IR3_REG_RELATIV
) {
174 cat1
->off
= reg(src
, info
, instr
->repeat
,
175 IR3_REG_R
| IR3_REG_CONST
| IR3_REG_HALF
| IR3_REG_RELATIV
);
177 cat1
->src_rel_c
= !!(src
->flags
& IR3_REG_CONST
);
179 cat1
->src
= reg(src
, info
, instr
->repeat
,
180 IR3_REG_R
| IR3_REG_CONST
| IR3_REG_HALF
);
181 cat1
->src_c
= !!(src
->flags
& IR3_REG_CONST
);
184 cat1
->dst
= reg(dst
, info
, instr
->repeat
,
185 IR3_REG_RELATIV
| IR3_REG_EVEN
|
186 IR3_REG_R
| IR3_REG_POS_INF
| IR3_REG_HALF
);
187 cat1
->repeat
= instr
->repeat
;
188 cat1
->src_r
= !!(src
->flags
& IR3_REG_R
);
189 cat1
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
190 cat1
->ul
= !!(instr
->flags
& IR3_INSTR_UL
);
191 cat1
->dst_type
= instr
->cat1
.dst_type
;
192 cat1
->dst_rel
= !!(dst
->flags
& IR3_REG_RELATIV
);
193 cat1
->src_type
= instr
->cat1
.src_type
;
194 cat1
->even
= !!(dst
->flags
& IR3_REG_EVEN
);
195 cat1
->pos_inf
= !!(dst
->flags
& IR3_REG_POS_INF
);
196 cat1
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
197 cat1
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
203 static int emit_cat2(struct ir3_instruction
*instr
, void *ptr
,
204 struct ir3_info
*info
)
206 struct ir3_register
*dst
= instr
->regs
[0];
207 struct ir3_register
*src1
= instr
->regs
[1];
208 struct ir3_register
*src2
= instr
->regs
[2];
209 instr_cat2_t
*cat2
= ptr
;
210 unsigned absneg
= ir3_cat2_absneg(instr
->opc
);
212 iassert((instr
->regs_count
== 2) || (instr
->regs_count
== 3));
215 iassert(!instr
->repeat
);
216 iassert(instr
->nop
<= 3);
218 cat2
->src1_r
= instr
->nop
& 0x1;
219 cat2
->src2_r
= (instr
->nop
>> 1) & 0x1;
221 cat2
->src1_r
= !!(src1
->flags
& IR3_REG_R
);
223 cat2
->src2_r
= !!(src2
->flags
& IR3_REG_R
);
226 if (src1
->flags
& IR3_REG_RELATIV
) {
227 iassert(src1
->array
.offset
< (1 << 10));
228 cat2
->rel1
.src1
= reg(src1
, info
, instr
->repeat
,
229 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_R
|
230 IR3_REG_HALF
| absneg
);
231 cat2
->rel1
.src1_c
= !!(src1
->flags
& IR3_REG_CONST
);
232 cat2
->rel1
.src1_rel
= 1;
233 } else if (src1
->flags
& IR3_REG_CONST
) {
234 iassert(src1
->num
< (1 << 12));
235 cat2
->c1
.src1
= reg(src1
, info
, instr
->repeat
,
236 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
|
240 iassert(src1
->num
< (1 << 11));
241 cat2
->src1
= reg(src1
, info
, instr
->repeat
,
242 IR3_REG_IMMED
| IR3_REG_R
| IR3_REG_HALF
|
245 cat2
->src1_im
= !!(src1
->flags
& IR3_REG_IMMED
);
246 cat2
->src1_neg
= !!(src1
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
247 cat2
->src1_abs
= !!(src1
->flags
& (IR3_REG_FABS
| IR3_REG_SABS
));
250 iassert((src2
->flags
& IR3_REG_IMMED
) ||
251 !((src1
->flags
^ src2
->flags
) & IR3_REG_HALF
));
253 if (src2
->flags
& IR3_REG_RELATIV
) {
254 iassert(src2
->array
.offset
< (1 << 10));
255 cat2
->rel2
.src2
= reg(src2
, info
, instr
->repeat
,
256 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_R
|
257 IR3_REG_HALF
| absneg
);
258 cat2
->rel2
.src2_c
= !!(src2
->flags
& IR3_REG_CONST
);
259 cat2
->rel2
.src2_rel
= 1;
260 } else if (src2
->flags
& IR3_REG_CONST
) {
261 iassert(src2
->num
< (1 << 12));
262 cat2
->c2
.src2
= reg(src2
, info
, instr
->repeat
,
263 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
|
267 iassert(src2
->num
< (1 << 11));
268 cat2
->src2
= reg(src2
, info
, instr
->repeat
,
269 IR3_REG_IMMED
| IR3_REG_R
| IR3_REG_HALF
|
273 cat2
->src2_im
= !!(src2
->flags
& IR3_REG_IMMED
);
274 cat2
->src2_neg
= !!(src2
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
275 cat2
->src2_abs
= !!(src2
->flags
& (IR3_REG_FABS
| IR3_REG_SABS
));
278 cat2
->dst
= reg(dst
, info
, instr
->repeat
,
279 IR3_REG_R
| IR3_REG_EI
| IR3_REG_HALF
);
280 cat2
->repeat
= instr
->repeat
;
281 cat2
->sat
= !!(instr
->flags
& IR3_INSTR_SAT
);
282 cat2
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
283 cat2
->ul
= !!(instr
->flags
& IR3_INSTR_UL
);
284 cat2
->dst_half
= !!((src1
->flags
^ dst
->flags
) & IR3_REG_HALF
);
285 cat2
->ei
= !!(dst
->flags
& IR3_REG_EI
);
286 cat2
->cond
= instr
->cat2
.condition
;
287 cat2
->full
= ! (src1
->flags
& IR3_REG_HALF
);
288 cat2
->opc
= instr
->opc
;
289 cat2
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
290 cat2
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
296 static int emit_cat3(struct ir3_instruction
*instr
, void *ptr
,
297 struct ir3_info
*info
)
299 struct ir3_register
*dst
= instr
->regs
[0];
300 struct ir3_register
*src1
= instr
->regs
[1];
301 struct ir3_register
*src2
= instr
->regs
[2];
302 struct ir3_register
*src3
= instr
->regs
[3];
303 unsigned absneg
= ir3_cat3_absneg(instr
->opc
);
304 instr_cat3_t
*cat3
= ptr
;
305 uint32_t src_flags
= 0;
307 switch (instr
->opc
) {
315 case OPC_SAD_S32
: // really??
316 src_flags
|= IR3_REG_HALF
;
322 iassert(instr
->regs_count
== 4);
323 iassert(!((src1
->flags
^ src_flags
) & IR3_REG_HALF
));
324 iassert(!((src2
->flags
^ src_flags
) & IR3_REG_HALF
));
325 iassert(!((src3
->flags
^ src_flags
) & IR3_REG_HALF
));
328 iassert(!instr
->repeat
);
329 iassert(instr
->nop
<= 3);
331 cat3
->src1_r
= instr
->nop
& 0x1;
332 cat3
->src2_r
= (instr
->nop
>> 1) & 0x1;
334 cat3
->src1_r
= !!(src1
->flags
& IR3_REG_R
);
335 cat3
->src2_r
= !!(src2
->flags
& IR3_REG_R
);
338 if (src1
->flags
& IR3_REG_RELATIV
) {
339 iassert(src1
->array
.offset
< (1 << 10));
340 cat3
->rel1
.src1
= reg(src1
, info
, instr
->repeat
,
341 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_R
|
342 IR3_REG_HALF
| absneg
);
343 cat3
->rel1
.src1_c
= !!(src1
->flags
& IR3_REG_CONST
);
344 cat3
->rel1
.src1_rel
= 1;
345 } else if (src1
->flags
& IR3_REG_CONST
) {
346 iassert(src1
->num
< (1 << 12));
347 cat3
->c1
.src1
= reg(src1
, info
, instr
->repeat
,
348 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
| absneg
);
351 iassert(src1
->num
< (1 << 11));
352 cat3
->src1
= reg(src1
, info
, instr
->repeat
,
353 IR3_REG_R
| IR3_REG_HALF
| absneg
);
356 cat3
->src1_neg
= !!(src1
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
358 cat3
->src2
= reg(src2
, info
, instr
->repeat
,
359 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
| absneg
);
360 cat3
->src2_c
= !!(src2
->flags
& IR3_REG_CONST
);
361 cat3
->src2_neg
= !!(src2
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
363 if (src3
->flags
& IR3_REG_RELATIV
) {
364 iassert(src3
->array
.offset
< (1 << 10));
365 cat3
->rel2
.src3
= reg(src3
, info
, instr
->repeat
,
366 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_R
|
367 IR3_REG_HALF
| absneg
);
368 cat3
->rel2
.src3_c
= !!(src3
->flags
& IR3_REG_CONST
);
369 cat3
->rel2
.src3_rel
= 1;
370 } else if (src3
->flags
& IR3_REG_CONST
) {
371 iassert(src3
->num
< (1 << 12));
372 cat3
->c2
.src3
= reg(src3
, info
, instr
->repeat
,
373 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
| absneg
);
376 iassert(src3
->num
< (1 << 11));
377 cat3
->src3
= reg(src3
, info
, instr
->repeat
,
378 IR3_REG_R
| IR3_REG_HALF
| absneg
);
381 cat3
->src3_neg
= !!(src3
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
382 cat3
->src3_r
= !!(src3
->flags
& IR3_REG_R
);
384 cat3
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
385 cat3
->repeat
= instr
->repeat
;
386 cat3
->sat
= !!(instr
->flags
& IR3_INSTR_SAT
);
387 cat3
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
388 cat3
->ul
= !!(instr
->flags
& IR3_INSTR_UL
);
389 cat3
->dst_half
= !!((src_flags
^ dst
->flags
) & IR3_REG_HALF
);
390 cat3
->opc
= instr
->opc
;
391 cat3
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
392 cat3
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
398 static int emit_cat4(struct ir3_instruction
*instr
, void *ptr
,
399 struct ir3_info
*info
)
401 struct ir3_register
*dst
= instr
->regs
[0];
402 struct ir3_register
*src
= instr
->regs
[1];
403 instr_cat4_t
*cat4
= ptr
;
405 iassert(instr
->regs_count
== 2);
407 if (src
->flags
& IR3_REG_RELATIV
) {
408 iassert(src
->array
.offset
< (1 << 10));
409 cat4
->rel
.src
= reg(src
, info
, instr
->repeat
,
410 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_FNEG
|
411 IR3_REG_FABS
| IR3_REG_R
| IR3_REG_HALF
);
412 cat4
->rel
.src_c
= !!(src
->flags
& IR3_REG_CONST
);
413 cat4
->rel
.src_rel
= 1;
414 } else if (src
->flags
& IR3_REG_CONST
) {
415 iassert(src
->num
< (1 << 12));
416 cat4
->c
.src
= reg(src
, info
, instr
->repeat
,
417 IR3_REG_CONST
| IR3_REG_FNEG
| IR3_REG_FABS
|
418 IR3_REG_R
| IR3_REG_HALF
);
421 iassert(src
->num
< (1 << 11));
422 cat4
->src
= reg(src
, info
, instr
->repeat
,
423 IR3_REG_IMMED
| IR3_REG_FNEG
| IR3_REG_FABS
|
424 IR3_REG_R
| IR3_REG_HALF
);
427 cat4
->src_im
= !!(src
->flags
& IR3_REG_IMMED
);
428 cat4
->src_neg
= !!(src
->flags
& IR3_REG_FNEG
);
429 cat4
->src_abs
= !!(src
->flags
& IR3_REG_FABS
);
430 cat4
->src_r
= !!(src
->flags
& IR3_REG_R
);
432 cat4
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
433 cat4
->repeat
= instr
->repeat
;
434 cat4
->sat
= !!(instr
->flags
& IR3_INSTR_SAT
);
435 cat4
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
436 cat4
->ul
= !!(instr
->flags
& IR3_INSTR_UL
);
437 cat4
->dst_half
= !!((src
->flags
^ dst
->flags
) & IR3_REG_HALF
);
438 cat4
->full
= ! (src
->flags
& IR3_REG_HALF
);
439 cat4
->opc
= instr
->opc
;
440 cat4
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
441 cat4
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
447 static int emit_cat5(struct ir3_instruction
*instr
, void *ptr
,
448 struct ir3_info
*info
)
450 struct ir3_register
*dst
= instr
->regs
[0];
451 /* To simplify things when there could be zero, one, or two args other
452 * than tex/sampler idx, we use the first src reg in the ir to hold
455 struct ir3_register
*src1
;
456 struct ir3_register
*src2
;
457 instr_cat5_t
*cat5
= ptr
;
459 iassert((instr
->regs_count
== 1) ||
460 (instr
->regs_count
== 2) ||
461 (instr
->regs_count
== 3) ||
462 (instr
->regs_count
== 4));
464 if (instr
->flags
& IR3_INSTR_S2EN
) {
465 src1
= instr
->regs
[2];
466 src2
= instr
->regs_count
> 3 ? instr
->regs
[3] : NULL
;
468 src1
= instr
->regs_count
> 1 ? instr
->regs
[1] : NULL
;
469 src2
= instr
->regs_count
> 2 ? instr
->regs
[2] : NULL
;
472 assume(src1
|| !src2
);
475 cat5
->full
= ! (src1
->flags
& IR3_REG_HALF
);
476 cat5
->src1
= reg(src1
, info
, instr
->repeat
, IR3_REG_HALF
);
480 iassert(!((src1
->flags
^ src2
->flags
) & IR3_REG_HALF
));
481 cat5
->src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_HALF
);
484 if (instr
->flags
& IR3_INSTR_B
) {
485 cat5
->s2en_bindless
.base_hi
= instr
->cat5
.tex_base
>> 1;
486 cat5
->base_lo
= instr
->cat5
.tex_base
& 1;
489 if (instr
->flags
& IR3_INSTR_S2EN
) {
490 struct ir3_register
*samp_tex
= instr
->regs
[1];
491 iassert(samp_tex
->flags
& IR3_REG_HALF
);
492 cat5
->s2en_bindless
.src3
= reg(samp_tex
, info
, instr
->repeat
,
493 (instr
->flags
& IR3_INSTR_B
) ? 0 : IR3_REG_HALF
);
494 if (instr
->flags
& IR3_INSTR_B
) {
495 if (instr
->flags
& IR3_INSTR_A1EN
) {
496 cat5
->s2en_bindless
.desc_mode
= CAT5_BINDLESS_A1_UNIFORM
;
498 cat5
->s2en_bindless
.desc_mode
= CAT5_BINDLESS_UNIFORM
;
501 /* TODO: This should probably be CAT5_UNIFORM, at least on a6xx,
502 * as this is what the blob does and it is presumably faster, but
503 * first we should confirm it is actually nonuniform and figure
504 * out when the whole descriptor mode mechanism was introduced.
506 cat5
->s2en_bindless
.desc_mode
= CAT5_NONUNIFORM
;
508 iassert(!(instr
->cat5
.samp
| instr
->cat5
.tex
));
509 } else if (instr
->flags
& IR3_INSTR_B
) {
510 cat5
->s2en_bindless
.src3
= instr
->cat5
.samp
;
511 if (instr
->flags
& IR3_INSTR_A1EN
) {
512 cat5
->s2en_bindless
.desc_mode
= CAT5_BINDLESS_A1_IMM
;
514 cat5
->s2en_bindless
.desc_mode
= CAT5_BINDLESS_IMM
;
517 cat5
->norm
.samp
= instr
->cat5
.samp
;
518 cat5
->norm
.tex
= instr
->cat5
.tex
;
521 cat5
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
522 cat5
->wrmask
= dst
->wrmask
;
523 cat5
->type
= instr
->cat5
.type
;
524 cat5
->is_3d
= !!(instr
->flags
& IR3_INSTR_3D
);
525 cat5
->is_a
= !!(instr
->flags
& IR3_INSTR_A
);
526 cat5
->is_s
= !!(instr
->flags
& IR3_INSTR_S
);
527 cat5
->is_s2en_bindless
= !!(instr
->flags
& (IR3_INSTR_S2EN
| IR3_INSTR_B
));
528 cat5
->is_o
= !!(instr
->flags
& IR3_INSTR_O
);
529 cat5
->is_p
= !!(instr
->flags
& IR3_INSTR_P
);
530 cat5
->opc
= instr
->opc
;
531 cat5
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
532 cat5
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
538 static int emit_cat6_a6xx(struct ir3_instruction
*instr
, void *ptr
,
539 struct ir3_info
*info
)
541 struct ir3_register
*ssbo
;
542 instr_cat6_a6xx_t
*cat6
= ptr
;
544 ssbo
= instr
->regs
[1];
546 cat6
->type
= instr
->cat6
.type
;
547 cat6
->d
= instr
->cat6
.d
- (instr
->opc
== OPC_LDC
? 0 : 1);
548 cat6
->typed
= instr
->cat6
.typed
;
549 cat6
->type_size
= instr
->cat6
.iim_val
- 1;
550 cat6
->opc
= instr
->opc
;
551 cat6
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
552 cat6
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
555 cat6
->ssbo
= reg(ssbo
, info
, instr
->repeat
, IR3_REG_IMMED
);
557 /* For unused sources in an opcode, initialize contents with the ir3 dest
560 switch (instr
->opc
) {
562 cat6
->src1
= reg(instr
->regs
[0], info
, instr
->repeat
, 0);
563 cat6
->src2
= reg(instr
->regs
[0], info
, instr
->repeat
, 0);
567 cat6
->src1
= reg(instr
->regs
[2], info
, instr
->repeat
, 0);
568 cat6
->src2
= reg(instr
->regs
[0], info
, instr
->repeat
, 0);
571 cat6
->src1
= reg(instr
->regs
[2], info
, instr
->repeat
, 0);
572 cat6
->src2
= reg(instr
->regs
[3], info
, instr
->repeat
, 0);
576 if (instr
->flags
& IR3_INSTR_B
) {
577 if (ssbo
->flags
& IR3_REG_IMMED
) {
578 cat6
->desc_mode
= CAT6_BINDLESS_IMM
;
580 cat6
->desc_mode
= CAT6_BINDLESS_UNIFORM
;
582 cat6
->base
= instr
->cat6
.base
;
584 if (ssbo
->flags
& IR3_REG_IMMED
)
585 cat6
->desc_mode
= CAT6_IMM
;
587 cat6
->desc_mode
= CAT6_UNIFORM
;
590 switch (instr
->opc
) {
593 case OPC_ATOMIC_XCHG
:
596 case OPC_ATOMIC_CMPXCHG
:
631 static int emit_cat6(struct ir3_instruction
*instr
, void *ptr
,
632 struct ir3_info
*info
)
634 struct ir3_shader_variant
*v
= info
->data
;
635 struct ir3_register
*dst
, *src1
, *src2
;
636 instr_cat6_t
*cat6
= ptr
;
638 /* In a6xx we start using a new instruction encoding for some of
639 * these instructions:
641 if (v
->shader
->compiler
->gpu_id
>= 600) {
642 switch (instr
->opc
) {
645 case OPC_ATOMIC_XCHG
:
648 case OPC_ATOMIC_CMPXCHG
:
654 /* The shared variants of these still use the old encoding: */
655 if (!(instr
->flags
& IR3_INSTR_G
))
662 return emit_cat6_a6xx(instr
, ptr
, info
);
668 bool type_full
= type_size(instr
->cat6
.type
) == 32;
670 cat6
->type
= instr
->cat6
.type
;
671 cat6
->opc
= instr
->opc
;
672 cat6
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
673 cat6
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
674 cat6
->g
= !!(instr
->flags
& IR3_INSTR_G
);
677 switch (instr
->opc
) {
680 iassert_type(instr
->regs
[0], type_full
); /* dst */
681 iassert_type(instr
->regs
[1], type_full
); /* src1 */
685 iassert_type(instr
->regs
[0], true); /* dst */
686 iassert_type(instr
->regs
[1], true); /* src1 */
693 /* no dst, so regs[0] is dummy */
694 iassert_type(instr
->regs
[1], true); /* dst */
695 iassert_type(instr
->regs
[2], type_full
); /* src1 */
696 iassert_type(instr
->regs
[3], true); /* src2 */
699 iassert_type(instr
->regs
[0], type_full
); /* dst */
700 iassert_type(instr
->regs
[1], true); /* src1 */
701 if (instr
->regs_count
> 2)
702 iassert_type(instr
->regs
[2], true); /* src1 */
706 /* the "dst" for a store instruction is (from the perspective
707 * of data flow in the shader, ie. register use/def, etc) in
708 * fact a register that is read by the instruction, rather
711 if (is_store(instr
)) {
712 iassert(instr
->regs_count
>= 3);
714 dst
= instr
->regs
[1];
715 src1
= instr
->regs
[2];
716 src2
= (instr
->regs_count
>= 4) ? instr
->regs
[3] : NULL
;
718 iassert(instr
->regs_count
>= 2);
720 dst
= instr
->regs
[0];
721 src1
= instr
->regs
[1];
722 src2
= (instr
->regs_count
>= 3) ? instr
->regs
[2] : NULL
;
725 /* TODO we need a more comprehensive list about which instructions
726 * can be encoded which way. Or possibly use IR3_INSTR_0 flag to
727 * indicate to use the src_off encoding even if offset is zero
728 * (but then what to do about dst_off?)
730 if (is_atomic(instr
->opc
)) {
731 instr_cat6ldgb_t
*ldgb
= ptr
;
733 /* maybe these two bits both determine the instruction encoding? */
734 cat6
->src_off
= false;
736 ldgb
->d
= instr
->cat6
.d
- 1;
737 ldgb
->typed
= instr
->cat6
.typed
;
738 ldgb
->type_size
= instr
->cat6
.iim_val
- 1;
740 ldgb
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
743 struct ir3_register
*src3
= instr
->regs
[3];
744 struct ir3_register
*src4
= instr
->regs
[4];
746 /* first src is src_ssbo: */
747 iassert(src1
->flags
& IR3_REG_IMMED
);
748 ldgb
->src_ssbo
= src1
->uim_val
;
749 ldgb
->src_ssbo_im
= 0x1;
751 ldgb
->src1
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
752 ldgb
->src1_im
= !!(src2
->flags
& IR3_REG_IMMED
);
753 ldgb
->src2
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
754 ldgb
->src2_im
= !!(src3
->flags
& IR3_REG_IMMED
);
756 ldgb
->src3
= reg(src4
, info
, instr
->repeat
, 0);
759 ldgb
->src1
= reg(src1
, info
, instr
->repeat
, IR3_REG_IMMED
);
760 ldgb
->src1_im
= !!(src1
->flags
& IR3_REG_IMMED
);
761 ldgb
->src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
762 ldgb
->src2_im
= !!(src2
->flags
& IR3_REG_IMMED
);
764 ldgb
->src_ssbo_im
= 0x0;
768 } else if (instr
->opc
== OPC_LDGB
) {
769 struct ir3_register
*src3
= instr
->regs
[3];
770 instr_cat6ldgb_t
*ldgb
= ptr
;
772 /* maybe these two bits both determine the instruction encoding? */
773 cat6
->src_off
= false;
775 ldgb
->d
= instr
->cat6
.d
- 1;
776 ldgb
->typed
= instr
->cat6
.typed
;
777 ldgb
->type_size
= instr
->cat6
.iim_val
- 1;
779 ldgb
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
781 /* first src is src_ssbo: */
782 iassert(src1
->flags
& IR3_REG_IMMED
);
783 ldgb
->src_ssbo
= src1
->uim_val
;
785 /* then next two are src1/src2: */
786 ldgb
->src1
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
787 ldgb
->src1_im
= !!(src2
->flags
& IR3_REG_IMMED
);
788 ldgb
->src2
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
789 ldgb
->src2_im
= !!(src3
->flags
& IR3_REG_IMMED
);
792 ldgb
->src_ssbo_im
= true;
795 } else if (instr
->opc
== OPC_RESINFO
) {
796 instr_cat6ldgb_t
*ldgb
= ptr
;
798 ldgb
->d
= instr
->cat6
.d
- 1;
800 ldgb
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
802 /* first src is src_ssbo: */
803 ldgb
->src_ssbo
= reg(src1
, info
, instr
->repeat
, IR3_REG_IMMED
);
804 ldgb
->src_ssbo_im
= !!(src1
->flags
& IR3_REG_IMMED
);
807 } else if ((instr
->opc
== OPC_STGB
) || (instr
->opc
== OPC_STIB
)) {
808 struct ir3_register
*src3
= instr
->regs
[4];
809 instr_cat6stgb_t
*stgb
= ptr
;
811 /* maybe these two bits both determine the instruction encoding? */
812 cat6
->src_off
= true;
815 stgb
->d
= instr
->cat6
.d
- 1;
816 stgb
->typed
= instr
->cat6
.typed
;
817 stgb
->type_size
= instr
->cat6
.iim_val
- 1;
819 /* first src is dst_ssbo: */
820 iassert(dst
->flags
& IR3_REG_IMMED
);
821 stgb
->dst_ssbo
= dst
->uim_val
;
823 /* then src1/src2/src3: */
824 stgb
->src1
= reg(src1
, info
, instr
->repeat
, 0);
825 stgb
->src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
826 stgb
->src2_im
= !!(src2
->flags
& IR3_REG_IMMED
);
827 stgb
->src3
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
828 stgb
->src3_im
= !!(src3
->flags
& IR3_REG_IMMED
);
831 } else if (instr
->cat6
.src_offset
|| (instr
->opc
== OPC_LDG
) ||
832 (instr
->opc
== OPC_LDL
) || (instr
->opc
== OPC_LDLW
)) {
833 struct ir3_register
*src3
= instr
->regs
[3];
834 instr_cat6a_t
*cat6a
= ptr
;
836 cat6
->src_off
= true;
838 if (instr
->opc
== OPC_LDG
) {
839 /* For LDG src1 can not be immediate, so src1_imm is redundant and
840 * instead used to signal whether (when true) 'off' is a 32 bit
841 * register or an immediate offset.
843 cat6a
->src1
= reg(src1
, info
, instr
->repeat
, 0);
844 cat6a
->src1_im
= !(src3
->flags
& IR3_REG_IMMED
);
845 cat6a
->off
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
847 cat6a
->src1
= reg(src1
, info
, instr
->repeat
, IR3_REG_IMMED
);
848 cat6a
->src1_im
= !!(src1
->flags
& IR3_REG_IMMED
);
849 cat6a
->off
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
850 iassert(src3
->flags
& IR3_REG_IMMED
);
854 cat6a
->src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
855 cat6a
->src2_im
= true;
857 instr_cat6b_t
*cat6b
= ptr
;
859 cat6
->src_off
= false;
861 cat6b
->src1
= reg(src1
, info
, instr
->repeat
, IR3_REG_IMMED
| IR3_REG_HALF
);
862 cat6b
->src1_im
= !!(src1
->flags
& IR3_REG_IMMED
);
864 cat6b
->src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
865 cat6b
->src2_im
= !!(src2
->flags
& IR3_REG_IMMED
);
869 if (instr
->cat6
.dst_offset
|| (instr
->opc
== OPC_STG
) ||
870 (instr
->opc
== OPC_STL
) || (instr
->opc
== OPC_STLW
)) {
871 instr_cat6c_t
*cat6c
= ptr
;
872 cat6
->dst_off
= true;
873 cat6c
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
875 if (instr
->flags
& IR3_INSTR_G
) {
876 struct ir3_register
*src3
= instr
->regs
[4];
877 cat6c
->off
= reg(src3
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
878 if (src3
->flags
& IR3_REG_IMMED
) {
879 /* Immediate offsets are in bytes... */
884 cat6c
->off
= instr
->cat6
.dst_offset
;
887 instr_cat6d_t
*cat6d
= ptr
;
888 cat6
->dst_off
= false;
889 cat6d
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
895 static int emit_cat7(struct ir3_instruction
*instr
, void *ptr
,
896 struct ir3_info
*info
)
898 instr_cat7_t
*cat7
= ptr
;
900 cat7
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
901 cat7
->w
= instr
->cat7
.w
;
902 cat7
->r
= instr
->cat7
.r
;
903 cat7
->l
= instr
->cat7
.l
;
904 cat7
->g
= instr
->cat7
.g
;
905 cat7
->opc
= instr
->opc
;
906 cat7
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
907 cat7
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
913 static int (*emit
[])(struct ir3_instruction
*instr
, void *ptr
,
914 struct ir3_info
*info
) = {
915 emit_cat0
, emit_cat1
, emit_cat2
, emit_cat3
, emit_cat4
, emit_cat5
, emit_cat6
,
919 void * ir3_assemble(struct ir3_shader_variant
*v
)
921 uint32_t *ptr
, *dwords
;
922 struct ir3_info
*info
= &v
->info
;
923 struct ir3
*shader
= v
->ir
;
925 memset(info
, 0, sizeof(*info
));
928 info
->max_half_reg
= -1;
929 info
->max_const
= -1;
931 foreach_block (block
, &shader
->block_list
) {
932 foreach_instr (instr
, &block
->instr_list
) {
933 info
->sizedwords
+= 2;
937 /* need an integer number of instruction "groups" (sets of 16
938 * instructions on a4xx or sets of 4 instructions on a3xx),
939 * so pad out w/ NOPs if needed: (NOTE each instruction is 64bits)
941 if (v
->shader
->compiler
->gpu_id
>= 400) {
942 info
->sizedwords
= align(info
->sizedwords
, 16 * 2);
944 info
->sizedwords
= align(info
->sizedwords
, 4 * 2);
947 ptr
= dwords
= rzalloc_size(v
, 4 * info
->sizedwords
);
949 foreach_block (block
, &shader
->block_list
) {
950 unsigned sfu_delay
= 0;
952 foreach_instr (instr
, &block
->instr_list
) {
953 int ret
= emit
[opc_cat(instr
->opc
)](instr
, dwords
, info
);
957 if ((instr
->opc
== OPC_BARY_F
) && (instr
->regs
[0]->flags
& IR3_REG_EI
))
958 info
->last_baryf
= info
->instrs_count
;
960 info
->instrs_count
+= 1 + instr
->repeat
+ instr
->nop
;
961 info
->nops_count
+= instr
->nop
;
962 if (instr
->opc
== OPC_NOP
)
963 info
->nops_count
+= 1 + instr
->repeat
;
964 if (instr
->opc
== OPC_MOV
) {
965 if (instr
->cat1
.src_type
== instr
->cat1
.dst_type
) {
966 info
->mov_count
+= 1 + instr
->repeat
;
968 info
->cov_count
+= 1 + instr
->repeat
;
973 if (instr
->flags
& IR3_INSTR_SS
) {
975 info
->sstall
+= sfu_delay
;
978 if (instr
->flags
& IR3_INSTR_SY
)
983 } else if (sfu_delay
> 0) {
996 static struct ir3_register
* reg_create(struct ir3
*shader
,
999 struct ir3_register
*reg
=
1000 ir3_alloc(shader
, sizeof(struct ir3_register
));
1007 static void insert_instr(struct ir3_block
*block
,
1008 struct ir3_instruction
*instr
)
1010 struct ir3
*shader
= block
->shader
;
1012 instr
->serialno
= ++shader
->instr_count
;
1014 list_addtail(&instr
->node
, &block
->instr_list
);
1016 if (is_input(instr
))
1017 array_insert(shader
, shader
->baryfs
, instr
);
1020 struct ir3_block
* ir3_block_create(struct ir3
*shader
)
1022 struct ir3_block
*block
= ir3_alloc(shader
, sizeof(*block
));
1024 block
->serialno
= ++shader
->block_count
;
1026 block
->shader
= shader
;
1027 list_inithead(&block
->node
);
1028 list_inithead(&block
->instr_list
);
1029 block
->predecessors
= _mesa_pointer_set_create(block
);
1033 static struct ir3_instruction
*instr_create(struct ir3_block
*block
, int nreg
)
1035 struct ir3_instruction
*instr
;
1036 unsigned sz
= sizeof(*instr
) + (nreg
* sizeof(instr
->regs
[0]));
1037 char *ptr
= ir3_alloc(block
->shader
, sz
);
1039 instr
= (struct ir3_instruction
*)ptr
;
1040 ptr
+= sizeof(*instr
);
1041 instr
->regs
= (struct ir3_register
**)ptr
;
1044 instr
->regs_max
= nreg
;
1050 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
1051 opc_t opc
, int nreg
)
1053 struct ir3_instruction
*instr
= instr_create(block
, nreg
);
1054 instr
->block
= block
;
1056 insert_instr(block
, instr
);
1060 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
)
1062 /* NOTE: we could be slightly more clever, at least for non-meta,
1063 * and choose # of regs based on category.
1065 return ir3_instr_create2(block
, opc
, 4);
1068 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
)
1070 struct ir3_instruction
*new_instr
= instr_create(instr
->block
,
1072 struct ir3_register
**regs
;
1075 regs
= new_instr
->regs
;
1076 *new_instr
= *instr
;
1077 new_instr
->regs
= regs
;
1079 insert_instr(instr
->block
, new_instr
);
1081 /* clone registers: */
1082 new_instr
->regs_count
= 0;
1083 for (i
= 0; i
< instr
->regs_count
; i
++) {
1084 struct ir3_register
*reg
= instr
->regs
[i
];
1085 struct ir3_register
*new_reg
=
1086 ir3_reg_create(new_instr
, reg
->num
, reg
->flags
);
1093 /* Add a false dependency to instruction, to ensure it is scheduled first: */
1094 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
)
1096 array_insert(instr
, instr
->deps
, dep
);
1099 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
1102 struct ir3
*shader
= instr
->block
->shader
;
1103 struct ir3_register
*reg
= reg_create(shader
, num
, flags
);
1105 debug_assert(instr
->regs_count
< instr
->regs_max
);
1107 instr
->regs
[instr
->regs_count
++] = reg
;
1111 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
1112 struct ir3_register
*reg
)
1114 struct ir3_register
*new_reg
= reg_create(shader
, 0, 0);
1120 ir3_instr_set_address(struct ir3_instruction
*instr
,
1121 struct ir3_instruction
*addr
)
1123 if (instr
->address
!= addr
) {
1124 struct ir3
*ir
= instr
->block
->shader
;
1126 debug_assert(!instr
->address
);
1127 debug_assert(instr
->block
== addr
->block
);
1129 instr
->address
= addr
;
1130 debug_assert(reg_num(addr
->regs
[0]) == REG_A0
);
1131 unsigned comp
= reg_comp(addr
->regs
[0]);
1133 array_insert(ir
, ir
->a0_users
, instr
);
1135 debug_assert(comp
== 1);
1136 array_insert(ir
, ir
->a1_users
, instr
);
1142 ir3_block_clear_mark(struct ir3_block
*block
)
1144 foreach_instr (instr
, &block
->instr_list
)
1145 instr
->flags
&= ~IR3_INSTR_MARK
;
1149 ir3_clear_mark(struct ir3
*ir
)
1151 foreach_block (block
, &ir
->block_list
) {
1152 ir3_block_clear_mark(block
);
1157 ir3_count_instructions(struct ir3
*ir
)
1160 foreach_block (block
, &ir
->block_list
) {
1161 block
->start_ip
= cnt
;
1162 foreach_instr (instr
, &block
->instr_list
) {
1165 block
->end_ip
= cnt
;
1170 /* When counting instructions for RA, we insert extra fake instructions at the
1171 * beginning of each block, where values become live, and at the end where
1172 * values die. This prevents problems where values live-in at the beginning or
1173 * live-out at the end of a block from being treated as if they were
1174 * live-in/live-out at the first/last instruction, which would be incorrect.
1175 * In ir3_legalize these ip's are assumed to be actual ip's of the final
1176 * program, so it would be incorrect to use this everywhere.
1180 ir3_count_instructions_ra(struct ir3
*ir
)
1183 foreach_block (block
, &ir
->block_list
) {
1184 block
->start_ip
= cnt
++;
1185 foreach_instr (instr
, &block
->instr_list
) {
1188 block
->end_ip
= cnt
++;
1194 ir3_lookup_array(struct ir3
*ir
, unsigned id
)
1196 foreach_array (arr
, &ir
->array_list
)
1203 ir3_find_ssa_uses(struct ir3
*ir
, void *mem_ctx
, bool falsedeps
)
1205 /* We could do this in a single pass if we can assume instructions
1206 * are always sorted. Which currently might not always be true.
1207 * (In particular after ir3_group pass, but maybe other places.)
1209 foreach_block (block
, &ir
->block_list
)
1210 foreach_instr (instr
, &block
->instr_list
)
1213 foreach_block (block
, &ir
->block_list
) {
1214 foreach_instr (instr
, &block
->instr_list
) {
1215 foreach_ssa_src_n (src
, n
, instr
) {
1216 if (__is_false_dep(instr
, n
) && !falsedeps
)
1219 src
->uses
= _mesa_pointer_set_create(mem_ctx
);
1220 _mesa_set_add(src
->uses
, instr
);
1227 * Set the destination type of an instruction, for example if a
1228 * conversion is folded in, handling the special cases where the
1229 * instruction's dest type or opcode needs to be fixed up.
1232 ir3_set_dst_type(struct ir3_instruction
*instr
, bool half
)
1235 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
1237 instr
->regs
[0]->flags
&= ~IR3_REG_HALF
;
1240 switch (opc_cat(instr
->opc
)) {
1241 case 1: /* move instructions */
1243 instr
->cat1
.dst_type
= half_type(instr
->cat1
.dst_type
);
1245 instr
->cat1
.dst_type
= full_type(instr
->cat1
.dst_type
);
1250 instr
->opc
= cat4_half_opc(instr
->opc
);
1252 instr
->opc
= cat4_full_opc(instr
->opc
);
1257 instr
->cat5
.type
= half_type(instr
->cat5
.type
);
1259 instr
->cat5
.type
= full_type(instr
->cat5
.type
);
1266 * One-time fixup for instruction src-types. Other than cov's that
1267 * are folded, an instruction's src type does not change.
1270 ir3_fixup_src_type(struct ir3_instruction
*instr
)
1272 bool half
= !!(instr
->regs
[1]->flags
& IR3_REG_HALF
);
1274 switch (opc_cat(instr
->opc
)) {
1275 case 1: /* move instructions */
1277 instr
->cat1
.src_type
= half_type(instr
->cat1
.src_type
);
1279 instr
->cat1
.src_type
= full_type(instr
->cat1
.src_type
);
1284 instr
->opc
= cat3_half_opc(instr
->opc
);
1286 instr
->opc
= cat3_full_opc(instr
->opc
);
1293 cp_flags(unsigned flags
)
1295 /* only considering these flags (at least for now): */
1296 flags
&= (IR3_REG_CONST
| IR3_REG_IMMED
|
1297 IR3_REG_FNEG
| IR3_REG_FABS
|
1298 IR3_REG_SNEG
| IR3_REG_SABS
|
1299 IR3_REG_BNOT
| IR3_REG_RELATIV
);
1304 ir3_valid_flags(struct ir3_instruction
*instr
, unsigned n
,
1307 struct ir3_compiler
*compiler
= instr
->block
->shader
->compiler
;
1308 unsigned valid_flags
;
1310 if ((flags
& IR3_REG_HIGH
) &&
1311 (opc_cat(instr
->opc
) > 1) &&
1312 (compiler
->gpu_id
>= 600))
1315 flags
= cp_flags(flags
);
1317 /* If destination is indirect, then source cannot be.. at least
1318 * I don't think so..
1320 if ((instr
->regs
[0]->flags
& IR3_REG_RELATIV
) &&
1321 (flags
& IR3_REG_RELATIV
))
1324 if (flags
& IR3_REG_RELATIV
) {
1325 /* TODO need to test on earlier gens.. pretty sure the earlier
1326 * problem was just that we didn't check that the src was from
1327 * same block (since we can't propagate address register values
1328 * across blocks currently)
1330 if (compiler
->gpu_id
< 600)
1333 /* NOTE in the special try_swap_mad_two_srcs() case we can be
1334 * called on a src that has already had an indirect load folded
1335 * in, in which case ssa() returns NULL
1337 if (instr
->regs
[n
+1]->flags
& IR3_REG_SSA
) {
1338 struct ir3_instruction
*src
= ssa(instr
->regs
[n
+1]);
1339 if (src
->address
->block
!= instr
->block
)
1344 switch (opc_cat(instr
->opc
)) {
1346 valid_flags
= IR3_REG_IMMED
| IR3_REG_CONST
| IR3_REG_RELATIV
;
1347 if (flags
& ~valid_flags
)
1351 valid_flags
= ir3_cat2_absneg(instr
->opc
) |
1352 IR3_REG_CONST
| IR3_REG_RELATIV
;
1354 if (ir3_cat2_int(instr
->opc
))
1355 valid_flags
|= IR3_REG_IMMED
;
1357 if (flags
& ~valid_flags
)
1360 if (flags
& (IR3_REG_CONST
| IR3_REG_IMMED
)) {
1361 unsigned m
= (n
^ 1) + 1;
1362 /* cannot deal w/ const in both srcs:
1363 * (note that some cat2 actually only have a single src)
1365 if (m
< instr
->regs_count
) {
1366 struct ir3_register
*reg
= instr
->regs
[m
];
1367 if ((flags
& IR3_REG_CONST
) && (reg
->flags
& IR3_REG_CONST
))
1369 if ((flags
& IR3_REG_IMMED
) && (reg
->flags
& IR3_REG_IMMED
))
1375 valid_flags
= ir3_cat3_absneg(instr
->opc
) |
1376 IR3_REG_CONST
| IR3_REG_RELATIV
;
1378 if (flags
& ~valid_flags
)
1381 if (flags
& (IR3_REG_CONST
| IR3_REG_RELATIV
)) {
1382 /* cannot deal w/ const/relativ in 2nd src: */
1389 /* seems like blob compiler avoids const as src.. */
1390 /* TODO double check if this is still the case on a4xx */
1391 if (flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
1393 if (flags
& (IR3_REG_SABS
| IR3_REG_SNEG
))
1397 /* no flags allowed */
1402 valid_flags
= IR3_REG_IMMED
;
1403 if (flags
& ~valid_flags
)
1406 if (flags
& IR3_REG_IMMED
) {
1407 /* doesn't seem like we can have immediate src for store
1410 * TODO this restriction could also apply to load instructions,
1411 * but for load instructions this arg is the address (and not
1412 * really sure any good way to test a hard-coded immed addr src)
1414 if (is_store(instr
) && (n
== 1))
1417 if ((instr
->opc
== OPC_LDL
) && (n
== 0))
1420 if ((instr
->opc
== OPC_STL
) && (n
!= 2))
1423 if (instr
->opc
== OPC_STLW
&& n
== 0)
1426 if (instr
->opc
== OPC_LDLW
&& n
== 0)
1429 /* disallow immediates in anything but the SSBO slot argument for
1430 * cat6 instructions:
1432 if (is_atomic(instr
->opc
) && (n
!= 0))
1435 if (is_atomic(instr
->opc
) && !(instr
->flags
& IR3_INSTR_G
))
1438 if (instr
->opc
== OPC_STG
&& (instr
->flags
& IR3_INSTR_G
) && (n
!= 2))
1441 /* as with atomics, these cat6 instrs can only have an immediate
1442 * for SSBO/IBO slot argument
1444 switch (instr
->opc
) {