b137ee1a695a2a7cf90e3ba6f2a207cda8f55f9b
2 * Copyright (c) 2012 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include "util/bitscan.h"
34 #include "util/ralloc.h"
35 #include "util/u_math.h"
37 #include "instr-a3xx.h"
38 #include "ir3_compiler.h"
40 /* simple allocator to carve allocations out of an up-front allocated heap,
41 * so that we can free everything easily in one shot.
43 void * ir3_alloc(struct ir3
*shader
, int sz
)
45 return rzalloc_size(shader
, sz
); /* TODO: don't use rzalloc */
48 struct ir3
* ir3_create(struct ir3_compiler
*compiler
,
49 gl_shader_stage type
, unsigned nin
, unsigned nout
)
51 struct ir3
*shader
= rzalloc(NULL
, struct ir3
);
53 shader
->compiler
= compiler
;
55 shader
->ninputs
= nin
;
56 shader
->inputs
= ir3_alloc(shader
, sizeof(shader
->inputs
[0]) * nin
);
58 shader
->noutputs
= nout
;
59 shader
->outputs
= ir3_alloc(shader
, sizeof(shader
->outputs
[0]) * nout
);
61 list_inithead(&shader
->block_list
);
62 list_inithead(&shader
->array_list
);
67 void ir3_destroy(struct ir3
*shader
)
72 #define iassert(cond) do { \
78 #define iassert_type(reg, full) do { \
80 iassert(!((reg)->flags & IR3_REG_HALF)); \
82 iassert((reg)->flags & IR3_REG_HALF); \
85 static uint32_t reg(struct ir3_register
*reg
, struct ir3_info
*info
,
86 uint32_t repeat
, uint32_t valid_flags
)
88 reg_t val
= { .dummy32
= 0 };
90 if (reg
->flags
& ~valid_flags
) {
91 debug_printf("INVALID FLAGS: %x vs %x\n",
92 reg
->flags
, valid_flags
);
95 if (!(reg
->flags
& IR3_REG_R
))
98 if (reg
->flags
& IR3_REG_IMMED
) {
99 val
.iim_val
= reg
->iim_val
;
104 if (reg
->flags
& IR3_REG_RELATIV
) {
105 components
= reg
->size
;
106 val
.idummy10
= reg
->array
.offset
;
107 max
= (reg
->array
.offset
+ repeat
+ components
- 1);
109 components
= util_last_bit(reg
->wrmask
);
110 val
.comp
= reg
->num
& 0x3;
111 val
.num
= reg
->num
>> 2;
112 max
= (reg
->num
+ repeat
+ components
- 1);
115 if (reg
->flags
& IR3_REG_CONST
) {
116 info
->max_const
= MAX2(info
->max_const
, max
>> 2);
117 } else if (val
.num
== 63) {
118 /* ignore writes to dummy register r63.x */
119 } else if (max
< regid(48, 0)) {
120 if (reg
->flags
& IR3_REG_HALF
) {
121 if (info
->gpu_id
>= 600) {
122 /* starting w/ a6xx, half regs conflict with full regs: */
123 info
->max_reg
= MAX2(info
->max_reg
, max
>> 3);
125 info
->max_half_reg
= MAX2(info
->max_half_reg
, max
>> 2);
128 info
->max_reg
= MAX2(info
->max_reg
, max
>> 2);
136 static int emit_cat0(struct ir3_instruction
*instr
, void *ptr
,
137 struct ir3_info
*info
)
139 instr_cat0_t
*cat0
= ptr
;
141 if (info
->gpu_id
>= 500) {
142 cat0
->a5xx
.immed
= instr
->cat0
.immed
;
143 } else if (info
->gpu_id
>= 400) {
144 cat0
->a4xx
.immed
= instr
->cat0
.immed
;
146 cat0
->a3xx
.immed
= instr
->cat0
.immed
;
148 cat0
->repeat
= instr
->repeat
;
149 cat0
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
150 cat0
->inv
= instr
->cat0
.inv
;
151 cat0
->comp
= instr
->cat0
.comp
;
152 cat0
->opc
= instr
->opc
;
153 cat0
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
154 cat0
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
160 static int emit_cat1(struct ir3_instruction
*instr
, void *ptr
,
161 struct ir3_info
*info
)
163 struct ir3_register
*dst
= instr
->regs
[0];
164 struct ir3_register
*src
= instr
->regs
[1];
165 instr_cat1_t
*cat1
= ptr
;
167 iassert(instr
->regs_count
== 2);
168 iassert_type(dst
, type_size(instr
->cat1
.dst_type
) == 32);
169 if (!(src
->flags
& IR3_REG_IMMED
))
170 iassert_type(src
, type_size(instr
->cat1
.src_type
) == 32);
172 if (src
->flags
& IR3_REG_IMMED
) {
173 cat1
->iim_val
= src
->iim_val
;
175 } else if (src
->flags
& IR3_REG_RELATIV
) {
176 cat1
->off
= reg(src
, info
, instr
->repeat
,
177 IR3_REG_R
| IR3_REG_CONST
| IR3_REG_HALF
| IR3_REG_RELATIV
);
179 cat1
->src_rel_c
= !!(src
->flags
& IR3_REG_CONST
);
181 cat1
->src
= reg(src
, info
, instr
->repeat
,
182 IR3_REG_R
| IR3_REG_CONST
| IR3_REG_HALF
);
183 cat1
->src_c
= !!(src
->flags
& IR3_REG_CONST
);
186 cat1
->dst
= reg(dst
, info
, instr
->repeat
,
187 IR3_REG_RELATIV
| IR3_REG_EVEN
|
188 IR3_REG_R
| IR3_REG_POS_INF
| IR3_REG_HALF
);
189 cat1
->repeat
= instr
->repeat
;
190 cat1
->src_r
= !!(src
->flags
& IR3_REG_R
);
191 cat1
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
192 cat1
->ul
= !!(instr
->flags
& IR3_INSTR_UL
);
193 cat1
->dst_type
= instr
->cat1
.dst_type
;
194 cat1
->dst_rel
= !!(dst
->flags
& IR3_REG_RELATIV
);
195 cat1
->src_type
= instr
->cat1
.src_type
;
196 cat1
->even
= !!(dst
->flags
& IR3_REG_EVEN
);
197 cat1
->pos_inf
= !!(dst
->flags
& IR3_REG_POS_INF
);
198 cat1
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
199 cat1
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
205 static int emit_cat2(struct ir3_instruction
*instr
, void *ptr
,
206 struct ir3_info
*info
)
208 struct ir3_register
*dst
= instr
->regs
[0];
209 struct ir3_register
*src1
= instr
->regs
[1];
210 struct ir3_register
*src2
= instr
->regs
[2];
211 instr_cat2_t
*cat2
= ptr
;
212 unsigned absneg
= ir3_cat2_absneg(instr
->opc
);
214 iassert((instr
->regs_count
== 2) || (instr
->regs_count
== 3));
217 iassert(!instr
->repeat
);
218 iassert(instr
->nop
<= 3);
220 cat2
->src1_r
= instr
->nop
& 0x1;
221 cat2
->src2_r
= (instr
->nop
>> 1) & 0x1;
223 cat2
->src1_r
= !!(src1
->flags
& IR3_REG_R
);
225 cat2
->src2_r
= !!(src2
->flags
& IR3_REG_R
);
228 if (src1
->flags
& IR3_REG_RELATIV
) {
229 iassert(src1
->array
.offset
< (1 << 10));
230 cat2
->rel1
.src1
= reg(src1
, info
, instr
->repeat
,
231 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_R
|
232 IR3_REG_HALF
| absneg
);
233 cat2
->rel1
.src1_c
= !!(src1
->flags
& IR3_REG_CONST
);
234 cat2
->rel1
.src1_rel
= 1;
235 } else if (src1
->flags
& IR3_REG_CONST
) {
236 iassert(src1
->num
< (1 << 12));
237 cat2
->c1
.src1
= reg(src1
, info
, instr
->repeat
,
238 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
|
242 iassert(src1
->num
< (1 << 11));
243 cat2
->src1
= reg(src1
, info
, instr
->repeat
,
244 IR3_REG_IMMED
| IR3_REG_R
| IR3_REG_HALF
|
247 cat2
->src1_im
= !!(src1
->flags
& IR3_REG_IMMED
);
248 cat2
->src1_neg
= !!(src1
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
249 cat2
->src1_abs
= !!(src1
->flags
& (IR3_REG_FABS
| IR3_REG_SABS
));
252 iassert((src2
->flags
& IR3_REG_IMMED
) ||
253 !((src1
->flags
^ src2
->flags
) & IR3_REG_HALF
));
255 if (src2
->flags
& IR3_REG_RELATIV
) {
256 iassert(src2
->array
.offset
< (1 << 10));
257 cat2
->rel2
.src2
= reg(src2
, info
, instr
->repeat
,
258 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_R
|
259 IR3_REG_HALF
| absneg
);
260 cat2
->rel2
.src2_c
= !!(src2
->flags
& IR3_REG_CONST
);
261 cat2
->rel2
.src2_rel
= 1;
262 } else if (src2
->flags
& IR3_REG_CONST
) {
263 iassert(src2
->num
< (1 << 12));
264 cat2
->c2
.src2
= reg(src2
, info
, instr
->repeat
,
265 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
|
269 iassert(src2
->num
< (1 << 11));
270 cat2
->src2
= reg(src2
, info
, instr
->repeat
,
271 IR3_REG_IMMED
| IR3_REG_R
| IR3_REG_HALF
|
275 cat2
->src2_im
= !!(src2
->flags
& IR3_REG_IMMED
);
276 cat2
->src2_neg
= !!(src2
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
277 cat2
->src2_abs
= !!(src2
->flags
& (IR3_REG_FABS
| IR3_REG_SABS
));
280 cat2
->dst
= reg(dst
, info
, instr
->repeat
,
281 IR3_REG_R
| IR3_REG_EI
| IR3_REG_HALF
);
282 cat2
->repeat
= instr
->repeat
;
283 cat2
->sat
= !!(instr
->flags
& IR3_INSTR_SAT
);
284 cat2
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
285 cat2
->ul
= !!(instr
->flags
& IR3_INSTR_UL
);
286 cat2
->dst_half
= !!((src1
->flags
^ dst
->flags
) & IR3_REG_HALF
);
287 cat2
->ei
= !!(dst
->flags
& IR3_REG_EI
);
288 cat2
->cond
= instr
->cat2
.condition
;
289 cat2
->full
= ! (src1
->flags
& IR3_REG_HALF
);
290 cat2
->opc
= instr
->opc
;
291 cat2
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
292 cat2
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
298 static int emit_cat3(struct ir3_instruction
*instr
, void *ptr
,
299 struct ir3_info
*info
)
301 struct ir3_register
*dst
= instr
->regs
[0];
302 struct ir3_register
*src1
= instr
->regs
[1];
303 struct ir3_register
*src2
= instr
->regs
[2];
304 struct ir3_register
*src3
= instr
->regs
[3];
305 unsigned absneg
= ir3_cat3_absneg(instr
->opc
);
306 instr_cat3_t
*cat3
= ptr
;
307 uint32_t src_flags
= 0;
309 switch (instr
->opc
) {
317 case OPC_SAD_S32
: // really??
318 src_flags
|= IR3_REG_HALF
;
324 iassert(instr
->regs_count
== 4);
325 iassert(!((src1
->flags
^ src_flags
) & IR3_REG_HALF
));
326 iassert(!((src2
->flags
^ src_flags
) & IR3_REG_HALF
));
327 iassert(!((src3
->flags
^ src_flags
) & IR3_REG_HALF
));
330 iassert(!instr
->repeat
);
331 iassert(instr
->nop
<= 3);
333 cat3
->src1_r
= instr
->nop
& 0x1;
334 cat3
->src2_r
= (instr
->nop
>> 1) & 0x1;
336 cat3
->src1_r
= !!(src1
->flags
& IR3_REG_R
);
337 cat3
->src2_r
= !!(src2
->flags
& IR3_REG_R
);
340 if (src1
->flags
& IR3_REG_RELATIV
) {
341 iassert(src1
->array
.offset
< (1 << 10));
342 cat3
->rel1
.src1
= reg(src1
, info
, instr
->repeat
,
343 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_R
|
344 IR3_REG_HALF
| absneg
);
345 cat3
->rel1
.src1_c
= !!(src1
->flags
& IR3_REG_CONST
);
346 cat3
->rel1
.src1_rel
= 1;
347 } else if (src1
->flags
& IR3_REG_CONST
) {
348 iassert(src1
->num
< (1 << 12));
349 cat3
->c1
.src1
= reg(src1
, info
, instr
->repeat
,
350 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
| absneg
);
353 iassert(src1
->num
< (1 << 11));
354 cat3
->src1
= reg(src1
, info
, instr
->repeat
,
355 IR3_REG_R
| IR3_REG_HALF
| absneg
);
358 cat3
->src1_neg
= !!(src1
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
360 cat3
->src2
= reg(src2
, info
, instr
->repeat
,
361 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
| absneg
);
362 cat3
->src2_c
= !!(src2
->flags
& IR3_REG_CONST
);
363 cat3
->src2_neg
= !!(src2
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
365 if (src3
->flags
& IR3_REG_RELATIV
) {
366 iassert(src3
->array
.offset
< (1 << 10));
367 cat3
->rel2
.src3
= reg(src3
, info
, instr
->repeat
,
368 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_R
|
369 IR3_REG_HALF
| absneg
);
370 cat3
->rel2
.src3_c
= !!(src3
->flags
& IR3_REG_CONST
);
371 cat3
->rel2
.src3_rel
= 1;
372 } else if (src3
->flags
& IR3_REG_CONST
) {
373 iassert(src3
->num
< (1 << 12));
374 cat3
->c2
.src3
= reg(src3
, info
, instr
->repeat
,
375 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
| absneg
);
378 iassert(src3
->num
< (1 << 11));
379 cat3
->src3
= reg(src3
, info
, instr
->repeat
,
380 IR3_REG_R
| IR3_REG_HALF
| absneg
);
383 cat3
->src3_neg
= !!(src3
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
384 cat3
->src3_r
= !!(src3
->flags
& IR3_REG_R
);
386 cat3
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
387 cat3
->repeat
= instr
->repeat
;
388 cat3
->sat
= !!(instr
->flags
& IR3_INSTR_SAT
);
389 cat3
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
390 cat3
->ul
= !!(instr
->flags
& IR3_INSTR_UL
);
391 cat3
->dst_half
= !!((src_flags
^ dst
->flags
) & IR3_REG_HALF
);
392 cat3
->opc
= instr
->opc
;
393 cat3
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
394 cat3
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
400 static int emit_cat4(struct ir3_instruction
*instr
, void *ptr
,
401 struct ir3_info
*info
)
403 struct ir3_register
*dst
= instr
->regs
[0];
404 struct ir3_register
*src
= instr
->regs
[1];
405 instr_cat4_t
*cat4
= ptr
;
407 iassert(instr
->regs_count
== 2);
409 if (src
->flags
& IR3_REG_RELATIV
) {
410 iassert(src
->array
.offset
< (1 << 10));
411 cat4
->rel
.src
= reg(src
, info
, instr
->repeat
,
412 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_FNEG
|
413 IR3_REG_FABS
| IR3_REG_R
| IR3_REG_HALF
);
414 cat4
->rel
.src_c
= !!(src
->flags
& IR3_REG_CONST
);
415 cat4
->rel
.src_rel
= 1;
416 } else if (src
->flags
& IR3_REG_CONST
) {
417 iassert(src
->num
< (1 << 12));
418 cat4
->c
.src
= reg(src
, info
, instr
->repeat
,
419 IR3_REG_CONST
| IR3_REG_FNEG
| IR3_REG_FABS
|
420 IR3_REG_R
| IR3_REG_HALF
);
423 iassert(src
->num
< (1 << 11));
424 cat4
->src
= reg(src
, info
, instr
->repeat
,
425 IR3_REG_IMMED
| IR3_REG_FNEG
| IR3_REG_FABS
|
426 IR3_REG_R
| IR3_REG_HALF
);
429 cat4
->src_im
= !!(src
->flags
& IR3_REG_IMMED
);
430 cat4
->src_neg
= !!(src
->flags
& IR3_REG_FNEG
);
431 cat4
->src_abs
= !!(src
->flags
& IR3_REG_FABS
);
432 cat4
->src_r
= !!(src
->flags
& IR3_REG_R
);
434 cat4
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
435 cat4
->repeat
= instr
->repeat
;
436 cat4
->sat
= !!(instr
->flags
& IR3_INSTR_SAT
);
437 cat4
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
438 cat4
->ul
= !!(instr
->flags
& IR3_INSTR_UL
);
439 cat4
->dst_half
= !!((src
->flags
^ dst
->flags
) & IR3_REG_HALF
);
440 cat4
->full
= ! (src
->flags
& IR3_REG_HALF
);
441 cat4
->opc
= instr
->opc
;
442 cat4
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
443 cat4
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
449 static int emit_cat5(struct ir3_instruction
*instr
, void *ptr
,
450 struct ir3_info
*info
)
452 struct ir3_register
*dst
= instr
->regs
[0];
453 /* To simplify things when there could be zero, one, or two args other
454 * than tex/sampler idx, we use the first src reg in the ir to hold
457 struct ir3_register
*src1
;
458 struct ir3_register
*src2
;
459 instr_cat5_t
*cat5
= ptr
;
461 iassert((instr
->regs_count
== 2) ||
462 (instr
->regs_count
== 3) || (instr
->regs_count
== 4));
464 switch (instr
->opc
) {
471 iassert((instr
->flags
& IR3_INSTR_S2EN
) == 0);
472 src1
= instr
->regs
[1];
473 src2
= instr
->regs_count
> 2 ? instr
->regs
[2] : NULL
;
476 src1
= instr
->regs
[2];
477 src2
= instr
->regs_count
> 3 ? instr
->regs
[3] : NULL
;
481 assume(src1
|| !src2
);
484 cat5
->full
= ! (src1
->flags
& IR3_REG_HALF
);
485 cat5
->src1
= reg(src1
, info
, instr
->repeat
, IR3_REG_HALF
);
488 if (instr
->flags
& IR3_INSTR_S2EN
) {
489 struct ir3_register
*samp_tex
= instr
->regs
[1];
491 iassert(!((src1
->flags
^ src2
->flags
) & IR3_REG_HALF
));
492 cat5
->s2en
.src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_HALF
);
494 iassert(samp_tex
->flags
& IR3_REG_HALF
);
495 cat5
->s2en
.src3
= reg(samp_tex
, info
, instr
->repeat
, IR3_REG_HALF
);
496 iassert(!(instr
->cat5
.samp
| instr
->cat5
.tex
));
499 iassert(!((src1
->flags
^ src2
->flags
) & IR3_REG_HALF
));
500 cat5
->norm
.src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_HALF
);
502 cat5
->norm
.samp
= instr
->cat5
.samp
;
503 cat5
->norm
.tex
= instr
->cat5
.tex
;
506 cat5
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
507 cat5
->wrmask
= dst
->wrmask
;
508 cat5
->type
= instr
->cat5
.type
;
509 cat5
->is_3d
= !!(instr
->flags
& IR3_INSTR_3D
);
510 cat5
->is_a
= !!(instr
->flags
& IR3_INSTR_A
);
511 cat5
->is_s
= !!(instr
->flags
& IR3_INSTR_S
);
512 cat5
->is_s2en
= !!(instr
->flags
& IR3_INSTR_S2EN
);
513 cat5
->is_o
= !!(instr
->flags
& IR3_INSTR_O
);
514 cat5
->is_p
= !!(instr
->flags
& IR3_INSTR_P
);
515 cat5
->opc
= instr
->opc
;
516 cat5
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
517 cat5
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
523 static int emit_cat6_a6xx(struct ir3_instruction
*instr
, void *ptr
,
524 struct ir3_info
*info
)
526 struct ir3_register
*src1
, *src2
;
527 instr_cat6_a6xx_t
*cat6
= ptr
;
528 bool has_dest
= (instr
->opc
== OPC_LDIB
);
530 /* first reg should be SSBO binding point: */
531 iassert(instr
->regs
[1]->flags
& IR3_REG_IMMED
);
533 src1
= instr
->regs
[2];
536 /* the src2 field in the instruction is actually the destination
537 * register for load instructions:
539 src2
= instr
->regs
[0];
541 src2
= instr
->regs
[3];
544 cat6
->type
= instr
->cat6
.type
;
545 cat6
->d
= instr
->cat6
.d
- 1;
546 cat6
->typed
= instr
->cat6
.typed
;
547 cat6
->type_size
= instr
->cat6
.iim_val
- 1;
548 cat6
->opc
= instr
->opc
;
549 cat6
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
550 cat6
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
553 cat6
->src1
= reg(src1
, info
, instr
->repeat
, 0);
554 cat6
->src2
= reg(src2
, info
, instr
->repeat
, 0);
555 cat6
->ssbo
= instr
->regs
[1]->iim_val
;
557 switch (instr
->opc
) {
560 case OPC_ATOMIC_XCHG
:
563 case OPC_ATOMIC_CMPXCHG
:
599 static int emit_cat6(struct ir3_instruction
*instr
, void *ptr
,
600 struct ir3_info
*info
)
602 struct ir3_register
*dst
, *src1
, *src2
;
603 instr_cat6_t
*cat6
= ptr
;
605 /* In a6xx we start using a new instruction encoding for some of
606 * these instructions:
608 if (info
->gpu_id
>= 600) {
609 switch (instr
->opc
) {
612 case OPC_ATOMIC_XCHG
:
615 case OPC_ATOMIC_CMPXCHG
:
621 /* The shared variants of these still use the old encoding: */
622 if (!(instr
->flags
& IR3_INSTR_G
))
628 return emit_cat6_a6xx(instr
, ptr
, info
);
634 bool type_full
= type_size(instr
->cat6
.type
) == 32;
636 cat6
->type
= instr
->cat6
.type
;
637 cat6
->opc
= instr
->opc
;
638 cat6
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
639 cat6
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
640 cat6
->g
= !!(instr
->flags
& IR3_INSTR_G
);
643 switch (instr
->opc
) {
646 iassert_type(instr
->regs
[0], type_full
); /* dst */
647 iassert_type(instr
->regs
[1], type_full
); /* src1 */
651 iassert_type(instr
->regs
[0], true); /* dst */
652 iassert_type(instr
->regs
[1], true); /* src1 */
659 /* no dst, so regs[0] is dummy */
660 iassert_type(instr
->regs
[1], true); /* dst */
661 iassert_type(instr
->regs
[2], type_full
); /* src1 */
662 iassert_type(instr
->regs
[3], true); /* src2 */
665 iassert_type(instr
->regs
[0], type_full
); /* dst */
666 iassert_type(instr
->regs
[1], true); /* src1 */
667 if (instr
->regs_count
> 2)
668 iassert_type(instr
->regs
[2], true); /* src1 */
672 /* the "dst" for a store instruction is (from the perspective
673 * of data flow in the shader, ie. register use/def, etc) in
674 * fact a register that is read by the instruction, rather
677 if (is_store(instr
)) {
678 iassert(instr
->regs_count
>= 3);
680 dst
= instr
->regs
[1];
681 src1
= instr
->regs
[2];
682 src2
= (instr
->regs_count
>= 4) ? instr
->regs
[3] : NULL
;
684 iassert(instr
->regs_count
>= 2);
686 dst
= instr
->regs
[0];
687 src1
= instr
->regs
[1];
688 src2
= (instr
->regs_count
>= 3) ? instr
->regs
[2] : NULL
;
691 /* TODO we need a more comprehensive list about which instructions
692 * can be encoded which way. Or possibly use IR3_INSTR_0 flag to
693 * indicate to use the src_off encoding even if offset is zero
694 * (but then what to do about dst_off?)
696 if (is_atomic(instr
->opc
)) {
697 instr_cat6ldgb_t
*ldgb
= ptr
;
699 /* maybe these two bits both determine the instruction encoding? */
700 cat6
->src_off
= false;
702 ldgb
->d
= instr
->cat6
.d
- 1;
703 ldgb
->typed
= instr
->cat6
.typed
;
704 ldgb
->type_size
= instr
->cat6
.iim_val
- 1;
706 ldgb
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
709 struct ir3_register
*src3
= instr
->regs
[3];
710 struct ir3_register
*src4
= instr
->regs
[4];
712 /* first src is src_ssbo: */
713 iassert(src1
->flags
& IR3_REG_IMMED
);
714 ldgb
->src_ssbo
= src1
->uim_val
;
716 ldgb
->src1
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
717 ldgb
->src1_im
= !!(src2
->flags
& IR3_REG_IMMED
);
718 ldgb
->src2
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
719 ldgb
->src2_im
= !!(src3
->flags
& IR3_REG_IMMED
);
721 ldgb
->src3
= reg(src4
, info
, instr
->repeat
, 0);
725 ldgb
->src1
= reg(src1
, info
, instr
->repeat
, IR3_REG_IMMED
);
726 ldgb
->src1_im
= !!(src1
->flags
& IR3_REG_IMMED
);
727 ldgb
->src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
728 ldgb
->src2_im
= !!(src2
->flags
& IR3_REG_IMMED
);
734 } else if (instr
->opc
== OPC_LDGB
) {
735 struct ir3_register
*src3
= instr
->regs
[3];
736 instr_cat6ldgb_t
*ldgb
= ptr
;
738 /* maybe these two bits both determine the instruction encoding? */
739 cat6
->src_off
= false;
741 ldgb
->d
= instr
->cat6
.d
- 1;
742 ldgb
->typed
= instr
->cat6
.typed
;
743 ldgb
->type_size
= instr
->cat6
.iim_val
- 1;
745 ldgb
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
747 /* first src is src_ssbo: */
748 iassert(src1
->flags
& IR3_REG_IMMED
);
749 ldgb
->src_ssbo
= src1
->uim_val
;
751 /* then next two are src1/src2: */
752 ldgb
->src1
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
753 ldgb
->src1_im
= !!(src2
->flags
& IR3_REG_IMMED
);
754 ldgb
->src2
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
755 ldgb
->src2_im
= !!(src3
->flags
& IR3_REG_IMMED
);
761 } else if (instr
->opc
== OPC_RESINFO
) {
762 instr_cat6ldgb_t
*ldgb
= ptr
;
764 ldgb
->d
= instr
->cat6
.d
- 1;
766 ldgb
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
768 /* first src is src_ssbo: */
769 iassert(src1
->flags
& IR3_REG_IMMED
);
770 ldgb
->src_ssbo
= src1
->uim_val
;
773 } else if ((instr
->opc
== OPC_STGB
) || (instr
->opc
== OPC_STIB
)) {
774 struct ir3_register
*src3
= instr
->regs
[4];
775 instr_cat6stgb_t
*stgb
= ptr
;
777 /* maybe these two bits both determine the instruction encoding? */
778 cat6
->src_off
= true;
781 stgb
->d
= instr
->cat6
.d
- 1;
782 stgb
->typed
= instr
->cat6
.typed
;
783 stgb
->type_size
= instr
->cat6
.iim_val
- 1;
785 /* first src is dst_ssbo: */
786 iassert(dst
->flags
& IR3_REG_IMMED
);
787 stgb
->dst_ssbo
= dst
->uim_val
;
789 /* then src1/src2/src3: */
790 stgb
->src1
= reg(src1
, info
, instr
->repeat
, 0);
791 stgb
->src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
792 stgb
->src2_im
= !!(src2
->flags
& IR3_REG_IMMED
);
793 stgb
->src3
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
794 stgb
->src3_im
= !!(src3
->flags
& IR3_REG_IMMED
);
797 } else if (instr
->cat6
.src_offset
|| (instr
->opc
== OPC_LDG
) ||
798 (instr
->opc
== OPC_LDL
) || (instr
->opc
== OPC_LDLW
)) {
799 struct ir3_register
*src3
= instr
->regs
[3];
800 instr_cat6a_t
*cat6a
= ptr
;
802 cat6
->src_off
= true;
804 cat6a
->src1
= reg(src1
, info
, instr
->repeat
, IR3_REG_IMMED
);
805 cat6a
->src1_im
= !!(src1
->flags
& IR3_REG_IMMED
);
808 cat6a
->src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
809 cat6a
->src2_im
= true;
812 iassert(src3
->flags
& IR3_REG_IMMED
);
813 cat6a
->off
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
815 instr_cat6b_t
*cat6b
= ptr
;
817 cat6
->src_off
= false;
819 cat6b
->src1
= reg(src1
, info
, instr
->repeat
, IR3_REG_IMMED
| IR3_REG_HALF
);
820 cat6b
->src1_im
= !!(src1
->flags
& IR3_REG_IMMED
);
822 cat6b
->src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
823 cat6b
->src2_im
= !!(src2
->flags
& IR3_REG_IMMED
);
827 if (instr
->cat6
.dst_offset
|| (instr
->opc
== OPC_STG
) ||
828 (instr
->opc
== OPC_STL
) || (instr
->opc
== OPC_STLW
)) {
829 instr_cat6c_t
*cat6c
= ptr
;
830 cat6
->dst_off
= true;
831 cat6c
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
832 cat6c
->off
= instr
->cat6
.dst_offset
;
834 instr_cat6d_t
*cat6d
= ptr
;
835 cat6
->dst_off
= false;
836 cat6d
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
842 static int emit_cat7(struct ir3_instruction
*instr
, void *ptr
,
843 struct ir3_info
*info
)
845 instr_cat7_t
*cat7
= ptr
;
847 cat7
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
848 cat7
->w
= instr
->cat7
.w
;
849 cat7
->r
= instr
->cat7
.r
;
850 cat7
->l
= instr
->cat7
.l
;
851 cat7
->g
= instr
->cat7
.g
;
852 cat7
->opc
= instr
->opc
;
853 cat7
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
854 cat7
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
860 static int (*emit
[])(struct ir3_instruction
*instr
, void *ptr
,
861 struct ir3_info
*info
) = {
862 emit_cat0
, emit_cat1
, emit_cat2
, emit_cat3
, emit_cat4
, emit_cat5
, emit_cat6
,
866 void * ir3_assemble(struct ir3
*shader
, struct ir3_info
*info
,
869 uint32_t *ptr
, *dwords
;
871 info
->gpu_id
= gpu_id
;
873 info
->max_half_reg
= -1;
874 info
->max_const
= -1;
875 info
->instrs_count
= 0;
876 info
->sizedwords
= 0;
877 info
->ss
= info
->sy
= 0;
879 list_for_each_entry (struct ir3_block
, block
, &shader
->block_list
, node
) {
880 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
881 info
->sizedwords
+= 2;
885 /* need an integer number of instruction "groups" (sets of 16
886 * instructions on a4xx or sets of 4 instructions on a3xx),
887 * so pad out w/ NOPs if needed: (NOTE each instruction is 64bits)
890 info
->sizedwords
= align(info
->sizedwords
, 16 * 2);
892 info
->sizedwords
= align(info
->sizedwords
, 4 * 2);
895 ptr
= dwords
= calloc(4, info
->sizedwords
);
897 list_for_each_entry (struct ir3_block
, block
, &shader
->block_list
, node
) {
898 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
899 int ret
= emit
[opc_cat(instr
->opc
)](instr
, dwords
, info
);
902 info
->instrs_count
+= 1 + instr
->repeat
+ instr
->nop
;
905 if (instr
->flags
& IR3_INSTR_SS
)
908 if (instr
->flags
& IR3_INSTR_SY
)
920 static struct ir3_register
* reg_create(struct ir3
*shader
,
923 struct ir3_register
*reg
=
924 ir3_alloc(shader
, sizeof(struct ir3_register
));
928 if (shader
->compiler
->gpu_id
>= 600)
933 static void insert_instr(struct ir3_block
*block
,
934 struct ir3_instruction
*instr
)
936 struct ir3
*shader
= block
->shader
;
938 instr
->serialno
= ++shader
->instr_count
;
940 list_addtail(&instr
->node
, &block
->instr_list
);
943 array_insert(shader
, shader
->baryfs
, instr
);
946 struct ir3_block
* ir3_block_create(struct ir3
*shader
)
948 struct ir3_block
*block
= ir3_alloc(shader
, sizeof(*block
));
950 block
->serialno
= ++shader
->block_count
;
952 block
->shader
= shader
;
953 list_inithead(&block
->node
);
954 list_inithead(&block
->instr_list
);
958 static struct ir3_instruction
*instr_create(struct ir3_block
*block
, int nreg
)
960 struct ir3_instruction
*instr
;
961 unsigned sz
= sizeof(*instr
) + (nreg
* sizeof(instr
->regs
[0]));
962 char *ptr
= ir3_alloc(block
->shader
, sz
);
964 instr
= (struct ir3_instruction
*)ptr
;
965 ptr
+= sizeof(*instr
);
966 instr
->regs
= (struct ir3_register
**)ptr
;
969 instr
->regs_max
= nreg
;
975 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
978 struct ir3_instruction
*instr
= instr_create(block
, nreg
);
979 instr
->block
= block
;
981 insert_instr(block
, instr
);
985 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
)
987 /* NOTE: we could be slightly more clever, at least for non-meta,
988 * and choose # of regs based on category.
990 return ir3_instr_create2(block
, opc
, 4);
993 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
)
995 struct ir3_instruction
*new_instr
= instr_create(instr
->block
,
997 struct ir3_register
**regs
;
1000 regs
= new_instr
->regs
;
1001 *new_instr
= *instr
;
1002 new_instr
->regs
= regs
;
1004 insert_instr(instr
->block
, new_instr
);
1006 /* clone registers: */
1007 new_instr
->regs_count
= 0;
1008 for (i
= 0; i
< instr
->regs_count
; i
++) {
1009 struct ir3_register
*reg
= instr
->regs
[i
];
1010 struct ir3_register
*new_reg
=
1011 ir3_reg_create(new_instr
, reg
->num
, reg
->flags
);
1018 /* Add a false dependency to instruction, to ensure it is scheduled first: */
1019 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
)
1021 array_insert(instr
, instr
->deps
, dep
);
1024 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
1027 struct ir3
*shader
= instr
->block
->shader
;
1028 struct ir3_register
*reg
= reg_create(shader
, num
, flags
);
1030 debug_assert(instr
->regs_count
< instr
->regs_max
);
1032 instr
->regs
[instr
->regs_count
++] = reg
;
1036 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
1037 struct ir3_register
*reg
)
1039 struct ir3_register
*new_reg
= reg_create(shader
, 0, 0);
1045 ir3_instr_set_address(struct ir3_instruction
*instr
,
1046 struct ir3_instruction
*addr
)
1048 if (instr
->address
!= addr
) {
1049 struct ir3
*ir
= instr
->block
->shader
;
1051 debug_assert(!instr
->address
);
1052 debug_assert(instr
->block
== addr
->block
);
1054 instr
->address
= addr
;
1055 array_insert(ir
, ir
->indirects
, instr
);
1060 ir3_block_clear_mark(struct ir3_block
*block
)
1062 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
)
1063 instr
->flags
&= ~IR3_INSTR_MARK
;
1067 ir3_clear_mark(struct ir3
*ir
)
1069 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
) {
1070 ir3_block_clear_mark(block
);
1074 /* note: this will destroy instr->depth, don't do it until after sched! */
1076 ir3_count_instructions(struct ir3
*ir
)
1079 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
) {
1080 block
->start_ip
= cnt
;
1081 block
->end_ip
= cnt
;
1082 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1084 block
->end_ip
= instr
->ip
;
1091 ir3_lookup_array(struct ir3
*ir
, unsigned id
)
1093 list_for_each_entry (struct ir3_array
, arr
, &ir
->array_list
, node
)