2 * Copyright (c) 2012 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include "util/bitscan.h"
34 #include "util/ralloc.h"
35 #include "util/u_math.h"
37 #include "instr-a3xx.h"
38 #include "ir3_compiler.h"
40 /* simple allocator to carve allocations out of an up-front allocated heap,
41 * so that we can free everything easily in one shot.
43 void * ir3_alloc(struct ir3
*shader
, int sz
)
45 return rzalloc_size(shader
, sz
); /* TODO: don't use rzalloc */
48 struct ir3
* ir3_create(struct ir3_compiler
*compiler
, gl_shader_stage type
)
50 struct ir3
*shader
= rzalloc(NULL
, struct ir3
);
52 shader
->compiler
= compiler
;
55 list_inithead(&shader
->block_list
);
56 list_inithead(&shader
->array_list
);
61 void ir3_destroy(struct ir3
*shader
)
66 #define iassert(cond) do { \
72 #define iassert_type(reg, full) do { \
74 iassert(!((reg)->flags & IR3_REG_HALF)); \
76 iassert((reg)->flags & IR3_REG_HALF); \
79 static uint32_t reg(struct ir3_register
*reg
, struct ir3_info
*info
,
80 uint32_t repeat
, uint32_t valid_flags
)
82 reg_t val
= { .dummy32
= 0 };
84 if (reg
->flags
& ~valid_flags
) {
85 debug_printf("INVALID FLAGS: %x vs %x\n",
86 reg
->flags
, valid_flags
);
89 if (!(reg
->flags
& IR3_REG_R
))
92 if (reg
->flags
& IR3_REG_IMMED
) {
93 val
.iim_val
= reg
->iim_val
;
98 if (reg
->flags
& IR3_REG_RELATIV
) {
99 components
= reg
->size
;
100 val
.idummy10
= reg
->array
.offset
;
101 max
= (reg
->array
.offset
+ repeat
+ components
- 1);
103 components
= util_last_bit(reg
->wrmask
);
104 val
.comp
= reg
->num
& 0x3;
105 val
.num
= reg
->num
>> 2;
106 max
= (reg
->num
+ repeat
+ components
- 1);
109 if (reg
->flags
& IR3_REG_CONST
) {
110 info
->max_const
= MAX2(info
->max_const
, max
>> 2);
111 } else if (val
.num
== 63) {
112 /* ignore writes to dummy register r63.x */
113 } else if (max
< regid(48, 0)) {
114 if (reg
->flags
& IR3_REG_HALF
) {
115 if (info
->gpu_id
>= 600) {
116 /* starting w/ a6xx, half regs conflict with full regs: */
117 info
->max_reg
= MAX2(info
->max_reg
, max
>> 3);
119 info
->max_half_reg
= MAX2(info
->max_half_reg
, max
>> 2);
122 info
->max_reg
= MAX2(info
->max_reg
, max
>> 2);
130 static int emit_cat0(struct ir3_instruction
*instr
, void *ptr
,
131 struct ir3_info
*info
)
133 instr_cat0_t
*cat0
= ptr
;
135 if (info
->gpu_id
>= 500) {
136 cat0
->a5xx
.immed
= instr
->cat0
.immed
;
137 } else if (info
->gpu_id
>= 400) {
138 cat0
->a4xx
.immed
= instr
->cat0
.immed
;
140 cat0
->a3xx
.immed
= instr
->cat0
.immed
;
142 cat0
->repeat
= instr
->repeat
;
143 cat0
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
144 cat0
->inv
= instr
->cat0
.inv
;
145 cat0
->comp
= instr
->cat0
.comp
;
146 cat0
->opc
= instr
->opc
;
147 cat0
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
148 cat0
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
151 if (instr
->opc
== OPC_CONDEND
|| instr
->opc
== OPC_ENDPATCH
)
157 static int emit_cat1(struct ir3_instruction
*instr
, void *ptr
,
158 struct ir3_info
*info
)
160 struct ir3_register
*dst
= instr
->regs
[0];
161 struct ir3_register
*src
= instr
->regs
[1];
162 instr_cat1_t
*cat1
= ptr
;
164 iassert(instr
->regs_count
== 2);
165 iassert_type(dst
, type_size(instr
->cat1
.dst_type
) == 32);
166 if (!(src
->flags
& IR3_REG_IMMED
))
167 iassert_type(src
, type_size(instr
->cat1
.src_type
) == 32);
169 if (src
->flags
& IR3_REG_IMMED
) {
170 cat1
->iim_val
= src
->iim_val
;
172 } else if (src
->flags
& IR3_REG_RELATIV
) {
173 cat1
->off
= reg(src
, info
, instr
->repeat
,
174 IR3_REG_R
| IR3_REG_CONST
| IR3_REG_HALF
| IR3_REG_RELATIV
);
176 cat1
->src_rel_c
= !!(src
->flags
& IR3_REG_CONST
);
178 cat1
->src
= reg(src
, info
, instr
->repeat
,
179 IR3_REG_R
| IR3_REG_CONST
| IR3_REG_HALF
);
180 cat1
->src_c
= !!(src
->flags
& IR3_REG_CONST
);
183 cat1
->dst
= reg(dst
, info
, instr
->repeat
,
184 IR3_REG_RELATIV
| IR3_REG_EVEN
|
185 IR3_REG_R
| IR3_REG_POS_INF
| IR3_REG_HALF
);
186 cat1
->repeat
= instr
->repeat
;
187 cat1
->src_r
= !!(src
->flags
& IR3_REG_R
);
188 cat1
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
189 cat1
->ul
= !!(instr
->flags
& IR3_INSTR_UL
);
190 cat1
->dst_type
= instr
->cat1
.dst_type
;
191 cat1
->dst_rel
= !!(dst
->flags
& IR3_REG_RELATIV
);
192 cat1
->src_type
= instr
->cat1
.src_type
;
193 cat1
->even
= !!(dst
->flags
& IR3_REG_EVEN
);
194 cat1
->pos_inf
= !!(dst
->flags
& IR3_REG_POS_INF
);
195 cat1
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
196 cat1
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
202 static int emit_cat2(struct ir3_instruction
*instr
, void *ptr
,
203 struct ir3_info
*info
)
205 struct ir3_register
*dst
= instr
->regs
[0];
206 struct ir3_register
*src1
= instr
->regs
[1];
207 struct ir3_register
*src2
= instr
->regs
[2];
208 instr_cat2_t
*cat2
= ptr
;
209 unsigned absneg
= ir3_cat2_absneg(instr
->opc
);
211 iassert((instr
->regs_count
== 2) || (instr
->regs_count
== 3));
214 iassert(!instr
->repeat
);
215 iassert(instr
->nop
<= 3);
217 cat2
->src1_r
= instr
->nop
& 0x1;
218 cat2
->src2_r
= (instr
->nop
>> 1) & 0x1;
220 cat2
->src1_r
= !!(src1
->flags
& IR3_REG_R
);
222 cat2
->src2_r
= !!(src2
->flags
& IR3_REG_R
);
225 if (src1
->flags
& IR3_REG_RELATIV
) {
226 iassert(src1
->array
.offset
< (1 << 10));
227 cat2
->rel1
.src1
= reg(src1
, info
, instr
->repeat
,
228 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_R
|
229 IR3_REG_HALF
| absneg
);
230 cat2
->rel1
.src1_c
= !!(src1
->flags
& IR3_REG_CONST
);
231 cat2
->rel1
.src1_rel
= 1;
232 } else if (src1
->flags
& IR3_REG_CONST
) {
233 iassert(src1
->num
< (1 << 12));
234 cat2
->c1
.src1
= reg(src1
, info
, instr
->repeat
,
235 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
|
239 iassert(src1
->num
< (1 << 11));
240 cat2
->src1
= reg(src1
, info
, instr
->repeat
,
241 IR3_REG_IMMED
| IR3_REG_R
| IR3_REG_HALF
|
244 cat2
->src1_im
= !!(src1
->flags
& IR3_REG_IMMED
);
245 cat2
->src1_neg
= !!(src1
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
246 cat2
->src1_abs
= !!(src1
->flags
& (IR3_REG_FABS
| IR3_REG_SABS
));
249 iassert((src2
->flags
& IR3_REG_IMMED
) ||
250 !((src1
->flags
^ src2
->flags
) & IR3_REG_HALF
));
252 if (src2
->flags
& IR3_REG_RELATIV
) {
253 iassert(src2
->array
.offset
< (1 << 10));
254 cat2
->rel2
.src2
= reg(src2
, info
, instr
->repeat
,
255 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_R
|
256 IR3_REG_HALF
| absneg
);
257 cat2
->rel2
.src2_c
= !!(src2
->flags
& IR3_REG_CONST
);
258 cat2
->rel2
.src2_rel
= 1;
259 } else if (src2
->flags
& IR3_REG_CONST
) {
260 iassert(src2
->num
< (1 << 12));
261 cat2
->c2
.src2
= reg(src2
, info
, instr
->repeat
,
262 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
|
266 iassert(src2
->num
< (1 << 11));
267 cat2
->src2
= reg(src2
, info
, instr
->repeat
,
268 IR3_REG_IMMED
| IR3_REG_R
| IR3_REG_HALF
|
272 cat2
->src2_im
= !!(src2
->flags
& IR3_REG_IMMED
);
273 cat2
->src2_neg
= !!(src2
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
274 cat2
->src2_abs
= !!(src2
->flags
& (IR3_REG_FABS
| IR3_REG_SABS
));
277 cat2
->dst
= reg(dst
, info
, instr
->repeat
,
278 IR3_REG_R
| IR3_REG_EI
| IR3_REG_HALF
);
279 cat2
->repeat
= instr
->repeat
;
280 cat2
->sat
= !!(instr
->flags
& IR3_INSTR_SAT
);
281 cat2
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
282 cat2
->ul
= !!(instr
->flags
& IR3_INSTR_UL
);
283 cat2
->dst_half
= !!((src1
->flags
^ dst
->flags
) & IR3_REG_HALF
);
284 cat2
->ei
= !!(dst
->flags
& IR3_REG_EI
);
285 cat2
->cond
= instr
->cat2
.condition
;
286 cat2
->full
= ! (src1
->flags
& IR3_REG_HALF
);
287 cat2
->opc
= instr
->opc
;
288 cat2
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
289 cat2
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
295 static int emit_cat3(struct ir3_instruction
*instr
, void *ptr
,
296 struct ir3_info
*info
)
298 struct ir3_register
*dst
= instr
->regs
[0];
299 struct ir3_register
*src1
= instr
->regs
[1];
300 struct ir3_register
*src2
= instr
->regs
[2];
301 struct ir3_register
*src3
= instr
->regs
[3];
302 unsigned absneg
= ir3_cat3_absneg(instr
->opc
);
303 instr_cat3_t
*cat3
= ptr
;
304 uint32_t src_flags
= 0;
306 switch (instr
->opc
) {
314 case OPC_SAD_S32
: // really??
315 src_flags
|= IR3_REG_HALF
;
321 iassert(instr
->regs_count
== 4);
322 iassert(!((src1
->flags
^ src_flags
) & IR3_REG_HALF
));
323 iassert(!((src2
->flags
^ src_flags
) & IR3_REG_HALF
));
324 iassert(!((src3
->flags
^ src_flags
) & IR3_REG_HALF
));
327 iassert(!instr
->repeat
);
328 iassert(instr
->nop
<= 3);
330 cat3
->src1_r
= instr
->nop
& 0x1;
331 cat3
->src2_r
= (instr
->nop
>> 1) & 0x1;
333 cat3
->src1_r
= !!(src1
->flags
& IR3_REG_R
);
334 cat3
->src2_r
= !!(src2
->flags
& IR3_REG_R
);
337 if (src1
->flags
& IR3_REG_RELATIV
) {
338 iassert(src1
->array
.offset
< (1 << 10));
339 cat3
->rel1
.src1
= reg(src1
, info
, instr
->repeat
,
340 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_R
|
341 IR3_REG_HALF
| absneg
);
342 cat3
->rel1
.src1_c
= !!(src1
->flags
& IR3_REG_CONST
);
343 cat3
->rel1
.src1_rel
= 1;
344 } else if (src1
->flags
& IR3_REG_CONST
) {
345 iassert(src1
->num
< (1 << 12));
346 cat3
->c1
.src1
= reg(src1
, info
, instr
->repeat
,
347 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
| absneg
);
350 iassert(src1
->num
< (1 << 11));
351 cat3
->src1
= reg(src1
, info
, instr
->repeat
,
352 IR3_REG_R
| IR3_REG_HALF
| absneg
);
355 cat3
->src1_neg
= !!(src1
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
357 cat3
->src2
= reg(src2
, info
, instr
->repeat
,
358 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
| absneg
);
359 cat3
->src2_c
= !!(src2
->flags
& IR3_REG_CONST
);
360 cat3
->src2_neg
= !!(src2
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
362 if (src3
->flags
& IR3_REG_RELATIV
) {
363 iassert(src3
->array
.offset
< (1 << 10));
364 cat3
->rel2
.src3
= reg(src3
, info
, instr
->repeat
,
365 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_R
|
366 IR3_REG_HALF
| absneg
);
367 cat3
->rel2
.src3_c
= !!(src3
->flags
& IR3_REG_CONST
);
368 cat3
->rel2
.src3_rel
= 1;
369 } else if (src3
->flags
& IR3_REG_CONST
) {
370 iassert(src3
->num
< (1 << 12));
371 cat3
->c2
.src3
= reg(src3
, info
, instr
->repeat
,
372 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
| absneg
);
375 iassert(src3
->num
< (1 << 11));
376 cat3
->src3
= reg(src3
, info
, instr
->repeat
,
377 IR3_REG_R
| IR3_REG_HALF
| absneg
);
380 cat3
->src3_neg
= !!(src3
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
381 cat3
->src3_r
= !!(src3
->flags
& IR3_REG_R
);
383 cat3
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
384 cat3
->repeat
= instr
->repeat
;
385 cat3
->sat
= !!(instr
->flags
& IR3_INSTR_SAT
);
386 cat3
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
387 cat3
->ul
= !!(instr
->flags
& IR3_INSTR_UL
);
388 cat3
->dst_half
= !!((src_flags
^ dst
->flags
) & IR3_REG_HALF
);
389 cat3
->opc
= instr
->opc
;
390 cat3
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
391 cat3
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
397 static int emit_cat4(struct ir3_instruction
*instr
, void *ptr
,
398 struct ir3_info
*info
)
400 struct ir3_register
*dst
= instr
->regs
[0];
401 struct ir3_register
*src
= instr
->regs
[1];
402 instr_cat4_t
*cat4
= ptr
;
404 iassert(instr
->regs_count
== 2);
406 if (src
->flags
& IR3_REG_RELATIV
) {
407 iassert(src
->array
.offset
< (1 << 10));
408 cat4
->rel
.src
= reg(src
, info
, instr
->repeat
,
409 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_FNEG
|
410 IR3_REG_FABS
| IR3_REG_R
| IR3_REG_HALF
);
411 cat4
->rel
.src_c
= !!(src
->flags
& IR3_REG_CONST
);
412 cat4
->rel
.src_rel
= 1;
413 } else if (src
->flags
& IR3_REG_CONST
) {
414 iassert(src
->num
< (1 << 12));
415 cat4
->c
.src
= reg(src
, info
, instr
->repeat
,
416 IR3_REG_CONST
| IR3_REG_FNEG
| IR3_REG_FABS
|
417 IR3_REG_R
| IR3_REG_HALF
);
420 iassert(src
->num
< (1 << 11));
421 cat4
->src
= reg(src
, info
, instr
->repeat
,
422 IR3_REG_IMMED
| IR3_REG_FNEG
| IR3_REG_FABS
|
423 IR3_REG_R
| IR3_REG_HALF
);
426 cat4
->src_im
= !!(src
->flags
& IR3_REG_IMMED
);
427 cat4
->src_neg
= !!(src
->flags
& IR3_REG_FNEG
);
428 cat4
->src_abs
= !!(src
->flags
& IR3_REG_FABS
);
429 cat4
->src_r
= !!(src
->flags
& IR3_REG_R
);
431 cat4
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
432 cat4
->repeat
= instr
->repeat
;
433 cat4
->sat
= !!(instr
->flags
& IR3_INSTR_SAT
);
434 cat4
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
435 cat4
->ul
= !!(instr
->flags
& IR3_INSTR_UL
);
436 cat4
->dst_half
= !!((src
->flags
^ dst
->flags
) & IR3_REG_HALF
);
437 cat4
->full
= ! (src
->flags
& IR3_REG_HALF
);
438 cat4
->opc
= instr
->opc
;
439 cat4
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
440 cat4
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
446 static int emit_cat5(struct ir3_instruction
*instr
, void *ptr
,
447 struct ir3_info
*info
)
449 struct ir3_register
*dst
= instr
->regs
[0];
450 /* To simplify things when there could be zero, one, or two args other
451 * than tex/sampler idx, we use the first src reg in the ir to hold
454 struct ir3_register
*src1
;
455 struct ir3_register
*src2
;
456 instr_cat5_t
*cat5
= ptr
;
458 iassert((instr
->regs_count
== 2) ||
459 (instr
->regs_count
== 3) || (instr
->regs_count
== 4));
461 switch (instr
->opc
) {
468 iassert((instr
->flags
& IR3_INSTR_S2EN
) == 0);
469 src1
= instr
->regs
[1];
470 src2
= instr
->regs_count
> 2 ? instr
->regs
[2] : NULL
;
473 src1
= instr
->regs
[2];
474 src2
= instr
->regs_count
> 3 ? instr
->regs
[3] : NULL
;
478 assume(src1
|| !src2
);
481 cat5
->full
= ! (src1
->flags
& IR3_REG_HALF
);
482 cat5
->src1
= reg(src1
, info
, instr
->repeat
, IR3_REG_HALF
);
485 if (instr
->flags
& IR3_INSTR_S2EN
) {
486 struct ir3_register
*samp_tex
= instr
->regs
[1];
488 iassert(!((src1
->flags
^ src2
->flags
) & IR3_REG_HALF
));
489 cat5
->s2en
.src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_HALF
);
491 iassert(samp_tex
->flags
& IR3_REG_HALF
);
492 cat5
->s2en
.src3
= reg(samp_tex
, info
, instr
->repeat
, IR3_REG_HALF
);
493 iassert(!(instr
->cat5
.samp
| instr
->cat5
.tex
));
496 iassert(!((src1
->flags
^ src2
->flags
) & IR3_REG_HALF
));
497 cat5
->norm
.src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_HALF
);
499 cat5
->norm
.samp
= instr
->cat5
.samp
;
500 cat5
->norm
.tex
= instr
->cat5
.tex
;
503 cat5
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
504 cat5
->wrmask
= dst
->wrmask
;
505 cat5
->type
= instr
->cat5
.type
;
506 cat5
->is_3d
= !!(instr
->flags
& IR3_INSTR_3D
);
507 cat5
->is_a
= !!(instr
->flags
& IR3_INSTR_A
);
508 cat5
->is_s
= !!(instr
->flags
& IR3_INSTR_S
);
509 cat5
->is_s2en
= !!(instr
->flags
& IR3_INSTR_S2EN
);
510 cat5
->is_o
= !!(instr
->flags
& IR3_INSTR_O
);
511 cat5
->is_p
= !!(instr
->flags
& IR3_INSTR_P
);
512 cat5
->opc
= instr
->opc
;
513 cat5
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
514 cat5
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
520 static int emit_cat6_a6xx(struct ir3_instruction
*instr
, void *ptr
,
521 struct ir3_info
*info
)
523 struct ir3_register
*src1
, *src2
;
524 instr_cat6_a6xx_t
*cat6
= ptr
;
525 bool has_dest
= (instr
->opc
== OPC_LDIB
);
527 /* first reg should be SSBO binding point: */
528 iassert(instr
->regs
[1]->flags
& IR3_REG_IMMED
);
530 src1
= instr
->regs
[2];
533 /* the src2 field in the instruction is actually the destination
534 * register for load instructions:
536 src2
= instr
->regs
[0];
538 src2
= instr
->regs
[3];
541 cat6
->type
= instr
->cat6
.type
;
542 cat6
->d
= instr
->cat6
.d
- 1;
543 cat6
->typed
= instr
->cat6
.typed
;
544 cat6
->type_size
= instr
->cat6
.iim_val
- 1;
545 cat6
->opc
= instr
->opc
;
546 cat6
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
547 cat6
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
550 cat6
->src1
= reg(src1
, info
, instr
->repeat
, 0);
551 cat6
->src2
= reg(src2
, info
, instr
->repeat
, 0);
552 cat6
->ssbo
= instr
->regs
[1]->iim_val
;
554 switch (instr
->opc
) {
557 case OPC_ATOMIC_XCHG
:
560 case OPC_ATOMIC_CMPXCHG
:
596 static int emit_cat6(struct ir3_instruction
*instr
, void *ptr
,
597 struct ir3_info
*info
)
599 struct ir3_register
*dst
, *src1
, *src2
;
600 instr_cat6_t
*cat6
= ptr
;
602 /* In a6xx we start using a new instruction encoding for some of
603 * these instructions:
605 if (info
->gpu_id
>= 600) {
606 switch (instr
->opc
) {
609 case OPC_ATOMIC_XCHG
:
612 case OPC_ATOMIC_CMPXCHG
:
618 /* The shared variants of these still use the old encoding: */
619 if (!(instr
->flags
& IR3_INSTR_G
))
625 return emit_cat6_a6xx(instr
, ptr
, info
);
631 bool type_full
= type_size(instr
->cat6
.type
) == 32;
633 cat6
->type
= instr
->cat6
.type
;
634 cat6
->opc
= instr
->opc
;
635 cat6
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
636 cat6
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
637 cat6
->g
= !!(instr
->flags
& IR3_INSTR_G
);
640 switch (instr
->opc
) {
643 iassert_type(instr
->regs
[0], type_full
); /* dst */
644 iassert_type(instr
->regs
[1], type_full
); /* src1 */
648 iassert_type(instr
->regs
[0], true); /* dst */
649 iassert_type(instr
->regs
[1], true); /* src1 */
656 /* no dst, so regs[0] is dummy */
657 iassert_type(instr
->regs
[1], true); /* dst */
658 iassert_type(instr
->regs
[2], type_full
); /* src1 */
659 iassert_type(instr
->regs
[3], true); /* src2 */
662 iassert_type(instr
->regs
[0], type_full
); /* dst */
663 iassert_type(instr
->regs
[1], true); /* src1 */
664 if (instr
->regs_count
> 2)
665 iassert_type(instr
->regs
[2], true); /* src1 */
669 /* the "dst" for a store instruction is (from the perspective
670 * of data flow in the shader, ie. register use/def, etc) in
671 * fact a register that is read by the instruction, rather
674 if (is_store(instr
)) {
675 iassert(instr
->regs_count
>= 3);
677 dst
= instr
->regs
[1];
678 src1
= instr
->regs
[2];
679 src2
= (instr
->regs_count
>= 4) ? instr
->regs
[3] : NULL
;
681 iassert(instr
->regs_count
>= 2);
683 dst
= instr
->regs
[0];
684 src1
= instr
->regs
[1];
685 src2
= (instr
->regs_count
>= 3) ? instr
->regs
[2] : NULL
;
688 /* TODO we need a more comprehensive list about which instructions
689 * can be encoded which way. Or possibly use IR3_INSTR_0 flag to
690 * indicate to use the src_off encoding even if offset is zero
691 * (but then what to do about dst_off?)
693 if (is_atomic(instr
->opc
)) {
694 instr_cat6ldgb_t
*ldgb
= ptr
;
696 /* maybe these two bits both determine the instruction encoding? */
697 cat6
->src_off
= false;
699 ldgb
->d
= instr
->cat6
.d
- 1;
700 ldgb
->typed
= instr
->cat6
.typed
;
701 ldgb
->type_size
= instr
->cat6
.iim_val
- 1;
703 ldgb
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
706 struct ir3_register
*src3
= instr
->regs
[3];
707 struct ir3_register
*src4
= instr
->regs
[4];
709 /* first src is src_ssbo: */
710 iassert(src1
->flags
& IR3_REG_IMMED
);
711 ldgb
->src_ssbo
= src1
->uim_val
;
713 ldgb
->src1
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
714 ldgb
->src1_im
= !!(src2
->flags
& IR3_REG_IMMED
);
715 ldgb
->src2
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
716 ldgb
->src2_im
= !!(src3
->flags
& IR3_REG_IMMED
);
718 ldgb
->src3
= reg(src4
, info
, instr
->repeat
, 0);
722 ldgb
->src1
= reg(src1
, info
, instr
->repeat
, IR3_REG_IMMED
);
723 ldgb
->src1_im
= !!(src1
->flags
& IR3_REG_IMMED
);
724 ldgb
->src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
725 ldgb
->src2_im
= !!(src2
->flags
& IR3_REG_IMMED
);
731 } else if (instr
->opc
== OPC_LDGB
) {
732 struct ir3_register
*src3
= instr
->regs
[3];
733 instr_cat6ldgb_t
*ldgb
= ptr
;
735 /* maybe these two bits both determine the instruction encoding? */
736 cat6
->src_off
= false;
738 ldgb
->d
= instr
->cat6
.d
- 1;
739 ldgb
->typed
= instr
->cat6
.typed
;
740 ldgb
->type_size
= instr
->cat6
.iim_val
- 1;
742 ldgb
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
744 /* first src is src_ssbo: */
745 iassert(src1
->flags
& IR3_REG_IMMED
);
746 ldgb
->src_ssbo
= src1
->uim_val
;
748 /* then next two are src1/src2: */
749 ldgb
->src1
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
750 ldgb
->src1_im
= !!(src2
->flags
& IR3_REG_IMMED
);
751 ldgb
->src2
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
752 ldgb
->src2_im
= !!(src3
->flags
& IR3_REG_IMMED
);
758 } else if (instr
->opc
== OPC_RESINFO
) {
759 instr_cat6ldgb_t
*ldgb
= ptr
;
761 ldgb
->d
= instr
->cat6
.d
- 1;
763 ldgb
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
765 /* first src is src_ssbo: */
766 iassert(src1
->flags
& IR3_REG_IMMED
);
767 ldgb
->src_ssbo
= src1
->uim_val
;
770 } else if ((instr
->opc
== OPC_STGB
) || (instr
->opc
== OPC_STIB
)) {
771 struct ir3_register
*src3
= instr
->regs
[4];
772 instr_cat6stgb_t
*stgb
= ptr
;
774 /* maybe these two bits both determine the instruction encoding? */
775 cat6
->src_off
= true;
778 stgb
->d
= instr
->cat6
.d
- 1;
779 stgb
->typed
= instr
->cat6
.typed
;
780 stgb
->type_size
= instr
->cat6
.iim_val
- 1;
782 /* first src is dst_ssbo: */
783 iassert(dst
->flags
& IR3_REG_IMMED
);
784 stgb
->dst_ssbo
= dst
->uim_val
;
786 /* then src1/src2/src3: */
787 stgb
->src1
= reg(src1
, info
, instr
->repeat
, 0);
788 stgb
->src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
789 stgb
->src2_im
= !!(src2
->flags
& IR3_REG_IMMED
);
790 stgb
->src3
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
791 stgb
->src3_im
= !!(src3
->flags
& IR3_REG_IMMED
);
794 } else if (instr
->cat6
.src_offset
|| (instr
->opc
== OPC_LDG
) ||
795 (instr
->opc
== OPC_LDL
) || (instr
->opc
== OPC_LDLW
)) {
796 struct ir3_register
*src3
= instr
->regs
[3];
797 instr_cat6a_t
*cat6a
= ptr
;
799 cat6
->src_off
= true;
801 if (instr
->opc
== OPC_LDG
) {
802 /* For LDG src1 can not be immediate, so src1_imm is redundant and
803 * instead used to signal whether (when true) 'off' is a 32 bit
804 * register or an immediate offset.
806 cat6a
->src1
= reg(src1
, info
, instr
->repeat
, 0);
807 cat6a
->src1_im
= !(src3
->flags
& IR3_REG_IMMED
);
808 cat6a
->off
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
810 cat6a
->src1
= reg(src1
, info
, instr
->repeat
, IR3_REG_IMMED
);
811 cat6a
->src1_im
= !!(src1
->flags
& IR3_REG_IMMED
);
812 cat6a
->off
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
813 iassert(src3
->flags
& IR3_REG_IMMED
);
817 cat6a
->src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
818 cat6a
->src2_im
= true;
820 instr_cat6b_t
*cat6b
= ptr
;
822 cat6
->src_off
= false;
824 cat6b
->src1
= reg(src1
, info
, instr
->repeat
, IR3_REG_IMMED
| IR3_REG_HALF
);
825 cat6b
->src1_im
= !!(src1
->flags
& IR3_REG_IMMED
);
827 cat6b
->src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
828 cat6b
->src2_im
= !!(src2
->flags
& IR3_REG_IMMED
);
832 if (instr
->cat6
.dst_offset
|| (instr
->opc
== OPC_STG
) ||
833 (instr
->opc
== OPC_STL
) || (instr
->opc
== OPC_STLW
)) {
834 instr_cat6c_t
*cat6c
= ptr
;
835 cat6
->dst_off
= true;
836 cat6c
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
838 if (instr
->flags
& IR3_INSTR_G
) {
839 struct ir3_register
*src3
= instr
->regs
[4];
840 cat6c
->off
= reg(src3
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
841 if (src3
->flags
& IR3_REG_IMMED
) {
842 /* Immediate offsets are in bytes... */
847 cat6c
->off
= instr
->cat6
.dst_offset
;
850 instr_cat6d_t
*cat6d
= ptr
;
851 cat6
->dst_off
= false;
852 cat6d
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
858 static int emit_cat7(struct ir3_instruction
*instr
, void *ptr
,
859 struct ir3_info
*info
)
861 instr_cat7_t
*cat7
= ptr
;
863 cat7
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
864 cat7
->w
= instr
->cat7
.w
;
865 cat7
->r
= instr
->cat7
.r
;
866 cat7
->l
= instr
->cat7
.l
;
867 cat7
->g
= instr
->cat7
.g
;
868 cat7
->opc
= instr
->opc
;
869 cat7
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
870 cat7
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
876 static int (*emit
[])(struct ir3_instruction
*instr
, void *ptr
,
877 struct ir3_info
*info
) = {
878 emit_cat0
, emit_cat1
, emit_cat2
, emit_cat3
, emit_cat4
, emit_cat5
, emit_cat6
,
882 void * ir3_assemble(struct ir3
*shader
, struct ir3_info
*info
,
885 uint32_t *ptr
, *dwords
;
887 info
->gpu_id
= gpu_id
;
889 info
->max_half_reg
= -1;
890 info
->max_const
= -1;
891 info
->instrs_count
= 0;
892 info
->sizedwords
= 0;
893 info
->ss
= info
->sy
= 0;
895 list_for_each_entry (struct ir3_block
, block
, &shader
->block_list
, node
) {
896 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
897 info
->sizedwords
+= 2;
901 /* need an integer number of instruction "groups" (sets of 16
902 * instructions on a4xx or sets of 4 instructions on a3xx),
903 * so pad out w/ NOPs if needed: (NOTE each instruction is 64bits)
906 info
->sizedwords
= align(info
->sizedwords
, 16 * 2);
908 info
->sizedwords
= align(info
->sizedwords
, 4 * 2);
911 ptr
= dwords
= calloc(4, info
->sizedwords
);
913 list_for_each_entry (struct ir3_block
, block
, &shader
->block_list
, node
) {
914 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
915 int ret
= emit
[opc_cat(instr
->opc
)](instr
, dwords
, info
);
918 info
->instrs_count
+= 1 + instr
->repeat
+ instr
->nop
;
919 info
->nops_count
+= instr
->nop
;
920 if (instr
->opc
== OPC_NOP
)
921 info
->nops_count
+= 1 + instr
->repeat
;
924 if (instr
->flags
& IR3_INSTR_SS
)
927 if (instr
->flags
& IR3_INSTR_SY
)
939 static struct ir3_register
* reg_create(struct ir3
*shader
,
942 struct ir3_register
*reg
=
943 ir3_alloc(shader
, sizeof(struct ir3_register
));
947 if (shader
->compiler
->gpu_id
>= 600)
952 static void insert_instr(struct ir3_block
*block
,
953 struct ir3_instruction
*instr
)
955 struct ir3
*shader
= block
->shader
;
957 instr
->serialno
= ++shader
->instr_count
;
959 list_addtail(&instr
->node
, &block
->instr_list
);
962 array_insert(shader
, shader
->baryfs
, instr
);
965 struct ir3_block
* ir3_block_create(struct ir3
*shader
)
967 struct ir3_block
*block
= ir3_alloc(shader
, sizeof(*block
));
969 block
->serialno
= ++shader
->block_count
;
971 block
->shader
= shader
;
972 list_inithead(&block
->node
);
973 list_inithead(&block
->instr_list
);
977 static struct ir3_instruction
*instr_create(struct ir3_block
*block
, int nreg
)
979 struct ir3_instruction
*instr
;
980 unsigned sz
= sizeof(*instr
) + (nreg
* sizeof(instr
->regs
[0]));
981 char *ptr
= ir3_alloc(block
->shader
, sz
);
983 instr
= (struct ir3_instruction
*)ptr
;
984 ptr
+= sizeof(*instr
);
985 instr
->regs
= (struct ir3_register
**)ptr
;
988 instr
->regs_max
= nreg
;
994 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
997 struct ir3_instruction
*instr
= instr_create(block
, nreg
);
998 instr
->block
= block
;
1000 insert_instr(block
, instr
);
1004 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
)
1006 /* NOTE: we could be slightly more clever, at least for non-meta,
1007 * and choose # of regs based on category.
1009 return ir3_instr_create2(block
, opc
, 4);
1012 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
)
1014 struct ir3_instruction
*new_instr
= instr_create(instr
->block
,
1016 struct ir3_register
**regs
;
1019 regs
= new_instr
->regs
;
1020 *new_instr
= *instr
;
1021 new_instr
->regs
= regs
;
1023 insert_instr(instr
->block
, new_instr
);
1025 /* clone registers: */
1026 new_instr
->regs_count
= 0;
1027 for (i
= 0; i
< instr
->regs_count
; i
++) {
1028 struct ir3_register
*reg
= instr
->regs
[i
];
1029 struct ir3_register
*new_reg
=
1030 ir3_reg_create(new_instr
, reg
->num
, reg
->flags
);
1037 /* Add a false dependency to instruction, to ensure it is scheduled first: */
1038 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
)
1040 array_insert(instr
, instr
->deps
, dep
);
1043 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
1046 struct ir3
*shader
= instr
->block
->shader
;
1047 struct ir3_register
*reg
= reg_create(shader
, num
, flags
);
1049 debug_assert(instr
->regs_count
< instr
->regs_max
);
1051 instr
->regs
[instr
->regs_count
++] = reg
;
1055 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
1056 struct ir3_register
*reg
)
1058 struct ir3_register
*new_reg
= reg_create(shader
, 0, 0);
1064 ir3_instr_set_address(struct ir3_instruction
*instr
,
1065 struct ir3_instruction
*addr
)
1067 if (instr
->address
!= addr
) {
1068 struct ir3
*ir
= instr
->block
->shader
;
1070 debug_assert(!instr
->address
);
1071 debug_assert(instr
->block
== addr
->block
);
1073 instr
->address
= addr
;
1074 array_insert(ir
, ir
->indirects
, instr
);
1079 ir3_block_clear_mark(struct ir3_block
*block
)
1081 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
)
1082 instr
->flags
&= ~IR3_INSTR_MARK
;
1086 ir3_clear_mark(struct ir3
*ir
)
1088 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
) {
1089 ir3_block_clear_mark(block
);
1093 /* note: this will destroy instr->depth, don't do it until after sched! */
1095 ir3_count_instructions(struct ir3
*ir
)
1098 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
) {
1099 block
->start_ip
= cnt
;
1100 block
->end_ip
= cnt
;
1101 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
1103 block
->end_ip
= instr
->ip
;
1110 ir3_lookup_array(struct ir3
*ir
, unsigned id
)
1112 list_for_each_entry (struct ir3_array
, arr
, &ir
->array_list
, node
)