2 * Copyright (c) 2012 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include "util/bitscan.h"
34 #include "util/ralloc.h"
35 #include "util/u_math.h"
37 #include "instr-a3xx.h"
38 #include "ir3_compiler.h"
40 /* simple allocator to carve allocations out of an up-front allocated heap,
41 * so that we can free everything easily in one shot.
43 void * ir3_alloc(struct ir3
*shader
, int sz
)
45 return rzalloc_size(shader
, sz
); /* TODO: don't use rzalloc */
48 struct ir3
* ir3_create(struct ir3_compiler
*compiler
, gl_shader_stage type
)
50 struct ir3
*shader
= rzalloc(NULL
, struct ir3
);
52 shader
->compiler
= compiler
;
55 list_inithead(&shader
->block_list
);
56 list_inithead(&shader
->array_list
);
61 void ir3_destroy(struct ir3
*shader
)
66 #define iassert(cond) do { \
72 #define iassert_type(reg, full) do { \
74 iassert(!((reg)->flags & IR3_REG_HALF)); \
76 iassert((reg)->flags & IR3_REG_HALF); \
79 static uint32_t reg(struct ir3_register
*reg
, struct ir3_info
*info
,
80 uint32_t repeat
, uint32_t valid_flags
)
82 reg_t val
= { .dummy32
= 0 };
84 if (reg
->flags
& ~valid_flags
) {
85 debug_printf("INVALID FLAGS: %x vs %x\n",
86 reg
->flags
, valid_flags
);
89 if (!(reg
->flags
& IR3_REG_R
))
92 if (reg
->flags
& IR3_REG_IMMED
) {
93 val
.iim_val
= reg
->iim_val
;
98 if (reg
->flags
& IR3_REG_RELATIV
) {
99 components
= reg
->size
;
100 val
.idummy10
= reg
->array
.offset
;
101 max
= (reg
->array
.offset
+ repeat
+ components
- 1);
103 components
= util_last_bit(reg
->wrmask
);
104 val
.comp
= reg
->num
& 0x3;
105 val
.num
= reg
->num
>> 2;
106 max
= (reg
->num
+ repeat
+ components
- 1);
109 if (reg
->flags
& IR3_REG_CONST
) {
110 info
->max_const
= MAX2(info
->max_const
, max
>> 2);
111 } else if (val
.num
== 63) {
112 /* ignore writes to dummy register r63.x */
113 } else if (max
< regid(48, 0)) {
114 if (reg
->flags
& IR3_REG_HALF
) {
115 if (info
->gpu_id
>= 600) {
116 /* starting w/ a6xx, half regs conflict with full regs: */
117 info
->max_reg
= MAX2(info
->max_reg
, max
>> 3);
119 info
->max_half_reg
= MAX2(info
->max_half_reg
, max
>> 2);
122 info
->max_reg
= MAX2(info
->max_reg
, max
>> 2);
130 static int emit_cat0(struct ir3_instruction
*instr
, void *ptr
,
131 struct ir3_info
*info
)
133 instr_cat0_t
*cat0
= ptr
;
135 if (info
->gpu_id
>= 500) {
136 cat0
->a5xx
.immed
= instr
->cat0
.immed
;
137 } else if (info
->gpu_id
>= 400) {
138 cat0
->a4xx
.immed
= instr
->cat0
.immed
;
140 cat0
->a3xx
.immed
= instr
->cat0
.immed
;
142 cat0
->repeat
= instr
->repeat
;
143 cat0
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
144 cat0
->inv
= instr
->cat0
.inv
;
145 cat0
->comp
= instr
->cat0
.comp
;
146 cat0
->opc
= instr
->opc
;
147 cat0
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
148 cat0
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
151 switch (instr
->opc
) {
164 static int emit_cat1(struct ir3_instruction
*instr
, void *ptr
,
165 struct ir3_info
*info
)
167 struct ir3_register
*dst
= instr
->regs
[0];
168 struct ir3_register
*src
= instr
->regs
[1];
169 instr_cat1_t
*cat1
= ptr
;
171 iassert(instr
->regs_count
== 2);
172 iassert_type(dst
, type_size(instr
->cat1
.dst_type
) == 32);
173 if (!(src
->flags
& IR3_REG_IMMED
))
174 iassert_type(src
, type_size(instr
->cat1
.src_type
) == 32);
176 if (src
->flags
& IR3_REG_IMMED
) {
177 cat1
->iim_val
= src
->iim_val
;
179 } else if (src
->flags
& IR3_REG_RELATIV
) {
180 cat1
->off
= reg(src
, info
, instr
->repeat
,
181 IR3_REG_R
| IR3_REG_CONST
| IR3_REG_HALF
| IR3_REG_RELATIV
);
183 cat1
->src_rel_c
= !!(src
->flags
& IR3_REG_CONST
);
185 cat1
->src
= reg(src
, info
, instr
->repeat
,
186 IR3_REG_R
| IR3_REG_CONST
| IR3_REG_HALF
);
187 cat1
->src_c
= !!(src
->flags
& IR3_REG_CONST
);
190 cat1
->dst
= reg(dst
, info
, instr
->repeat
,
191 IR3_REG_RELATIV
| IR3_REG_EVEN
|
192 IR3_REG_R
| IR3_REG_POS_INF
| IR3_REG_HALF
);
193 cat1
->repeat
= instr
->repeat
;
194 cat1
->src_r
= !!(src
->flags
& IR3_REG_R
);
195 cat1
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
196 cat1
->ul
= !!(instr
->flags
& IR3_INSTR_UL
);
197 cat1
->dst_type
= instr
->cat1
.dst_type
;
198 cat1
->dst_rel
= !!(dst
->flags
& IR3_REG_RELATIV
);
199 cat1
->src_type
= instr
->cat1
.src_type
;
200 cat1
->even
= !!(dst
->flags
& IR3_REG_EVEN
);
201 cat1
->pos_inf
= !!(dst
->flags
& IR3_REG_POS_INF
);
202 cat1
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
203 cat1
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
209 static int emit_cat2(struct ir3_instruction
*instr
, void *ptr
,
210 struct ir3_info
*info
)
212 struct ir3_register
*dst
= instr
->regs
[0];
213 struct ir3_register
*src1
= instr
->regs
[1];
214 struct ir3_register
*src2
= instr
->regs
[2];
215 instr_cat2_t
*cat2
= ptr
;
216 unsigned absneg
= ir3_cat2_absneg(instr
->opc
);
218 iassert((instr
->regs_count
== 2) || (instr
->regs_count
== 3));
221 iassert(!instr
->repeat
);
222 iassert(instr
->nop
<= 3);
224 cat2
->src1_r
= instr
->nop
& 0x1;
225 cat2
->src2_r
= (instr
->nop
>> 1) & 0x1;
227 cat2
->src1_r
= !!(src1
->flags
& IR3_REG_R
);
229 cat2
->src2_r
= !!(src2
->flags
& IR3_REG_R
);
232 if (src1
->flags
& IR3_REG_RELATIV
) {
233 iassert(src1
->array
.offset
< (1 << 10));
234 cat2
->rel1
.src1
= reg(src1
, info
, instr
->repeat
,
235 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_R
|
236 IR3_REG_HALF
| absneg
);
237 cat2
->rel1
.src1_c
= !!(src1
->flags
& IR3_REG_CONST
);
238 cat2
->rel1
.src1_rel
= 1;
239 } else if (src1
->flags
& IR3_REG_CONST
) {
240 iassert(src1
->num
< (1 << 12));
241 cat2
->c1
.src1
= reg(src1
, info
, instr
->repeat
,
242 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
|
246 iassert(src1
->num
< (1 << 11));
247 cat2
->src1
= reg(src1
, info
, instr
->repeat
,
248 IR3_REG_IMMED
| IR3_REG_R
| IR3_REG_HALF
|
251 cat2
->src1_im
= !!(src1
->flags
& IR3_REG_IMMED
);
252 cat2
->src1_neg
= !!(src1
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
253 cat2
->src1_abs
= !!(src1
->flags
& (IR3_REG_FABS
| IR3_REG_SABS
));
256 iassert((src2
->flags
& IR3_REG_IMMED
) ||
257 !((src1
->flags
^ src2
->flags
) & IR3_REG_HALF
));
259 if (src2
->flags
& IR3_REG_RELATIV
) {
260 iassert(src2
->array
.offset
< (1 << 10));
261 cat2
->rel2
.src2
= reg(src2
, info
, instr
->repeat
,
262 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_R
|
263 IR3_REG_HALF
| absneg
);
264 cat2
->rel2
.src2_c
= !!(src2
->flags
& IR3_REG_CONST
);
265 cat2
->rel2
.src2_rel
= 1;
266 } else if (src2
->flags
& IR3_REG_CONST
) {
267 iassert(src2
->num
< (1 << 12));
268 cat2
->c2
.src2
= reg(src2
, info
, instr
->repeat
,
269 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
|
273 iassert(src2
->num
< (1 << 11));
274 cat2
->src2
= reg(src2
, info
, instr
->repeat
,
275 IR3_REG_IMMED
| IR3_REG_R
| IR3_REG_HALF
|
279 cat2
->src2_im
= !!(src2
->flags
& IR3_REG_IMMED
);
280 cat2
->src2_neg
= !!(src2
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
281 cat2
->src2_abs
= !!(src2
->flags
& (IR3_REG_FABS
| IR3_REG_SABS
));
284 cat2
->dst
= reg(dst
, info
, instr
->repeat
,
285 IR3_REG_R
| IR3_REG_EI
| IR3_REG_HALF
);
286 cat2
->repeat
= instr
->repeat
;
287 cat2
->sat
= !!(instr
->flags
& IR3_INSTR_SAT
);
288 cat2
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
289 cat2
->ul
= !!(instr
->flags
& IR3_INSTR_UL
);
290 cat2
->dst_half
= !!((src1
->flags
^ dst
->flags
) & IR3_REG_HALF
);
291 cat2
->ei
= !!(dst
->flags
& IR3_REG_EI
);
292 cat2
->cond
= instr
->cat2
.condition
;
293 cat2
->full
= ! (src1
->flags
& IR3_REG_HALF
);
294 cat2
->opc
= instr
->opc
;
295 cat2
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
296 cat2
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
302 static int emit_cat3(struct ir3_instruction
*instr
, void *ptr
,
303 struct ir3_info
*info
)
305 struct ir3_register
*dst
= instr
->regs
[0];
306 struct ir3_register
*src1
= instr
->regs
[1];
307 struct ir3_register
*src2
= instr
->regs
[2];
308 struct ir3_register
*src3
= instr
->regs
[3];
309 unsigned absneg
= ir3_cat3_absneg(instr
->opc
);
310 instr_cat3_t
*cat3
= ptr
;
311 uint32_t src_flags
= 0;
313 switch (instr
->opc
) {
321 case OPC_SAD_S32
: // really??
322 src_flags
|= IR3_REG_HALF
;
328 iassert(instr
->regs_count
== 4);
329 iassert(!((src1
->flags
^ src_flags
) & IR3_REG_HALF
));
330 iassert(!((src2
->flags
^ src_flags
) & IR3_REG_HALF
));
331 iassert(!((src3
->flags
^ src_flags
) & IR3_REG_HALF
));
334 iassert(!instr
->repeat
);
335 iassert(instr
->nop
<= 3);
337 cat3
->src1_r
= instr
->nop
& 0x1;
338 cat3
->src2_r
= (instr
->nop
>> 1) & 0x1;
340 cat3
->src1_r
= !!(src1
->flags
& IR3_REG_R
);
341 cat3
->src2_r
= !!(src2
->flags
& IR3_REG_R
);
344 if (src1
->flags
& IR3_REG_RELATIV
) {
345 iassert(src1
->array
.offset
< (1 << 10));
346 cat3
->rel1
.src1
= reg(src1
, info
, instr
->repeat
,
347 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_R
|
348 IR3_REG_HALF
| absneg
);
349 cat3
->rel1
.src1_c
= !!(src1
->flags
& IR3_REG_CONST
);
350 cat3
->rel1
.src1_rel
= 1;
351 } else if (src1
->flags
& IR3_REG_CONST
) {
352 iassert(src1
->num
< (1 << 12));
353 cat3
->c1
.src1
= reg(src1
, info
, instr
->repeat
,
354 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
| absneg
);
357 iassert(src1
->num
< (1 << 11));
358 cat3
->src1
= reg(src1
, info
, instr
->repeat
,
359 IR3_REG_R
| IR3_REG_HALF
| absneg
);
362 cat3
->src1_neg
= !!(src1
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
364 cat3
->src2
= reg(src2
, info
, instr
->repeat
,
365 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
| absneg
);
366 cat3
->src2_c
= !!(src2
->flags
& IR3_REG_CONST
);
367 cat3
->src2_neg
= !!(src2
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
369 if (src3
->flags
& IR3_REG_RELATIV
) {
370 iassert(src3
->array
.offset
< (1 << 10));
371 cat3
->rel2
.src3
= reg(src3
, info
, instr
->repeat
,
372 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_R
|
373 IR3_REG_HALF
| absneg
);
374 cat3
->rel2
.src3_c
= !!(src3
->flags
& IR3_REG_CONST
);
375 cat3
->rel2
.src3_rel
= 1;
376 } else if (src3
->flags
& IR3_REG_CONST
) {
377 iassert(src3
->num
< (1 << 12));
378 cat3
->c2
.src3
= reg(src3
, info
, instr
->repeat
,
379 IR3_REG_CONST
| IR3_REG_R
| IR3_REG_HALF
| absneg
);
382 iassert(src3
->num
< (1 << 11));
383 cat3
->src3
= reg(src3
, info
, instr
->repeat
,
384 IR3_REG_R
| IR3_REG_HALF
| absneg
);
387 cat3
->src3_neg
= !!(src3
->flags
& (IR3_REG_FNEG
| IR3_REG_SNEG
| IR3_REG_BNOT
));
388 cat3
->src3_r
= !!(src3
->flags
& IR3_REG_R
);
390 cat3
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
391 cat3
->repeat
= instr
->repeat
;
392 cat3
->sat
= !!(instr
->flags
& IR3_INSTR_SAT
);
393 cat3
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
394 cat3
->ul
= !!(instr
->flags
& IR3_INSTR_UL
);
395 cat3
->dst_half
= !!((src_flags
^ dst
->flags
) & IR3_REG_HALF
);
396 cat3
->opc
= instr
->opc
;
397 cat3
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
398 cat3
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
404 static int emit_cat4(struct ir3_instruction
*instr
, void *ptr
,
405 struct ir3_info
*info
)
407 struct ir3_register
*dst
= instr
->regs
[0];
408 struct ir3_register
*src
= instr
->regs
[1];
409 instr_cat4_t
*cat4
= ptr
;
411 iassert(instr
->regs_count
== 2);
413 if (src
->flags
& IR3_REG_RELATIV
) {
414 iassert(src
->array
.offset
< (1 << 10));
415 cat4
->rel
.src
= reg(src
, info
, instr
->repeat
,
416 IR3_REG_RELATIV
| IR3_REG_CONST
| IR3_REG_FNEG
|
417 IR3_REG_FABS
| IR3_REG_R
| IR3_REG_HALF
);
418 cat4
->rel
.src_c
= !!(src
->flags
& IR3_REG_CONST
);
419 cat4
->rel
.src_rel
= 1;
420 } else if (src
->flags
& IR3_REG_CONST
) {
421 iassert(src
->num
< (1 << 12));
422 cat4
->c
.src
= reg(src
, info
, instr
->repeat
,
423 IR3_REG_CONST
| IR3_REG_FNEG
| IR3_REG_FABS
|
424 IR3_REG_R
| IR3_REG_HALF
);
427 iassert(src
->num
< (1 << 11));
428 cat4
->src
= reg(src
, info
, instr
->repeat
,
429 IR3_REG_IMMED
| IR3_REG_FNEG
| IR3_REG_FABS
|
430 IR3_REG_R
| IR3_REG_HALF
);
433 cat4
->src_im
= !!(src
->flags
& IR3_REG_IMMED
);
434 cat4
->src_neg
= !!(src
->flags
& IR3_REG_FNEG
);
435 cat4
->src_abs
= !!(src
->flags
& IR3_REG_FABS
);
436 cat4
->src_r
= !!(src
->flags
& IR3_REG_R
);
438 cat4
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
439 cat4
->repeat
= instr
->repeat
;
440 cat4
->sat
= !!(instr
->flags
& IR3_INSTR_SAT
);
441 cat4
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
442 cat4
->ul
= !!(instr
->flags
& IR3_INSTR_UL
);
443 cat4
->dst_half
= !!((src
->flags
^ dst
->flags
) & IR3_REG_HALF
);
444 cat4
->full
= ! (src
->flags
& IR3_REG_HALF
);
445 cat4
->opc
= instr
->opc
;
446 cat4
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
447 cat4
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
453 static int emit_cat5(struct ir3_instruction
*instr
, void *ptr
,
454 struct ir3_info
*info
)
456 struct ir3_register
*dst
= instr
->regs
[0];
457 /* To simplify things when there could be zero, one, or two args other
458 * than tex/sampler idx, we use the first src reg in the ir to hold
461 struct ir3_register
*src1
;
462 struct ir3_register
*src2
;
463 instr_cat5_t
*cat5
= ptr
;
465 iassert((instr
->regs_count
== 2) ||
466 (instr
->regs_count
== 3) || (instr
->regs_count
== 4));
468 switch (instr
->opc
) {
475 iassert((instr
->flags
& IR3_INSTR_S2EN
) == 0);
476 src1
= instr
->regs
[1];
477 src2
= instr
->regs_count
> 2 ? instr
->regs
[2] : NULL
;
480 src1
= instr
->regs
[2];
481 src2
= instr
->regs_count
> 3 ? instr
->regs
[3] : NULL
;
485 assume(src1
|| !src2
);
488 cat5
->full
= ! (src1
->flags
& IR3_REG_HALF
);
489 cat5
->src1
= reg(src1
, info
, instr
->repeat
, IR3_REG_HALF
);
492 if (instr
->flags
& IR3_INSTR_S2EN
) {
493 struct ir3_register
*samp_tex
= instr
->regs
[1];
495 iassert(!((src1
->flags
^ src2
->flags
) & IR3_REG_HALF
));
496 cat5
->s2en
.src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_HALF
);
498 iassert(samp_tex
->flags
& IR3_REG_HALF
);
499 cat5
->s2en
.src3
= reg(samp_tex
, info
, instr
->repeat
, IR3_REG_HALF
);
500 iassert(!(instr
->cat5
.samp
| instr
->cat5
.tex
));
503 iassert(!((src1
->flags
^ src2
->flags
) & IR3_REG_HALF
));
504 cat5
->norm
.src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_HALF
);
506 cat5
->norm
.samp
= instr
->cat5
.samp
;
507 cat5
->norm
.tex
= instr
->cat5
.tex
;
510 cat5
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
511 cat5
->wrmask
= dst
->wrmask
;
512 cat5
->type
= instr
->cat5
.type
;
513 cat5
->is_3d
= !!(instr
->flags
& IR3_INSTR_3D
);
514 cat5
->is_a
= !!(instr
->flags
& IR3_INSTR_A
);
515 cat5
->is_s
= !!(instr
->flags
& IR3_INSTR_S
);
516 cat5
->is_s2en
= !!(instr
->flags
& IR3_INSTR_S2EN
);
517 cat5
->is_o
= !!(instr
->flags
& IR3_INSTR_O
);
518 cat5
->is_p
= !!(instr
->flags
& IR3_INSTR_P
);
519 cat5
->opc
= instr
->opc
;
520 cat5
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
521 cat5
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
527 static int emit_cat6_a6xx(struct ir3_instruction
*instr
, void *ptr
,
528 struct ir3_info
*info
)
530 struct ir3_register
*src1
, *src2
;
531 instr_cat6_a6xx_t
*cat6
= ptr
;
532 bool has_dest
= (instr
->opc
== OPC_LDIB
);
534 /* first reg should be SSBO binding point: */
535 iassert(instr
->regs
[1]->flags
& IR3_REG_IMMED
);
537 src1
= instr
->regs
[2];
540 /* the src2 field in the instruction is actually the destination
541 * register for load instructions:
543 src2
= instr
->regs
[0];
545 src2
= instr
->regs
[3];
548 cat6
->type
= instr
->cat6
.type
;
549 cat6
->d
= instr
->cat6
.d
- 1;
550 cat6
->typed
= instr
->cat6
.typed
;
551 cat6
->type_size
= instr
->cat6
.iim_val
- 1;
552 cat6
->opc
= instr
->opc
;
553 cat6
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
554 cat6
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
557 cat6
->src1
= reg(src1
, info
, instr
->repeat
, 0);
558 cat6
->src2
= reg(src2
, info
, instr
->repeat
, 0);
559 cat6
->ssbo
= instr
->regs
[1]->iim_val
;
561 switch (instr
->opc
) {
564 case OPC_ATOMIC_XCHG
:
567 case OPC_ATOMIC_CMPXCHG
:
603 static int emit_cat6(struct ir3_instruction
*instr
, void *ptr
,
604 struct ir3_info
*info
)
606 struct ir3_register
*dst
, *src1
, *src2
;
607 instr_cat6_t
*cat6
= ptr
;
609 /* In a6xx we start using a new instruction encoding for some of
610 * these instructions:
612 if (info
->gpu_id
>= 600) {
613 switch (instr
->opc
) {
616 case OPC_ATOMIC_XCHG
:
619 case OPC_ATOMIC_CMPXCHG
:
625 /* The shared variants of these still use the old encoding: */
626 if (!(instr
->flags
& IR3_INSTR_G
))
632 return emit_cat6_a6xx(instr
, ptr
, info
);
638 bool type_full
= type_size(instr
->cat6
.type
) == 32;
640 cat6
->type
= instr
->cat6
.type
;
641 cat6
->opc
= instr
->opc
;
642 cat6
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
643 cat6
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
644 cat6
->g
= !!(instr
->flags
& IR3_INSTR_G
);
647 switch (instr
->opc
) {
650 iassert_type(instr
->regs
[0], type_full
); /* dst */
651 iassert_type(instr
->regs
[1], type_full
); /* src1 */
655 iassert_type(instr
->regs
[0], true); /* dst */
656 iassert_type(instr
->regs
[1], true); /* src1 */
663 /* no dst, so regs[0] is dummy */
664 iassert_type(instr
->regs
[1], true); /* dst */
665 iassert_type(instr
->regs
[2], type_full
); /* src1 */
666 iassert_type(instr
->regs
[3], true); /* src2 */
669 iassert_type(instr
->regs
[0], type_full
); /* dst */
670 iassert_type(instr
->regs
[1], true); /* src1 */
671 if (instr
->regs_count
> 2)
672 iassert_type(instr
->regs
[2], true); /* src1 */
676 /* the "dst" for a store instruction is (from the perspective
677 * of data flow in the shader, ie. register use/def, etc) in
678 * fact a register that is read by the instruction, rather
681 if (is_store(instr
)) {
682 iassert(instr
->regs_count
>= 3);
684 dst
= instr
->regs
[1];
685 src1
= instr
->regs
[2];
686 src2
= (instr
->regs_count
>= 4) ? instr
->regs
[3] : NULL
;
688 iassert(instr
->regs_count
>= 2);
690 dst
= instr
->regs
[0];
691 src1
= instr
->regs
[1];
692 src2
= (instr
->regs_count
>= 3) ? instr
->regs
[2] : NULL
;
695 /* TODO we need a more comprehensive list about which instructions
696 * can be encoded which way. Or possibly use IR3_INSTR_0 flag to
697 * indicate to use the src_off encoding even if offset is zero
698 * (but then what to do about dst_off?)
700 if (is_atomic(instr
->opc
)) {
701 instr_cat6ldgb_t
*ldgb
= ptr
;
703 /* maybe these two bits both determine the instruction encoding? */
704 cat6
->src_off
= false;
706 ldgb
->d
= instr
->cat6
.d
- 1;
707 ldgb
->typed
= instr
->cat6
.typed
;
708 ldgb
->type_size
= instr
->cat6
.iim_val
- 1;
710 ldgb
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
713 struct ir3_register
*src3
= instr
->regs
[3];
714 struct ir3_register
*src4
= instr
->regs
[4];
716 /* first src is src_ssbo: */
717 iassert(src1
->flags
& IR3_REG_IMMED
);
718 ldgb
->src_ssbo
= src1
->uim_val
;
720 ldgb
->src1
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
721 ldgb
->src1_im
= !!(src2
->flags
& IR3_REG_IMMED
);
722 ldgb
->src2
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
723 ldgb
->src2_im
= !!(src3
->flags
& IR3_REG_IMMED
);
725 ldgb
->src3
= reg(src4
, info
, instr
->repeat
, 0);
729 ldgb
->src1
= reg(src1
, info
, instr
->repeat
, IR3_REG_IMMED
);
730 ldgb
->src1_im
= !!(src1
->flags
& IR3_REG_IMMED
);
731 ldgb
->src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
732 ldgb
->src2_im
= !!(src2
->flags
& IR3_REG_IMMED
);
738 } else if (instr
->opc
== OPC_LDGB
) {
739 struct ir3_register
*src3
= instr
->regs
[3];
740 instr_cat6ldgb_t
*ldgb
= ptr
;
742 /* maybe these two bits both determine the instruction encoding? */
743 cat6
->src_off
= false;
745 ldgb
->d
= instr
->cat6
.d
- 1;
746 ldgb
->typed
= instr
->cat6
.typed
;
747 ldgb
->type_size
= instr
->cat6
.iim_val
- 1;
749 ldgb
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
751 /* first src is src_ssbo: */
752 iassert(src1
->flags
& IR3_REG_IMMED
);
753 ldgb
->src_ssbo
= src1
->uim_val
;
755 /* then next two are src1/src2: */
756 ldgb
->src1
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
757 ldgb
->src1_im
= !!(src2
->flags
& IR3_REG_IMMED
);
758 ldgb
->src2
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
759 ldgb
->src2_im
= !!(src3
->flags
& IR3_REG_IMMED
);
765 } else if (instr
->opc
== OPC_RESINFO
) {
766 instr_cat6ldgb_t
*ldgb
= ptr
;
768 ldgb
->d
= instr
->cat6
.d
- 1;
770 ldgb
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
772 /* first src is src_ssbo: */
773 iassert(src1
->flags
& IR3_REG_IMMED
);
774 ldgb
->src_ssbo
= src1
->uim_val
;
777 } else if ((instr
->opc
== OPC_STGB
) || (instr
->opc
== OPC_STIB
)) {
778 struct ir3_register
*src3
= instr
->regs
[4];
779 instr_cat6stgb_t
*stgb
= ptr
;
781 /* maybe these two bits both determine the instruction encoding? */
782 cat6
->src_off
= true;
785 stgb
->d
= instr
->cat6
.d
- 1;
786 stgb
->typed
= instr
->cat6
.typed
;
787 stgb
->type_size
= instr
->cat6
.iim_val
- 1;
789 /* first src is dst_ssbo: */
790 iassert(dst
->flags
& IR3_REG_IMMED
);
791 stgb
->dst_ssbo
= dst
->uim_val
;
793 /* then src1/src2/src3: */
794 stgb
->src1
= reg(src1
, info
, instr
->repeat
, 0);
795 stgb
->src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
796 stgb
->src2_im
= !!(src2
->flags
& IR3_REG_IMMED
);
797 stgb
->src3
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
798 stgb
->src3_im
= !!(src3
->flags
& IR3_REG_IMMED
);
801 } else if (instr
->cat6
.src_offset
|| (instr
->opc
== OPC_LDG
) ||
802 (instr
->opc
== OPC_LDL
) || (instr
->opc
== OPC_LDLW
)) {
803 struct ir3_register
*src3
= instr
->regs
[3];
804 instr_cat6a_t
*cat6a
= ptr
;
806 cat6
->src_off
= true;
808 if (instr
->opc
== OPC_LDG
) {
809 /* For LDG src1 can not be immediate, so src1_imm is redundant and
810 * instead used to signal whether (when true) 'off' is a 32 bit
811 * register or an immediate offset.
813 cat6a
->src1
= reg(src1
, info
, instr
->repeat
, 0);
814 cat6a
->src1_im
= !(src3
->flags
& IR3_REG_IMMED
);
815 cat6a
->off
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
817 cat6a
->src1
= reg(src1
, info
, instr
->repeat
, IR3_REG_IMMED
);
818 cat6a
->src1_im
= !!(src1
->flags
& IR3_REG_IMMED
);
819 cat6a
->off
= reg(src3
, info
, instr
->repeat
, IR3_REG_IMMED
);
820 iassert(src3
->flags
& IR3_REG_IMMED
);
824 cat6a
->src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
825 cat6a
->src2_im
= true;
827 instr_cat6b_t
*cat6b
= ptr
;
829 cat6
->src_off
= false;
831 cat6b
->src1
= reg(src1
, info
, instr
->repeat
, IR3_REG_IMMED
| IR3_REG_HALF
);
832 cat6b
->src1_im
= !!(src1
->flags
& IR3_REG_IMMED
);
834 cat6b
->src2
= reg(src2
, info
, instr
->repeat
, IR3_REG_IMMED
);
835 cat6b
->src2_im
= !!(src2
->flags
& IR3_REG_IMMED
);
839 if (instr
->cat6
.dst_offset
|| (instr
->opc
== OPC_STG
) ||
840 (instr
->opc
== OPC_STL
) || (instr
->opc
== OPC_STLW
)) {
841 instr_cat6c_t
*cat6c
= ptr
;
842 cat6
->dst_off
= true;
843 cat6c
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
845 if (instr
->flags
& IR3_INSTR_G
) {
846 struct ir3_register
*src3
= instr
->regs
[4];
847 cat6c
->off
= reg(src3
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
848 if (src3
->flags
& IR3_REG_IMMED
) {
849 /* Immediate offsets are in bytes... */
854 cat6c
->off
= instr
->cat6
.dst_offset
;
857 instr_cat6d_t
*cat6d
= ptr
;
858 cat6
->dst_off
= false;
859 cat6d
->dst
= reg(dst
, info
, instr
->repeat
, IR3_REG_R
| IR3_REG_HALF
);
865 static int emit_cat7(struct ir3_instruction
*instr
, void *ptr
,
866 struct ir3_info
*info
)
868 instr_cat7_t
*cat7
= ptr
;
870 cat7
->ss
= !!(instr
->flags
& IR3_INSTR_SS
);
871 cat7
->w
= instr
->cat7
.w
;
872 cat7
->r
= instr
->cat7
.r
;
873 cat7
->l
= instr
->cat7
.l
;
874 cat7
->g
= instr
->cat7
.g
;
875 cat7
->opc
= instr
->opc
;
876 cat7
->jmp_tgt
= !!(instr
->flags
& IR3_INSTR_JP
);
877 cat7
->sync
= !!(instr
->flags
& IR3_INSTR_SY
);
883 static int (*emit
[])(struct ir3_instruction
*instr
, void *ptr
,
884 struct ir3_info
*info
) = {
885 emit_cat0
, emit_cat1
, emit_cat2
, emit_cat3
, emit_cat4
, emit_cat5
, emit_cat6
,
889 void * ir3_assemble(struct ir3
*shader
, struct ir3_info
*info
,
892 uint32_t *ptr
, *dwords
;
894 info
->gpu_id
= gpu_id
;
896 info
->max_half_reg
= -1;
897 info
->max_const
= -1;
898 info
->instrs_count
= 0;
899 info
->sizedwords
= 0;
900 info
->ss
= info
->sy
= 0;
902 foreach_block (block
, &shader
->block_list
) {
903 foreach_instr (instr
, &block
->instr_list
) {
904 info
->sizedwords
+= 2;
908 /* need an integer number of instruction "groups" (sets of 16
909 * instructions on a4xx or sets of 4 instructions on a3xx),
910 * so pad out w/ NOPs if needed: (NOTE each instruction is 64bits)
913 info
->sizedwords
= align(info
->sizedwords
, 16 * 2);
915 info
->sizedwords
= align(info
->sizedwords
, 4 * 2);
918 ptr
= dwords
= calloc(4, info
->sizedwords
);
920 foreach_block (block
, &shader
->block_list
) {
921 foreach_instr (instr
, &block
->instr_list
) {
922 int ret
= emit
[opc_cat(instr
->opc
)](instr
, dwords
, info
);
926 if ((instr
->opc
== OPC_BARY_F
) && (instr
->regs
[0]->flags
& IR3_REG_EI
))
927 info
->last_baryf
= info
->instrs_count
;
929 info
->instrs_count
+= 1 + instr
->repeat
+ instr
->nop
;
930 info
->nops_count
+= instr
->nop
;
931 if (instr
->opc
== OPC_NOP
)
932 info
->nops_count
+= 1 + instr
->repeat
;
935 if (instr
->flags
& IR3_INSTR_SS
)
938 if (instr
->flags
& IR3_INSTR_SY
)
950 static struct ir3_register
* reg_create(struct ir3
*shader
,
953 struct ir3_register
*reg
=
954 ir3_alloc(shader
, sizeof(struct ir3_register
));
958 if (shader
->compiler
->gpu_id
>= 600)
963 static void insert_instr(struct ir3_block
*block
,
964 struct ir3_instruction
*instr
)
966 struct ir3
*shader
= block
->shader
;
968 instr
->serialno
= ++shader
->instr_count
;
970 list_addtail(&instr
->node
, &block
->instr_list
);
973 array_insert(shader
, shader
->baryfs
, instr
);
976 struct ir3_block
* ir3_block_create(struct ir3
*shader
)
978 struct ir3_block
*block
= ir3_alloc(shader
, sizeof(*block
));
980 block
->serialno
= ++shader
->block_count
;
982 block
->shader
= shader
;
983 list_inithead(&block
->node
);
984 list_inithead(&block
->instr_list
);
988 static struct ir3_instruction
*instr_create(struct ir3_block
*block
, int nreg
)
990 struct ir3_instruction
*instr
;
991 unsigned sz
= sizeof(*instr
) + (nreg
* sizeof(instr
->regs
[0]));
992 char *ptr
= ir3_alloc(block
->shader
, sz
);
994 instr
= (struct ir3_instruction
*)ptr
;
995 ptr
+= sizeof(*instr
);
996 instr
->regs
= (struct ir3_register
**)ptr
;
999 instr
->regs_max
= nreg
;
1005 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
1006 opc_t opc
, int nreg
)
1008 struct ir3_instruction
*instr
= instr_create(block
, nreg
);
1009 instr
->block
= block
;
1011 insert_instr(block
, instr
);
1015 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
)
1017 /* NOTE: we could be slightly more clever, at least for non-meta,
1018 * and choose # of regs based on category.
1020 return ir3_instr_create2(block
, opc
, 4);
1023 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
)
1025 struct ir3_instruction
*new_instr
= instr_create(instr
->block
,
1027 struct ir3_register
**regs
;
1030 regs
= new_instr
->regs
;
1031 *new_instr
= *instr
;
1032 new_instr
->regs
= regs
;
1034 insert_instr(instr
->block
, new_instr
);
1036 /* clone registers: */
1037 new_instr
->regs_count
= 0;
1038 for (i
= 0; i
< instr
->regs_count
; i
++) {
1039 struct ir3_register
*reg
= instr
->regs
[i
];
1040 struct ir3_register
*new_reg
=
1041 ir3_reg_create(new_instr
, reg
->num
, reg
->flags
);
1048 /* Add a false dependency to instruction, to ensure it is scheduled first: */
1049 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
)
1051 array_insert(instr
, instr
->deps
, dep
);
1054 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
1057 struct ir3
*shader
= instr
->block
->shader
;
1058 struct ir3_register
*reg
= reg_create(shader
, num
, flags
);
1060 debug_assert(instr
->regs_count
< instr
->regs_max
);
1062 instr
->regs
[instr
->regs_count
++] = reg
;
1066 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
1067 struct ir3_register
*reg
)
1069 struct ir3_register
*new_reg
= reg_create(shader
, 0, 0);
1075 ir3_instr_set_address(struct ir3_instruction
*instr
,
1076 struct ir3_instruction
*addr
)
1078 if (instr
->address
!= addr
) {
1079 struct ir3
*ir
= instr
->block
->shader
;
1081 debug_assert(!instr
->address
);
1082 debug_assert(instr
->block
== addr
->block
);
1084 instr
->address
= addr
;
1085 array_insert(ir
, ir
->indirects
, instr
);
1090 ir3_block_clear_mark(struct ir3_block
*block
)
1092 foreach_instr (instr
, &block
->instr_list
)
1093 instr
->flags
&= ~IR3_INSTR_MARK
;
1097 ir3_clear_mark(struct ir3
*ir
)
1099 foreach_block (block
, &ir
->block_list
) {
1100 ir3_block_clear_mark(block
);
1104 /* note: this will destroy instr->depth, don't do it until after sched! */
1106 ir3_count_instructions(struct ir3
*ir
)
1109 foreach_block (block
, &ir
->block_list
) {
1110 block
->start_ip
= cnt
;
1111 block
->end_ip
= cnt
;
1112 foreach_instr (instr
, &block
->instr_list
) {
1114 block
->end_ip
= instr
->ip
;
1121 ir3_lookup_array(struct ir3
*ir
, unsigned id
)
1123 foreach_array (arr
, &ir
->array_list
)