2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "compiler/shader_enums.h"
32 #include "util/bitscan.h"
33 #include "util/list.h"
35 #include "util/u_debug.h"
37 #include "instr-a3xx.h"
39 /* low level intermediate representation of an adreno shader program */
43 struct ir3_instruction
;
49 uint16_t instrs_count
; /* expanded to account for rpt's */
50 uint16_t nops_count
; /* # of nop instructions, including nopN */
53 /* NOTE: max_reg, etc, does not include registers not touched
54 * by the shader (ie. vertex fetched via VFD_DECODE but not
57 int8_t max_reg
; /* highest GPR # used by shader */
61 /* number of sync bits: */
64 /* estimate of number of cycles stalled on (ss) */
67 uint16_t last_baryf
; /* instruction # of last varying fetch */
72 IR3_REG_CONST
= 0x001,
73 IR3_REG_IMMED
= 0x002,
75 /* high registers are used for some things in compute shaders,
76 * for example. Seems to be for things that are global to all
77 * threads in a wave, so possibly these are global/shared by
78 * all the threads in the wave?
81 IR3_REG_RELATIV
= 0x010,
83 /* Most instructions, it seems, can do float abs/neg but not
84 * integer. The CP pass needs to know what is intended (int or
85 * float) in order to do the right thing. For this reason the
86 * abs/neg flags are split out into float and int variants. In
87 * addition, .b (bitwise) operations, the negate is actually a
88 * bitwise not, so split that out into a new flag to make it
97 IR3_REG_POS_INF
= 0x1000,
98 /* (ei) flag, end-input? Set on last bary, presumably to signal
99 * that the shader needs no more input:
102 /* meta-flags, for intermediate stages of IR, ie.
103 * before register assignment is done:
105 IR3_REG_SSA
= 0x4000, /* 'instr' is ptr to assigning instr */
106 IR3_REG_ARRAY
= 0x8000,
110 /* used for cat5 instructions, but also for internal/IR level
111 * tracking of what registers are read/written by an instruction.
112 * wrmask may be a bad name since it is used to represent both
113 * src and dst that touch multiple adjacent registers.
115 unsigned wrmask
: 16; /* up to vec16 */
117 /* for relative addressing, 32bits for array size is too small,
118 * but otoh we don't need to deal with disjoint sets, so instead
119 * use a simple size field (number of scalar components).
121 * Note the size field isn't important for relative const (since
122 * we don't have to do register allocation for constants).
126 bool merged
: 1; /* half-regs conflict with full regs (ie >= a6xx) */
129 * the component is in the low two bits of the reg #, so
130 * rN.x becomes: (N << 2) | x
145 /* For IR3_REG_SSA, src registers contain ptr back to assigning
148 * For IR3_REG_ARRAY, the pointer is back to the last dependent
149 * array access (although the net effect is the same, it points
150 * back to a previous instruction that we depend on).
152 struct ir3_instruction
*instr
;
156 * Stupid/simple growable array implementation:
158 #define DECLARE_ARRAY(type, name) \
159 unsigned name ## _count, name ## _sz; \
162 #define array_insert(ctx, arr, val) do { \
163 if (arr ## _count == arr ## _sz) { \
164 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
165 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
167 arr[arr ##_count++] = val; \
170 struct ir3_instruction
{
171 struct ir3_block
*block
;
174 /* (sy) flag is set on first instruction, and after sample
175 * instructions (probably just on RAW hazard).
177 IR3_INSTR_SY
= 0x001,
178 /* (ss) flag is set on first instruction, and first instruction
179 * to depend on the result of "long" instructions (RAW hazard):
181 * rcp, rsq, log2, exp2, sin, cos, sqrt
183 * It seems to synchronize until all in-flight instructions are
184 * completed, for example:
187 * add.f hr2.z, (neg)hr2.z, hc0.y
188 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
191 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
193 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
194 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
195 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
197 * The last mul.f does not have (ss) set, presumably because the
198 * (ss) on the previous instruction does the job.
200 * The blob driver also seems to set it on WAR hazards, although
201 * not really clear if this is needed or just blob compiler being
202 * sloppy. So far I haven't found a case where removing the (ss)
203 * causes problems for WAR hazard, but I could just be getting
207 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
210 IR3_INSTR_SS
= 0x002,
211 /* (jp) flag is set on jump targets:
213 IR3_INSTR_JP
= 0x004,
214 IR3_INSTR_UL
= 0x008,
215 IR3_INSTR_3D
= 0x010,
220 IR3_INSTR_S2EN
= 0x200,
222 IR3_INSTR_SAT
= 0x800,
223 /* (cat5/cat6) Bindless */
224 IR3_INSTR_B
= 0x1000,
225 /* (cat5-only) Get some parts of the encoding from a1.x */
226 IR3_INSTR_A1EN
= 0x2000,
227 /* meta-flags, for intermediate stages of IR, ie.
228 * before register assignment is done:
230 IR3_INSTR_MARK
= 0x4000,
231 IR3_INSTR_UNUSED
= 0x8000,
239 struct ir3_register
**regs
;
245 struct ir3_block
*target
;
248 type_t src_type
, dst_type
;
262 unsigned tex_base
: 3;
269 int iim_val
: 3; /* for ldgb/stgb, # of components */
270 unsigned d
: 3; /* for ldc, component offset */
275 unsigned w
: 1; /* write */
276 unsigned r
: 1; /* read */
277 unsigned l
: 1; /* local */
278 unsigned g
: 1; /* global */
280 /* for meta-instructions, just used to hold extra data
281 * before instruction scheduling, etc
284 int off
; /* component/offset */
287 /* for output collects, this maps back to the entry in the
288 * ir3_shader_variant::outputs table.
294 unsigned input_offset
;
295 unsigned samp_base
: 3;
296 unsigned tex_base
: 3;
299 /* maps back to entry in ir3_shader_variant::inputs table: */
301 /* for sysvals, identifies the sysval type. Mostly so we can
302 * identify the special cases where a sysval should not be DCE'd
303 * (currently, just pre-fs texture fetch)
305 gl_system_value sysval
;
309 /* When we get to the RA stage, we need instruction's position/name: */
313 /* used for per-pass extra instruction data.
315 * TODO we should remove the per-pass data like this and 'use_count'
316 * and do something similar to what RA does w/ ir3_ra_instr_data..
317 * ie. use the ir3_count_instructions pass, and then use instr->ip
318 * to index into a table of pass-private data.
323 * Valid if pass calls ir3_find_ssa_uses().. see foreach_ssa_use()
327 int sun
; /* Sethi–Ullman number, used by sched */
328 int use_count
; /* currently just updated/used by cp */
330 /* Used during CP and RA stages. For collect and shader inputs/
331 * outputs where we need a sequence of consecutive registers,
332 * keep track of each src instructions left (ie 'n-1') and right
333 * (ie 'n+1') neighbor. The front-end must insert enough mov's
334 * to ensure that each instruction has at most one left and at
335 * most one right neighbor. During the copy-propagation pass,
336 * we only remove mov's when we can preserve this constraint.
337 * And during the RA stage, we use the neighbor information to
338 * allocate a block of registers in one shot.
340 * TODO: maybe just add something like:
341 * struct ir3_instruction_ref {
342 * struct ir3_instruction *instr;
346 * Or can we get away without the refcnt stuff? It seems like
347 * it should be overkill.. the problem is if, potentially after
348 * already eliminating some mov's, if you have a single mov that
349 * needs to be grouped with it's neighbors in two different
350 * places (ex. shader output and a collect).
353 struct ir3_instruction
*left
, *right
;
354 uint16_t left_cnt
, right_cnt
;
357 /* an instruction can reference at most one address register amongst
358 * it's src/dst registers. Beyond that, you need to insert mov's.
360 * NOTE: do not write this directly, use ir3_instr_set_address()
362 struct ir3_instruction
*address
;
364 /* Tracking for additional dependent instructions. Used to handle
365 * barriers, WAR hazards for arrays/SSBOs/etc.
367 DECLARE_ARRAY(struct ir3_instruction
*, deps
);
370 * From PoV of instruction scheduling, not execution (ie. ignores global/
371 * local distinction):
372 * shared image atomic SSBO everything
373 * barrier()/ - R/W R/W R/W R/W X
374 * groupMemoryBarrier()
375 * memoryBarrier() - R/W R/W
376 * (but only images declared coherent?)
377 * memoryBarrierAtomic() - R/W
378 * memoryBarrierBuffer() - R/W
379 * memoryBarrierImage() - R/W
380 * memoryBarrierShared() - R/W
382 * TODO I think for SSBO/image/shared, in cases where we can determine
383 * which variable is accessed, we don't need to care about accesses to
384 * different variables (unless declared coherent??)
387 IR3_BARRIER_EVERYTHING
= 1 << 0,
388 IR3_BARRIER_SHARED_R
= 1 << 1,
389 IR3_BARRIER_SHARED_W
= 1 << 2,
390 IR3_BARRIER_IMAGE_R
= 1 << 3,
391 IR3_BARRIER_IMAGE_W
= 1 << 4,
392 IR3_BARRIER_BUFFER_R
= 1 << 5,
393 IR3_BARRIER_BUFFER_W
= 1 << 6,
394 IR3_BARRIER_ARRAY_R
= 1 << 7,
395 IR3_BARRIER_ARRAY_W
= 1 << 8,
396 } barrier_class
, barrier_conflict
;
398 /* Entry in ir3_block's instruction list: */
399 struct list_head node
;
405 // TODO only computerator/assembler:
409 static inline struct ir3_instruction
*
410 ir3_neighbor_first(struct ir3_instruction
*instr
)
413 while (instr
->cp
.left
) {
414 instr
= instr
->cp
.left
;
415 if (++cnt
> 0xffff) {
423 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
427 debug_assert(!instr
->cp
.left
);
429 while (instr
->cp
.right
) {
431 instr
= instr
->cp
.right
;
442 struct ir3_compiler
*compiler
;
443 gl_shader_stage type
;
445 DECLARE_ARRAY(struct ir3_instruction
*, inputs
);
446 DECLARE_ARRAY(struct ir3_instruction
*, outputs
);
448 /* Track bary.f (and ldlv) instructions.. this is needed in
449 * scheduling to ensure that all varying fetches happen before
450 * any potential kill instructions. The hw gets grumpy if all
451 * threads in a group are killed before the last bary.f gets
452 * a chance to signal end of input (ei).
454 DECLARE_ARRAY(struct ir3_instruction
*, baryfs
);
456 /* Track all indirect instructions (read and write). To avoid
457 * deadlock scenario where an address register gets scheduled,
458 * but other dependent src instructions cannot be scheduled due
459 * to dependency on a *different* address register value, the
460 * scheduler needs to ensure that all dependencies other than
461 * the instruction other than the address register are scheduled
462 * before the one that writes the address register. Having a
463 * convenient list of instructions that reference some address
464 * register simplifies this.
466 DECLARE_ARRAY(struct ir3_instruction
*, a0_users
);
469 DECLARE_ARRAY(struct ir3_instruction
*, a1_users
);
471 /* and same for instructions that consume predicate register: */
472 DECLARE_ARRAY(struct ir3_instruction
*, predicates
);
474 /* Track texture sample instructions which need texture state
475 * patched in (for astc-srgb workaround):
477 DECLARE_ARRAY(struct ir3_instruction
*, astc_srgb
);
479 /* List of blocks: */
480 struct list_head block_list
;
482 /* List of ir3_array's: */
483 struct list_head array_list
;
485 unsigned max_sun
; /* max Sethi–Ullman number */
488 unsigned block_count
, instr_count
;
493 struct list_head node
;
497 struct nir_register
*r
;
499 /* To avoid array write's from getting DCE'd, keep track of the
500 * most recent write. Any array access depends on the most
501 * recent write. This way, nothing depends on writes after the
502 * last read. But all the writes that happen before that have
503 * something depending on them
505 struct ir3_instruction
*last_write
;
507 /* extra stuff used in RA pass: */
508 unsigned base
; /* base vreg name */
509 unsigned reg
; /* base physical reg */
510 uint16_t start_ip
, end_ip
;
512 /* Indicates if half-precision */
516 struct ir3_array
* ir3_lookup_array(struct ir3
*ir
, unsigned id
);
519 struct list_head node
;
522 const struct nir_block
*nblock
;
524 struct list_head instr_list
; /* list of ir3_instruction */
526 /* each block has either one or two successors.. in case of
527 * two successors, 'condition' decides which one to follow.
528 * A block preceding an if/else has two successors.
530 struct ir3_instruction
*condition
;
531 struct ir3_block
*successors
[2];
533 struct set
*predecessors
; /* set of ir3_block */
535 uint16_t start_ip
, end_ip
;
537 /* Track instructions which do not write a register but other-
538 * wise must not be discarded (such as kill, stg, etc)
540 DECLARE_ARRAY(struct ir3_instruction
*, keeps
);
542 /* used for per-pass extra block data. Mainly used right
543 * now in RA step to track livein/liveout.
552 static inline uint32_t
553 block_id(struct ir3_block
*block
)
556 return block
->serialno
;
558 return (uint32_t)(unsigned long)block
;
562 struct ir3
* ir3_create(struct ir3_compiler
*compiler
, gl_shader_stage type
);
563 void ir3_destroy(struct ir3
*shader
);
564 void * ir3_assemble(struct ir3
*shader
,
565 struct ir3_info
*info
, uint32_t gpu_id
);
566 void * ir3_alloc(struct ir3
*shader
, int sz
);
568 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
570 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
);
571 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
572 opc_t opc
, int nreg
);
573 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
574 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
);
575 const char *ir3_instr_name(struct ir3_instruction
*instr
);
577 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
579 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
580 struct ir3_register
*reg
);
582 void ir3_instr_set_address(struct ir3_instruction
*instr
,
583 struct ir3_instruction
*addr
);
585 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
587 if (instr
->flags
& IR3_INSTR_MARK
)
588 return true; /* already visited */
589 instr
->flags
|= IR3_INSTR_MARK
;
593 void ir3_block_clear_mark(struct ir3_block
*block
);
594 void ir3_clear_mark(struct ir3
*shader
);
596 unsigned ir3_count_instructions(struct ir3
*ir
);
597 unsigned ir3_count_instructions_ra(struct ir3
*ir
);
599 void ir3_find_ssa_uses(struct ir3
*ir
, void *mem_ctx
, bool falsedeps
);
601 #include "util/set.h"
602 #define foreach_ssa_use(__use, __instr) \
603 for (struct ir3_instruction *__use = (void *)~0; \
604 __use && (__instr)->uses; __use = NULL) \
605 set_foreach ((__instr)->uses, __entry) \
606 if ((__use = (void *)__entry->key))
608 #define MAX_ARRAYS 16
616 static inline uint32_t regid(int num
, int comp
)
618 return (num
<< 2) | (comp
& 0x3);
621 static inline uint32_t reg_num(struct ir3_register
*reg
)
623 return reg
->num
>> 2;
626 static inline uint32_t reg_comp(struct ir3_register
*reg
)
628 return reg
->num
& 0x3;
631 #define INVALID_REG regid(63, 0)
632 #define VALIDREG(r) ((r) != INVALID_REG)
633 #define CONDREG(r, val) COND(VALIDREG(r), (val))
635 static inline bool is_flow(struct ir3_instruction
*instr
)
637 return (opc_cat(instr
->opc
) == 0);
640 static inline bool is_kill(struct ir3_instruction
*instr
)
642 return instr
->opc
== OPC_KILL
;
645 static inline bool is_nop(struct ir3_instruction
*instr
)
647 return instr
->opc
== OPC_NOP
;
650 static inline bool is_same_type_reg(struct ir3_register
*reg1
,
651 struct ir3_register
*reg2
)
653 unsigned type_reg1
= (reg1
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
654 unsigned type_reg2
= (reg2
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
656 if (type_reg1
^ type_reg2
)
662 /* Is it a non-transformative (ie. not type changing) mov? This can
663 * also include absneg.s/absneg.f, which for the most part can be
664 * treated as a mov (single src argument).
666 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
668 struct ir3_register
*dst
;
670 switch (instr
->opc
) {
672 if (instr
->cat1
.src_type
!= instr
->cat1
.dst_type
)
674 /* If the type of dest reg and src reg are different,
675 * it shouldn't be considered as same type mov
677 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
682 if (instr
->flags
& IR3_INSTR_SAT
)
684 /* If the type of dest reg and src reg are different,
685 * it shouldn't be considered as same type mov
687 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
694 dst
= instr
->regs
[0];
696 /* mov's that write to a0 or p0.x are special: */
697 if (dst
->num
== regid(REG_P0
, 0))
699 if (reg_num(dst
) == REG_A0
)
702 if (dst
->flags
& (IR3_REG_RELATIV
| IR3_REG_ARRAY
))
708 /* A move from const, which changes size but not type, can also be
709 * folded into dest instruction in some cases.
711 static inline bool is_const_mov(struct ir3_instruction
*instr
)
713 if (instr
->opc
!= OPC_MOV
)
716 if (!(instr
->regs
[1]->flags
& IR3_REG_CONST
))
719 type_t src_type
= instr
->cat1
.src_type
;
720 type_t dst_type
= instr
->cat1
.dst_type
;
722 return (type_float(src_type
) && type_float(dst_type
)) ||
723 (type_uint(src_type
) && type_uint(dst_type
)) ||
724 (type_sint(src_type
) && type_sint(dst_type
));
727 static inline bool is_alu(struct ir3_instruction
*instr
)
729 return (1 <= opc_cat(instr
->opc
)) && (opc_cat(instr
->opc
) <= 3);
732 static inline bool is_sfu(struct ir3_instruction
*instr
)
734 return (opc_cat(instr
->opc
) == 4);
737 static inline bool is_tex(struct ir3_instruction
*instr
)
739 return (opc_cat(instr
->opc
) == 5);
742 static inline bool is_tex_or_prefetch(struct ir3_instruction
*instr
)
744 return is_tex(instr
) || (instr
->opc
== OPC_META_TEX_PREFETCH
);
747 static inline bool is_mem(struct ir3_instruction
*instr
)
749 return (opc_cat(instr
->opc
) == 6);
752 static inline bool is_barrier(struct ir3_instruction
*instr
)
754 return (opc_cat(instr
->opc
) == 7);
758 is_half(struct ir3_instruction
*instr
)
760 return !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
764 is_high(struct ir3_instruction
*instr
)
766 return !!(instr
->regs
[0]->flags
& IR3_REG_HIGH
);
770 is_store(struct ir3_instruction
*instr
)
772 /* these instructions, the "destination" register is
773 * actually a source, the address to store to.
775 switch (instr
->opc
) {
790 static inline bool is_load(struct ir3_instruction
*instr
)
792 switch (instr
->opc
) {
802 /* probably some others too.. */
809 static inline bool is_input(struct ir3_instruction
*instr
)
811 /* in some cases, ldlv is used to fetch varying without
812 * interpolation.. fortunately inloc is the first src
813 * register in either case
815 switch (instr
->opc
) {
824 static inline bool is_bool(struct ir3_instruction
*instr
)
826 switch (instr
->opc
) {
836 static inline bool is_meta(struct ir3_instruction
*instr
)
838 return (opc_cat(instr
->opc
) == -1);
841 static inline unsigned dest_regs(struct ir3_instruction
*instr
)
843 if ((instr
->regs_count
== 0) || is_store(instr
) || is_flow(instr
))
846 return util_last_bit(instr
->regs
[0]->wrmask
);
850 writes_gpr(struct ir3_instruction
*instr
)
852 if (dest_regs(instr
) == 0)
854 /* is dest a normal temp register: */
855 struct ir3_register
*reg
= instr
->regs
[0];
856 debug_assert(!(reg
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
)));
857 if ((reg_num(reg
) == REG_A0
) ||
858 (reg
->num
== regid(REG_P0
, 0)))
863 static inline bool writes_addr0(struct ir3_instruction
*instr
)
865 if (instr
->regs_count
> 0) {
866 struct ir3_register
*dst
= instr
->regs
[0];
867 return dst
->num
== regid(REG_A0
, 0);
872 static inline bool writes_addr1(struct ir3_instruction
*instr
)
874 if (instr
->regs_count
> 0) {
875 struct ir3_register
*dst
= instr
->regs
[0];
876 return dst
->num
== regid(REG_A0
, 1);
881 static inline bool writes_pred(struct ir3_instruction
*instr
)
883 if (instr
->regs_count
> 0) {
884 struct ir3_register
*dst
= instr
->regs
[0];
885 return reg_num(dst
) == REG_P0
;
890 /* returns defining instruction for reg */
891 /* TODO better name */
892 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
894 if (reg
->flags
& (IR3_REG_SSA
| IR3_REG_ARRAY
)) {
900 static inline bool conflicts(struct ir3_instruction
*a
,
901 struct ir3_instruction
*b
)
903 return (a
&& b
) && (a
!= b
);
906 static inline bool reg_gpr(struct ir3_register
*r
)
908 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
910 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
915 static inline type_t
half_type(type_t type
)
918 case TYPE_F32
: return TYPE_F16
;
919 case TYPE_U32
: return TYPE_U16
;
920 case TYPE_S32
: return TYPE_S16
;
931 /* some cat2 instructions (ie. those which are not float) can embed an
934 static inline bool ir3_cat2_int(opc_t opc
)
974 /* map cat2 instruction to valid abs/neg flags: */
975 static inline unsigned ir3_cat2_absneg(opc_t opc
)
992 return IR3_REG_FABS
| IR3_REG_FNEG
;
1013 return IR3_REG_SABS
| IR3_REG_SNEG
;
1027 return IR3_REG_BNOT
;
1034 /* map cat3 instructions to valid abs/neg flags: */
1035 static inline unsigned ir3_cat3_absneg(opc_t opc
)
1042 return IR3_REG_FNEG
;
1054 /* neg *may* work on 3rd src.. */
1064 #define MASK(n) ((1 << (n)) - 1)
1066 /* iterator for an instructions's sources (reg), also returns src #: */
1067 #define foreach_src_n(__srcreg, __n, __instr) \
1068 if ((__instr)->regs_count) \
1069 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
1070 if ((__srcreg = (__instr)->regs[__n + 1]))
1072 /* iterator for an instructions's sources (reg): */
1073 #define foreach_src(__srcreg, __instr) \
1074 foreach_src_n(__srcreg, __i, __instr)
1076 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
1078 unsigned cnt
= instr
->regs_count
+ instr
->deps_count
;
1084 static inline struct ir3_instruction
**
1085 __ssa_srcp_n(struct ir3_instruction
*instr
, unsigned n
)
1087 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1088 return &instr
->address
;
1089 if (n
>= instr
->regs_count
)
1090 return &instr
->deps
[n
- instr
->regs_count
];
1091 if (ssa(instr
->regs
[n
]))
1092 return &instr
->regs
[n
]->instr
;
1096 static inline bool __is_false_dep(struct ir3_instruction
*instr
, unsigned n
)
1098 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1100 if (n
>= instr
->regs_count
)
1105 #define foreach_ssa_srcp_n(__srcp, __n, __instr) \
1106 for (struct ir3_instruction **__srcp = (void *)~0; __srcp; __srcp = NULL) \
1107 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
1108 if ((__srcp = __ssa_srcp_n(__instr, __n)))
1110 #define foreach_ssa_srcp(__srcp, __instr) \
1111 foreach_ssa_srcp_n(__srcp, __i, __instr)
1113 /* iterator for an instruction's SSA sources (instr), also returns src #: */
1114 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
1115 foreach_ssa_srcp_n(__srcp, __n, __instr) \
1116 if ((__srcinst = *__srcp))
1118 /* iterator for an instruction's SSA sources (instr): */
1119 #define foreach_ssa_src(__srcinst, __instr) \
1120 foreach_ssa_src_n(__srcinst, __i, __instr)
1122 /* iterators for shader inputs: */
1123 #define foreach_input_n(__ininstr, __cnt, __ir) \
1124 for (unsigned __cnt = 0; __cnt < (__ir)->inputs_count; __cnt++) \
1125 if ((__ininstr = (__ir)->inputs[__cnt]))
1126 #define foreach_input(__ininstr, __ir) \
1127 foreach_input_n(__ininstr, __i, __ir)
1129 /* iterators for shader outputs: */
1130 #define foreach_output_n(__outinstr, __cnt, __ir) \
1131 for (unsigned __cnt = 0; __cnt < (__ir)->outputs_count; __cnt++) \
1132 if ((__outinstr = (__ir)->outputs[__cnt]))
1133 #define foreach_output(__outinstr, __ir) \
1134 foreach_output_n(__outinstr, __i, __ir)
1136 /* iterators for instructions: */
1137 #define foreach_instr(__instr, __list) \
1138 list_for_each_entry(struct ir3_instruction, __instr, __list, node)
1139 #define foreach_instr_rev(__instr, __list) \
1140 list_for_each_entry_rev(struct ir3_instruction, __instr, __list, node)
1141 #define foreach_instr_safe(__instr, __list) \
1142 list_for_each_entry_safe(struct ir3_instruction, __instr, __list, node)
1144 /* iterators for blocks: */
1145 #define foreach_block(__block, __list) \
1146 list_for_each_entry(struct ir3_block, __block, __list, node)
1147 #define foreach_block_safe(__block, __list) \
1148 list_for_each_entry_safe(struct ir3_block, __block, __list, node)
1149 #define foreach_block_rev(__block, __list) \
1150 list_for_each_entry_rev(struct ir3_block, __block, __list, node)
1152 /* iterators for arrays: */
1153 #define foreach_array(__array, __list) \
1154 list_for_each_entry(struct ir3_array, __array, __list, node)
1156 /* Check if condition is true for any src instruction.
1159 check_src_cond(struct ir3_instruction
*instr
, bool (*cond
)(struct ir3_instruction
*))
1161 struct ir3_register
*reg
;
1163 /* Note that this is also used post-RA so skip the ssa iterator: */
1164 foreach_src (reg
, instr
) {
1165 struct ir3_instruction
*src
= reg
->instr
;
1170 /* meta:split/collect aren't real instructions, the thing that
1171 * we actually care about is *their* srcs
1173 if ((src
->opc
== OPC_META_SPLIT
) || (src
->opc
== OPC_META_COLLECT
)) {
1174 if (check_src_cond(src
, cond
))
1186 void ir3_print(struct ir3
*ir
);
1187 void ir3_print_instr(struct ir3_instruction
*instr
);
1189 /* delay calculation: */
1190 int ir3_delayslots(struct ir3_instruction
*assigner
,
1191 struct ir3_instruction
*consumer
, unsigned n
, bool soft
);
1192 unsigned ir3_delay_calc(struct ir3_block
*block
, struct ir3_instruction
*instr
,
1193 bool soft
, bool pred
);
1194 void ir3_remove_nops(struct ir3
*ir
);
1196 /* dead code elimination: */
1197 struct ir3_shader_variant
;
1198 void ir3_dce(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1200 /* fp16 conversion folding */
1201 void ir3_cf(struct ir3
*ir
);
1203 /* copy-propagate: */
1204 void ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1206 /* group neighbors and insert mov's to resolve conflicts: */
1207 void ir3_group(struct ir3
*ir
);
1209 /* Sethi–Ullman numbering: */
1210 void ir3_sun(struct ir3
*ir
);
1213 void ir3_sched_add_deps(struct ir3
*ir
);
1214 int ir3_sched(struct ir3
*ir
);
1217 int ir3_postsched(struct ir3_context
*ctx
);
1219 bool ir3_a6xx_fixup_atomic_dests(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1221 /* register assignment: */
1222 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(struct ir3_compiler
*compiler
);
1223 int ir3_ra(struct ir3_shader_variant
*v
, struct ir3_instruction
**precolor
, unsigned nprecolor
);
1226 void ir3_legalize(struct ir3
*ir
, struct ir3_shader_variant
*so
, int *max_bary
);
1229 ir3_has_latency_to_hide(struct ir3
*ir
)
1231 /* VS/GS/TCS/TESS co-exist with frag shader invocations, but we don't
1232 * know the nature of the fragment shader. Just assume it will have
1235 if (ir
->type
!= MESA_SHADER_FRAGMENT
)
1238 foreach_block (block
, &ir
->block_list
) {
1239 foreach_instr (instr
, &block
->instr_list
) {
1240 if (is_tex_or_prefetch(instr
))
1243 if (is_load(instr
)) {
1244 switch (instr
->opc
) {
1259 /* ************************************************************************* */
1260 /* instruction helpers */
1262 /* creates SSA src of correct type (ie. half vs full precision) */
1263 static inline struct ir3_register
* __ssa_src(struct ir3_instruction
*instr
,
1264 struct ir3_instruction
*src
, unsigned flags
)
1266 struct ir3_register
*reg
;
1267 if (src
->regs
[0]->flags
& IR3_REG_HALF
)
1268 flags
|= IR3_REG_HALF
;
1269 reg
= ir3_reg_create(instr
, 0, IR3_REG_SSA
| flags
);
1271 reg
->wrmask
= src
->regs
[0]->wrmask
;
1275 static inline struct ir3_register
* __ssa_dst(struct ir3_instruction
*instr
)
1277 struct ir3_register
*reg
= ir3_reg_create(instr
, 0, 0);
1278 reg
->flags
|= IR3_REG_SSA
;
1282 static inline struct ir3_instruction
*
1283 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
1285 struct ir3_instruction
*mov
;
1286 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1288 mov
= ir3_instr_create(block
, OPC_MOV
);
1289 mov
->cat1
.src_type
= type
;
1290 mov
->cat1
.dst_type
= type
;
1291 __ssa_dst(mov
)->flags
|= flags
;
1292 ir3_reg_create(mov
, 0, IR3_REG_IMMED
| flags
)->uim_val
= val
;
1297 static inline struct ir3_instruction
*
1298 create_immed(struct ir3_block
*block
, uint32_t val
)
1300 return create_immed_typed(block
, val
, TYPE_U32
);
1303 static inline struct ir3_instruction
*
1304 create_uniform_typed(struct ir3_block
*block
, unsigned n
, type_t type
)
1306 struct ir3_instruction
*mov
;
1307 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1309 mov
= ir3_instr_create(block
, OPC_MOV
);
1310 mov
->cat1
.src_type
= type
;
1311 mov
->cat1
.dst_type
= type
;
1312 __ssa_dst(mov
)->flags
|= flags
;
1313 ir3_reg_create(mov
, n
, IR3_REG_CONST
| flags
);
1318 static inline struct ir3_instruction
*
1319 create_uniform(struct ir3_block
*block
, unsigned n
)
1321 return create_uniform_typed(block
, n
, TYPE_F32
);
1324 static inline struct ir3_instruction
*
1325 create_uniform_indirect(struct ir3_block
*block
, int n
,
1326 struct ir3_instruction
*address
)
1328 struct ir3_instruction
*mov
;
1330 mov
= ir3_instr_create(block
, OPC_MOV
);
1331 mov
->cat1
.src_type
= TYPE_U32
;
1332 mov
->cat1
.dst_type
= TYPE_U32
;
1334 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
1336 ir3_instr_set_address(mov
, address
);
1341 static inline struct ir3_instruction
*
1342 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
1344 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1346 if (src
->regs
[0]->flags
& IR3_REG_ARRAY
) {
1347 struct ir3_register
*src_reg
= __ssa_src(instr
, src
, IR3_REG_ARRAY
);
1348 src_reg
->array
= src
->regs
[0]->array
;
1350 __ssa_src(instr
, src
, src
->regs
[0]->flags
& IR3_REG_HIGH
);
1352 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_RELATIV
));
1353 instr
->cat1
.src_type
= type
;
1354 instr
->cat1
.dst_type
= type
;
1358 static inline struct ir3_instruction
*
1359 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
1360 type_t src_type
, type_t dst_type
)
1362 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1363 unsigned dst_flags
= (type_size(dst_type
) < 32) ? IR3_REG_HALF
: 0;
1364 unsigned src_flags
= (type_size(src_type
) < 32) ? IR3_REG_HALF
: 0;
1366 debug_assert((src
->regs
[0]->flags
& IR3_REG_HALF
) == src_flags
);
1368 __ssa_dst(instr
)->flags
|= dst_flags
;
1369 __ssa_src(instr
, src
, 0);
1370 instr
->cat1
.src_type
= src_type
;
1371 instr
->cat1
.dst_type
= dst_type
;
1372 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_ARRAY
));
1376 static inline struct ir3_instruction
*
1377 ir3_NOP(struct ir3_block
*block
)
1379 return ir3_instr_create(block
, OPC_NOP
);
1382 #define IR3_INSTR_0 0
1384 #define __INSTR0(flag, name, opc) \
1385 static inline struct ir3_instruction * \
1386 ir3_##name(struct ir3_block *block) \
1388 struct ir3_instruction *instr = \
1389 ir3_instr_create(block, opc); \
1390 instr->flags |= flag; \
1393 #define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name)
1394 #define INSTR0(name) __INSTR0(0, name, OPC_##name)
1396 #define __INSTR1(flag, name, opc) \
1397 static inline struct ir3_instruction * \
1398 ir3_##name(struct ir3_block *block, \
1399 struct ir3_instruction *a, unsigned aflags) \
1401 struct ir3_instruction *instr = \
1402 ir3_instr_create(block, opc); \
1404 __ssa_src(instr, a, aflags); \
1405 instr->flags |= flag; \
1408 #define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name)
1409 #define INSTR1(name) __INSTR1(0, name, OPC_##name)
1411 #define __INSTR2(flag, name, opc) \
1412 static inline struct ir3_instruction * \
1413 ir3_##name(struct ir3_block *block, \
1414 struct ir3_instruction *a, unsigned aflags, \
1415 struct ir3_instruction *b, unsigned bflags) \
1417 struct ir3_instruction *instr = \
1418 ir3_instr_create(block, opc); \
1420 __ssa_src(instr, a, aflags); \
1421 __ssa_src(instr, b, bflags); \
1422 instr->flags |= flag; \
1425 #define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name)
1426 #define INSTR2(name) __INSTR2(0, name, OPC_##name)
1428 #define __INSTR3(flag, name, opc) \
1429 static inline struct ir3_instruction * \
1430 ir3_##name(struct ir3_block *block, \
1431 struct ir3_instruction *a, unsigned aflags, \
1432 struct ir3_instruction *b, unsigned bflags, \
1433 struct ir3_instruction *c, unsigned cflags) \
1435 struct ir3_instruction *instr = \
1436 ir3_instr_create2(block, opc, 4); \
1438 __ssa_src(instr, a, aflags); \
1439 __ssa_src(instr, b, bflags); \
1440 __ssa_src(instr, c, cflags); \
1441 instr->flags |= flag; \
1444 #define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name)
1445 #define INSTR3(name) __INSTR3(0, name, OPC_##name)
1447 #define __INSTR4(flag, name, opc) \
1448 static inline struct ir3_instruction * \
1449 ir3_##name(struct ir3_block *block, \
1450 struct ir3_instruction *a, unsigned aflags, \
1451 struct ir3_instruction *b, unsigned bflags, \
1452 struct ir3_instruction *c, unsigned cflags, \
1453 struct ir3_instruction *d, unsigned dflags) \
1455 struct ir3_instruction *instr = \
1456 ir3_instr_create2(block, opc, 5); \
1458 __ssa_src(instr, a, aflags); \
1459 __ssa_src(instr, b, bflags); \
1460 __ssa_src(instr, c, cflags); \
1461 __ssa_src(instr, d, dflags); \
1462 instr->flags |= flag; \
1465 #define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name)
1466 #define INSTR4(name) __INSTR4(0, name, OPC_##name)
1468 /* cat0 instructions: */
1479 /* cat2 instructions, most 2 src but some 1 src: */
1527 /* cat3 instructions: */
1536 /* NOTE: SEL_B32 checks for zero vs nonzero */
1546 /* cat4 instructions: */
1558 /* cat5 instructions: */
1567 static inline struct ir3_instruction
*
1568 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1569 unsigned wrmask
, unsigned flags
, struct ir3_instruction
*samp_tex
,
1570 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1572 struct ir3_instruction
*sam
;
1574 sam
= ir3_instr_create(block
, opc
);
1575 sam
->flags
|= flags
;
1576 __ssa_dst(sam
)->wrmask
= wrmask
;
1577 if (flags
& IR3_INSTR_S2EN
) {
1578 __ssa_src(sam
, samp_tex
, IR3_REG_HALF
);
1581 __ssa_src(sam
, src0
, 0);
1584 __ssa_src(sam
, src1
, 0);
1586 sam
->cat5
.type
= type
;
1591 /* cat6 instructions: */
1606 INSTR2(ATOMIC_CMPXCHG
)
1616 INSTR3F(G
, ATOMIC_ADD
)
1617 INSTR3F(G
, ATOMIC_SUB
)
1618 INSTR3F(G
, ATOMIC_XCHG
)
1619 INSTR3F(G
, ATOMIC_INC
)
1620 INSTR3F(G
, ATOMIC_DEC
)
1621 INSTR3F(G
, ATOMIC_CMPXCHG
)
1622 INSTR3F(G
, ATOMIC_MIN
)
1623 INSTR3F(G
, ATOMIC_MAX
)
1624 INSTR3F(G
, ATOMIC_AND
)
1625 INSTR3F(G
, ATOMIC_OR
)
1626 INSTR3F(G
, ATOMIC_XOR
)
1631 INSTR4F(G
, ATOMIC_ADD
)
1632 INSTR4F(G
, ATOMIC_SUB
)
1633 INSTR4F(G
, ATOMIC_XCHG
)
1634 INSTR4F(G
, ATOMIC_INC
)
1635 INSTR4F(G
, ATOMIC_DEC
)
1636 INSTR4F(G
, ATOMIC_CMPXCHG
)
1637 INSTR4F(G
, ATOMIC_MIN
)
1638 INSTR4F(G
, ATOMIC_MAX
)
1639 INSTR4F(G
, ATOMIC_AND
)
1640 INSTR4F(G
, ATOMIC_OR
)
1641 INSTR4F(G
, ATOMIC_XOR
)
1646 /* cat7 instructions: */
1650 /* meta instructions: */
1651 INSTR0(META_TEX_PREFETCH
);
1653 /* ************************************************************************* */
1654 /* split this out or find some helper to use.. like main/bitset.h.. */
1657 #include "util/bitset.h"
1661 typedef BITSET_DECLARE(regmask_t
, 2 * MAX_REG
);
1664 __regmask_get(regmask_t
*regmask
, struct ir3_register
*reg
, unsigned n
)
1667 /* a6xx+ case, with merged register file, we track things in terms
1668 * of half-precision registers, with a full precisions register
1669 * using two half-precision slots:
1671 if (reg
->flags
& IR3_REG_HALF
) {
1672 return BITSET_TEST(*regmask
, n
);
1675 return BITSET_TEST(*regmask
, n
) || BITSET_TEST(*regmask
, n
+1);
1678 /* pre a6xx case, with separate register file for half and full
1681 if (reg
->flags
& IR3_REG_HALF
)
1683 return BITSET_TEST(*regmask
, n
);
1688 __regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
, unsigned n
)
1691 /* a6xx+ case, with merged register file, we track things in terms
1692 * of half-precision registers, with a full precisions register
1693 * using two half-precision slots:
1695 if (reg
->flags
& IR3_REG_HALF
) {
1696 BITSET_SET(*regmask
, n
);
1699 BITSET_SET(*regmask
, n
);
1700 BITSET_SET(*regmask
, n
+1);
1703 /* pre a6xx case, with separate register file for half and full
1706 if (reg
->flags
& IR3_REG_HALF
)
1708 BITSET_SET(*regmask
, n
);
1712 static inline void regmask_init(regmask_t
*regmask
)
1714 memset(regmask
, 0, sizeof(*regmask
));
1717 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1719 if (reg
->flags
& IR3_REG_RELATIV
) {
1720 for (unsigned i
= 0; i
< reg
->size
; i
++)
1721 __regmask_set(regmask
, reg
, reg
->array
.offset
+ i
);
1723 for (unsigned mask
= reg
->wrmask
, n
= reg
->num
; mask
; mask
>>= 1, n
++)
1725 __regmask_set(regmask
, reg
, n
);
1729 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1732 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1733 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1736 static inline bool regmask_get(regmask_t
*regmask
,
1737 struct ir3_register
*reg
)
1739 if (reg
->flags
& IR3_REG_RELATIV
) {
1740 for (unsigned i
= 0; i
< reg
->size
; i
++)
1741 if (__regmask_get(regmask
, reg
, reg
->array
.offset
+ i
))
1744 for (unsigned mask
= reg
->wrmask
, n
= reg
->num
; mask
; mask
>>= 1, n
++)
1746 if (__regmask_get(regmask
, reg
, n
))
1752 /* ************************************************************************* */