2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "compiler/shader_enums.h"
32 #include "util/bitscan.h"
33 #include "util/list.h"
35 #include "util/u_debug.h"
37 #include "instr-a3xx.h"
39 /* low level intermediate representation of an adreno shader program */
43 struct ir3_instruction
;
49 uint16_t instrs_count
; /* expanded to account for rpt's */
50 uint16_t nops_count
; /* # of nop instructions, including nopN */
51 /* NOTE: max_reg, etc, does not include registers not touched
52 * by the shader (ie. vertex fetched via VFD_DECODE but not
55 int8_t max_reg
; /* highest GPR # used by shader */
59 /* number of sync bits: */
65 IR3_REG_CONST
= 0x001,
66 IR3_REG_IMMED
= 0x002,
68 /* high registers are used for some things in compute shaders,
69 * for example. Seems to be for things that are global to all
70 * threads in a wave, so possibly these are global/shared by
71 * all the threads in the wave?
74 IR3_REG_RELATIV
= 0x010,
76 /* Most instructions, it seems, can do float abs/neg but not
77 * integer. The CP pass needs to know what is intended (int or
78 * float) in order to do the right thing. For this reason the
79 * abs/neg flags are split out into float and int variants. In
80 * addition, .b (bitwise) operations, the negate is actually a
81 * bitwise not, so split that out into a new flag to make it
90 IR3_REG_POS_INF
= 0x1000,
91 /* (ei) flag, end-input? Set on last bary, presumably to signal
92 * that the shader needs no more input:
95 /* meta-flags, for intermediate stages of IR, ie.
96 * before register assignment is done:
98 IR3_REG_SSA
= 0x4000, /* 'instr' is ptr to assigning instr */
99 IR3_REG_ARRAY
= 0x8000,
103 bool merged
: 1; /* half-regs conflict with full regs (ie >= a6xx) */
106 * the component is in the low two bits of the reg #, so
107 * rN.x becomes: (N << 2) | x
122 /* For IR3_REG_SSA, src registers contain ptr back to assigning
125 * For IR3_REG_ARRAY, the pointer is back to the last dependent
126 * array access (although the net effect is the same, it points
127 * back to a previous instruction that we depend on).
129 struct ir3_instruction
*instr
;
132 /* used for cat5 instructions, but also for internal/IR level
133 * tracking of what registers are read/written by an instruction.
134 * wrmask may be a bad name since it is used to represent both
135 * src and dst that touch multiple adjacent registers.
138 /* for relative addressing, 32bits for array size is too small,
139 * but otoh we don't need to deal with disjoint sets, so instead
140 * use a simple size field (number of scalar components).
147 * Stupid/simple growable array implementation:
149 #define DECLARE_ARRAY(type, name) \
150 unsigned name ## _count, name ## _sz; \
153 #define array_insert(ctx, arr, val) do { \
154 if (arr ## _count == arr ## _sz) { \
155 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
156 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
158 arr[arr ##_count++] = val; \
161 struct ir3_instruction
{
162 struct ir3_block
*block
;
165 /* (sy) flag is set on first instruction, and after sample
166 * instructions (probably just on RAW hazard).
168 IR3_INSTR_SY
= 0x001,
169 /* (ss) flag is set on first instruction, and first instruction
170 * to depend on the result of "long" instructions (RAW hazard):
172 * rcp, rsq, log2, exp2, sin, cos, sqrt
174 * It seems to synchronize until all in-flight instructions are
175 * completed, for example:
178 * add.f hr2.z, (neg)hr2.z, hc0.y
179 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
182 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
184 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
185 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
186 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
188 * The last mul.f does not have (ss) set, presumably because the
189 * (ss) on the previous instruction does the job.
191 * The blob driver also seems to set it on WAR hazards, although
192 * not really clear if this is needed or just blob compiler being
193 * sloppy. So far I haven't found a case where removing the (ss)
194 * causes problems for WAR hazard, but I could just be getting
198 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
201 IR3_INSTR_SS
= 0x002,
202 /* (jp) flag is set on jump targets:
204 IR3_INSTR_JP
= 0x004,
205 IR3_INSTR_UL
= 0x008,
206 IR3_INSTR_3D
= 0x010,
211 IR3_INSTR_S2EN
= 0x200,
213 IR3_INSTR_SAT
= 0x800,
214 /* meta-flags, for intermediate stages of IR, ie.
215 * before register assignment is done:
217 IR3_INSTR_MARK
= 0x1000,
218 IR3_INSTR_UNUSED
= 0x2000,
226 struct ir3_register
**regs
;
232 struct ir3_block
*target
;
235 type_t src_type
, dst_type
;
255 int iim_val
: 3; /* for ldgb/stgb, # of components */
260 unsigned w
: 1; /* write */
261 unsigned r
: 1; /* read */
262 unsigned l
: 1; /* local */
263 unsigned g
: 1; /* global */
265 /* for meta-instructions, just used to hold extra data
266 * before instruction scheduling, etc
269 int off
; /* component/offset */
272 /* for output collects, this maps back to the entry in the
273 * ir3_shader_variant::outputs table.
279 unsigned input_offset
;
282 /* maps back to entry in ir3_shader_variant::inputs table: */
284 /* for sysvals, identifies the sysval type. Mostly so we can
285 * identify the special cases where a sysval should not be DCE'd
286 * (currently, just pre-fs texture fetch)
288 gl_system_value sysval
;
292 /* transient values used during various algorithms: */
294 /* The instruction depth is the max dependency distance to output.
296 * You can also think of it as the "cost", if we did any sort of
297 * optimization for register footprint. Ie. a value that is just
298 * result of moving a const to a reg would have a low cost, so to
299 * it could make sense to duplicate the instruction at various
300 * points where the result is needed to reduce register footprint.
303 /* When we get to the RA stage, we no longer need depth, but
304 * we do need instruction's position/name:
312 /* used for per-pass extra instruction data.
314 * TODO we should remove the per-pass data like this and 'use_count'
315 * and do something similar to what RA does w/ ir3_ra_instr_data..
316 * ie. use the ir3_count_instructions pass, and then use instr->ip
317 * to index into a table of pass-private data.
321 int sun
; /* Sethi–Ullman number, used by sched */
322 int use_count
; /* currently just updated/used by cp */
324 /* Used during CP and RA stages. For collect and shader inputs/
325 * outputs where we need a sequence of consecutive registers,
326 * keep track of each src instructions left (ie 'n-1') and right
327 * (ie 'n+1') neighbor. The front-end must insert enough mov's
328 * to ensure that each instruction has at most one left and at
329 * most one right neighbor. During the copy-propagation pass,
330 * we only remove mov's when we can preserve this constraint.
331 * And during the RA stage, we use the neighbor information to
332 * allocate a block of registers in one shot.
334 * TODO: maybe just add something like:
335 * struct ir3_instruction_ref {
336 * struct ir3_instruction *instr;
340 * Or can we get away without the refcnt stuff? It seems like
341 * it should be overkill.. the problem is if, potentially after
342 * already eliminating some mov's, if you have a single mov that
343 * needs to be grouped with it's neighbors in two different
344 * places (ex. shader output and a collect).
347 struct ir3_instruction
*left
, *right
;
348 uint16_t left_cnt
, right_cnt
;
351 /* an instruction can reference at most one address register amongst
352 * it's src/dst registers. Beyond that, you need to insert mov's.
354 * NOTE: do not write this directly, use ir3_instr_set_address()
356 struct ir3_instruction
*address
;
358 /* Tracking for additional dependent instructions. Used to handle
359 * barriers, WAR hazards for arrays/SSBOs/etc.
361 DECLARE_ARRAY(struct ir3_instruction
*, deps
);
364 * From PoV of instruction scheduling, not execution (ie. ignores global/
365 * local distinction):
366 * shared image atomic SSBO everything
367 * barrier()/ - R/W R/W R/W R/W X
368 * groupMemoryBarrier()
369 * memoryBarrier() - R/W R/W
370 * (but only images declared coherent?)
371 * memoryBarrierAtomic() - R/W
372 * memoryBarrierBuffer() - R/W
373 * memoryBarrierImage() - R/W
374 * memoryBarrierShared() - R/W
376 * TODO I think for SSBO/image/shared, in cases where we can determine
377 * which variable is accessed, we don't need to care about accesses to
378 * different variables (unless declared coherent??)
381 IR3_BARRIER_EVERYTHING
= 1 << 0,
382 IR3_BARRIER_SHARED_R
= 1 << 1,
383 IR3_BARRIER_SHARED_W
= 1 << 2,
384 IR3_BARRIER_IMAGE_R
= 1 << 3,
385 IR3_BARRIER_IMAGE_W
= 1 << 4,
386 IR3_BARRIER_BUFFER_R
= 1 << 5,
387 IR3_BARRIER_BUFFER_W
= 1 << 6,
388 IR3_BARRIER_ARRAY_R
= 1 << 7,
389 IR3_BARRIER_ARRAY_W
= 1 << 8,
390 } barrier_class
, barrier_conflict
;
392 /* Entry in ir3_block's instruction list: */
393 struct list_head node
;
400 static inline struct ir3_instruction
*
401 ir3_neighbor_first(struct ir3_instruction
*instr
)
404 while (instr
->cp
.left
) {
405 instr
= instr
->cp
.left
;
406 if (++cnt
> 0xffff) {
414 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
418 debug_assert(!instr
->cp
.left
);
420 while (instr
->cp
.right
) {
422 instr
= instr
->cp
.right
;
433 struct ir3_compiler
*compiler
;
434 gl_shader_stage type
;
436 DECLARE_ARRAY(struct ir3_instruction
*, inputs
);
437 DECLARE_ARRAY(struct ir3_instruction
*, outputs
);
439 /* Track bary.f (and ldlv) instructions.. this is needed in
440 * scheduling to ensure that all varying fetches happen before
441 * any potential kill instructions. The hw gets grumpy if all
442 * threads in a group are killed before the last bary.f gets
443 * a chance to signal end of input (ei).
445 DECLARE_ARRAY(struct ir3_instruction
*, baryfs
);
447 /* Track all indirect instructions (read and write). To avoid
448 * deadlock scenario where an address register gets scheduled,
449 * but other dependent src instructions cannot be scheduled due
450 * to dependency on a *different* address register value, the
451 * scheduler needs to ensure that all dependencies other than
452 * the instruction other than the address register are scheduled
453 * before the one that writes the address register. Having a
454 * convenient list of instructions that reference some address
455 * register simplifies this.
457 DECLARE_ARRAY(struct ir3_instruction
*, indirects
);
459 /* and same for instructions that consume predicate register: */
460 DECLARE_ARRAY(struct ir3_instruction
*, predicates
);
462 /* Track texture sample instructions which need texture state
463 * patched in (for astc-srgb workaround):
465 DECLARE_ARRAY(struct ir3_instruction
*, astc_srgb
);
467 /* List of blocks: */
468 struct list_head block_list
;
470 /* List of ir3_array's: */
471 struct list_head array_list
;
473 unsigned max_sun
; /* max Sethi–Ullman number */
476 unsigned block_count
, instr_count
;
481 struct list_head node
;
485 struct nir_register
*r
;
487 /* To avoid array write's from getting DCE'd, keep track of the
488 * most recent write. Any array access depends on the most
489 * recent write. This way, nothing depends on writes after the
490 * last read. But all the writes that happen before that have
491 * something depending on them
493 struct ir3_instruction
*last_write
;
495 /* extra stuff used in RA pass: */
496 unsigned base
; /* base vreg name */
497 unsigned reg
; /* base physical reg */
498 uint16_t start_ip
, end_ip
;
501 struct ir3_array
* ir3_lookup_array(struct ir3
*ir
, unsigned id
);
504 struct list_head node
;
507 const struct nir_block
*nblock
;
509 struct list_head instr_list
; /* list of ir3_instruction */
511 /* each block has either one or two successors.. in case of
512 * two successors, 'condition' decides which one to follow.
513 * A block preceding an if/else has two successors.
515 struct ir3_instruction
*condition
;
516 struct ir3_block
*successors
[2];
518 struct set
*predecessors
; /* set of ir3_block */
520 uint16_t start_ip
, end_ip
;
522 /* Track instructions which do not write a register but other-
523 * wise must not be discarded (such as kill, stg, etc)
525 DECLARE_ARRAY(struct ir3_instruction
*, keeps
);
527 /* used for per-pass extra block data. Mainly used right
528 * now in RA step to track livein/liveout.
537 static inline uint32_t
538 block_id(struct ir3_block
*block
)
541 return block
->serialno
;
543 return (uint32_t)(unsigned long)block
;
547 struct ir3
* ir3_create(struct ir3_compiler
*compiler
, gl_shader_stage type
);
548 void ir3_destroy(struct ir3
*shader
);
549 void * ir3_assemble(struct ir3
*shader
,
550 struct ir3_info
*info
, uint32_t gpu_id
);
551 void * ir3_alloc(struct ir3
*shader
, int sz
);
553 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
555 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
);
556 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
557 opc_t opc
, int nreg
);
558 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
559 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
);
560 const char *ir3_instr_name(struct ir3_instruction
*instr
);
562 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
564 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
565 struct ir3_register
*reg
);
567 void ir3_instr_set_address(struct ir3_instruction
*instr
,
568 struct ir3_instruction
*addr
);
570 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
572 if (instr
->flags
& IR3_INSTR_MARK
)
573 return true; /* already visited */
574 instr
->flags
|= IR3_INSTR_MARK
;
578 void ir3_block_clear_mark(struct ir3_block
*block
);
579 void ir3_clear_mark(struct ir3
*shader
);
581 unsigned ir3_count_instructions(struct ir3
*ir
);
583 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
584 struct ir3_register
*reg
)
587 for (i
= 0; i
< instr
->regs_count
; i
++)
588 if (reg
== instr
->regs
[i
])
594 #define MAX_ARRAYS 16
602 static inline uint32_t regid(int num
, int comp
)
604 return (num
<< 2) | (comp
& 0x3);
607 static inline uint32_t reg_num(struct ir3_register
*reg
)
609 return reg
->num
>> 2;
612 static inline uint32_t reg_comp(struct ir3_register
*reg
)
614 return reg
->num
& 0x3;
617 static inline bool is_flow(struct ir3_instruction
*instr
)
619 return (opc_cat(instr
->opc
) == 0);
622 static inline bool is_kill(struct ir3_instruction
*instr
)
624 return instr
->opc
== OPC_KILL
|| instr
->opc
== OPC_CONDEND
;
627 static inline bool is_nop(struct ir3_instruction
*instr
)
629 return instr
->opc
== OPC_NOP
;
632 static inline bool is_same_type_reg(struct ir3_register
*reg1
,
633 struct ir3_register
*reg2
)
635 unsigned type_reg1
= (reg1
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
636 unsigned type_reg2
= (reg2
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
638 if (type_reg1
^ type_reg2
)
644 /* Is it a non-transformative (ie. not type changing) mov? This can
645 * also include absneg.s/absneg.f, which for the most part can be
646 * treated as a mov (single src argument).
648 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
650 struct ir3_register
*dst
;
652 switch (instr
->opc
) {
654 if (instr
->cat1
.src_type
!= instr
->cat1
.dst_type
)
656 /* If the type of dest reg and src reg are different,
657 * it shouldn't be considered as same type mov
659 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
664 if (instr
->flags
& IR3_INSTR_SAT
)
666 /* If the type of dest reg and src reg are different,
667 * it shouldn't be considered as same type mov
669 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
676 dst
= instr
->regs
[0];
678 /* mov's that write to a0.x or p0.x are special: */
679 if (dst
->num
== regid(REG_P0
, 0))
681 if (dst
->num
== regid(REG_A0
, 0))
684 if (dst
->flags
& (IR3_REG_RELATIV
| IR3_REG_ARRAY
))
690 static inline bool is_alu(struct ir3_instruction
*instr
)
692 return (1 <= opc_cat(instr
->opc
)) && (opc_cat(instr
->opc
) <= 3);
695 static inline bool is_sfu(struct ir3_instruction
*instr
)
697 return (opc_cat(instr
->opc
) == 4);
700 static inline bool is_tex(struct ir3_instruction
*instr
)
702 return (opc_cat(instr
->opc
) == 5);
705 static inline bool is_mem(struct ir3_instruction
*instr
)
707 return (opc_cat(instr
->opc
) == 6);
710 static inline bool is_barrier(struct ir3_instruction
*instr
)
712 return (opc_cat(instr
->opc
) == 7);
716 is_store(struct ir3_instruction
*instr
)
718 /* these instructions, the "destination" register is
719 * actually a source, the address to store to.
721 switch (instr
->opc
) {
736 static inline bool is_load(struct ir3_instruction
*instr
)
738 switch (instr
->opc
) {
748 /* probably some others too.. */
755 static inline bool is_input(struct ir3_instruction
*instr
)
757 /* in some cases, ldlv is used to fetch varying without
758 * interpolation.. fortunately inloc is the first src
759 * register in either case
761 switch (instr
->opc
) {
770 static inline bool is_bool(struct ir3_instruction
*instr
)
772 switch (instr
->opc
) {
782 static inline bool is_meta(struct ir3_instruction
*instr
)
784 return (opc_cat(instr
->opc
) == -1);
787 static inline unsigned dest_regs(struct ir3_instruction
*instr
)
789 if ((instr
->regs_count
== 0) || is_store(instr
))
792 return util_last_bit(instr
->regs
[0]->wrmask
);
795 static inline bool writes_addr(struct ir3_instruction
*instr
)
797 if (instr
->regs_count
> 0) {
798 struct ir3_register
*dst
= instr
->regs
[0];
799 return reg_num(dst
) == REG_A0
;
804 static inline bool writes_pred(struct ir3_instruction
*instr
)
806 if (instr
->regs_count
> 0) {
807 struct ir3_register
*dst
= instr
->regs
[0];
808 return reg_num(dst
) == REG_P0
;
813 /* returns defining instruction for reg */
814 /* TODO better name */
815 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
817 if (reg
->flags
& (IR3_REG_SSA
| IR3_REG_ARRAY
)) {
823 static inline bool conflicts(struct ir3_instruction
*a
,
824 struct ir3_instruction
*b
)
826 return (a
&& b
) && (a
!= b
);
829 static inline bool reg_gpr(struct ir3_register
*r
)
831 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
833 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
838 static inline type_t
half_type(type_t type
)
841 case TYPE_F32
: return TYPE_F16
;
842 case TYPE_U32
: return TYPE_U16
;
843 case TYPE_S32
: return TYPE_S16
;
854 /* some cat2 instructions (ie. those which are not float) can embed an
857 static inline bool ir3_cat2_int(opc_t opc
)
897 static inline bool ir3_cat2_float(opc_t opc
)
920 static inline bool ir3_cat3_float(opc_t opc
)
933 /* map cat2 instruction to valid abs/neg flags: */
934 static inline unsigned ir3_cat2_absneg(opc_t opc
)
951 return IR3_REG_FABS
| IR3_REG_FNEG
;
972 return IR3_REG_SABS
| IR3_REG_SNEG
;
993 /* map cat3 instructions to valid abs/neg flags: */
994 static inline unsigned ir3_cat3_absneg(opc_t opc
)
1001 return IR3_REG_FNEG
;
1013 /* neg *may* work on 3rd src.. */
1023 #define MASK(n) ((1 << (n)) - 1)
1025 /* iterator for an instructions's sources (reg), also returns src #: */
1026 #define foreach_src_n(__srcreg, __n, __instr) \
1027 if ((__instr)->regs_count) \
1028 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
1029 if ((__srcreg = (__instr)->regs[__n + 1]))
1031 /* iterator for an instructions's sources (reg): */
1032 #define foreach_src(__srcreg, __instr) \
1033 foreach_src_n(__srcreg, __i, __instr)
1035 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
1037 unsigned cnt
= instr
->regs_count
+ instr
->deps_count
;
1043 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
1045 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1046 return instr
->address
;
1047 if (n
>= instr
->regs_count
)
1048 return instr
->deps
[n
- instr
->regs_count
];
1049 return ssa(instr
->regs
[n
]);
1052 static inline bool __is_false_dep(struct ir3_instruction
*instr
, unsigned n
)
1054 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1056 if (n
>= instr
->regs_count
)
1061 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
1063 /* iterator for an instruction's SSA sources (instr), also returns src #: */
1064 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
1065 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
1066 if ((__srcinst = __ssa_src_n(__instr, __n)))
1068 /* iterator for an instruction's SSA sources (instr): */
1069 #define foreach_ssa_src(__srcinst, __instr) \
1070 foreach_ssa_src_n(__srcinst, __i, __instr)
1072 /* iterators for shader inputs: */
1073 #define foreach_input_n(__ininstr, __cnt, __ir) \
1074 for (unsigned __cnt = 0; __cnt < (__ir)->inputs_count; __cnt++) \
1075 if ((__ininstr = (__ir)->inputs[__cnt]))
1076 #define foreach_input(__ininstr, __ir) \
1077 foreach_input_n(__ininstr, __i, __ir)
1079 /* iterators for shader outputs: */
1080 #define foreach_output_n(__outinstr, __cnt, __ir) \
1081 for (unsigned __cnt = 0; __cnt < (__ir)->outputs_count; __cnt++) \
1082 if ((__outinstr = (__ir)->outputs[__cnt]))
1083 #define foreach_output(__outinstr, __ir) \
1084 foreach_output_n(__outinstr, __i, __ir)
1087 void ir3_print(struct ir3
*ir
);
1088 void ir3_print_instr(struct ir3_instruction
*instr
);
1090 /* depth calculation: */
1091 struct ir3_shader_variant
;
1092 int ir3_delayslots(struct ir3_instruction
*assigner
,
1093 struct ir3_instruction
*consumer
, unsigned n
);
1094 void ir3_insert_by_depth(struct ir3_instruction
*instr
, struct list_head
*list
);
1095 void ir3_depth(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1097 /* copy-propagate: */
1098 void ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1100 /* group neighbors and insert mov's to resolve conflicts: */
1101 void ir3_group(struct ir3
*ir
);
1103 /* Sethi–Ullman numbering: */
1104 void ir3_sun(struct ir3
*ir
);
1107 void ir3_sched_add_deps(struct ir3
*ir
);
1108 int ir3_sched(struct ir3
*ir
);
1110 void ir3_a6xx_fixup_atomic_dests(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1112 /* register assignment: */
1113 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(struct ir3_compiler
*compiler
);
1114 int ir3_ra(struct ir3_shader_variant
*v
, struct ir3_instruction
**precolor
, unsigned nprecolor
);
1117 void ir3_legalize(struct ir3
*ir
, bool *has_ssbo
, bool *need_pixlod
, int *max_bary
);
1119 /* ************************************************************************* */
1120 /* instruction helpers */
1122 /* creates SSA src of correct type (ie. half vs full precision) */
1123 static inline struct ir3_register
* __ssa_src(struct ir3_instruction
*instr
,
1124 struct ir3_instruction
*src
, unsigned flags
)
1126 struct ir3_register
*reg
;
1127 if (src
->regs
[0]->flags
& IR3_REG_HALF
)
1128 flags
|= IR3_REG_HALF
;
1129 reg
= ir3_reg_create(instr
, 0, IR3_REG_SSA
| flags
);
1131 reg
->wrmask
= src
->regs
[0]->wrmask
;
1135 static inline struct ir3_register
* __ssa_dst(struct ir3_instruction
*instr
)
1137 struct ir3_register
*reg
= ir3_reg_create(instr
, 0, 0);
1138 reg
->flags
|= IR3_REG_SSA
;
1142 static inline struct ir3_instruction
*
1143 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
1145 struct ir3_instruction
*mov
;
1146 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1148 mov
= ir3_instr_create(block
, OPC_MOV
);
1149 mov
->cat1
.src_type
= type
;
1150 mov
->cat1
.dst_type
= type
;
1151 __ssa_dst(mov
)->flags
|= flags
;
1152 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
1157 static inline struct ir3_instruction
*
1158 create_immed(struct ir3_block
*block
, uint32_t val
)
1160 return create_immed_typed(block
, val
, TYPE_U32
);
1163 static inline struct ir3_instruction
*
1164 create_uniform_typed(struct ir3_block
*block
, unsigned n
, type_t type
)
1166 struct ir3_instruction
*mov
;
1167 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1169 mov
= ir3_instr_create(block
, OPC_MOV
);
1170 mov
->cat1
.src_type
= type
;
1171 mov
->cat1
.dst_type
= type
;
1172 __ssa_dst(mov
)->flags
|= flags
;
1173 ir3_reg_create(mov
, n
, IR3_REG_CONST
| flags
);
1178 static inline struct ir3_instruction
*
1179 create_uniform(struct ir3_block
*block
, unsigned n
)
1181 return create_uniform_typed(block
, n
, TYPE_F32
);
1184 static inline struct ir3_instruction
*
1185 create_uniform_indirect(struct ir3_block
*block
, int n
,
1186 struct ir3_instruction
*address
)
1188 struct ir3_instruction
*mov
;
1190 mov
= ir3_instr_create(block
, OPC_MOV
);
1191 mov
->cat1
.src_type
= TYPE_U32
;
1192 mov
->cat1
.dst_type
= TYPE_U32
;
1194 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
1196 ir3_instr_set_address(mov
, address
);
1201 static inline struct ir3_instruction
*
1202 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
1204 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1206 if (src
->regs
[0]->flags
& IR3_REG_ARRAY
) {
1207 struct ir3_register
*src_reg
= __ssa_src(instr
, src
, IR3_REG_ARRAY
);
1208 src_reg
->array
= src
->regs
[0]->array
;
1210 __ssa_src(instr
, src
, src
->regs
[0]->flags
& IR3_REG_HIGH
);
1212 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_RELATIV
));
1213 instr
->cat1
.src_type
= type
;
1214 instr
->cat1
.dst_type
= type
;
1218 static inline struct ir3_instruction
*
1219 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
1220 type_t src_type
, type_t dst_type
)
1222 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1223 unsigned dst_flags
= (type_size(dst_type
) < 32) ? IR3_REG_HALF
: 0;
1224 unsigned src_flags
= (type_size(src_type
) < 32) ? IR3_REG_HALF
: 0;
1226 debug_assert((src
->regs
[0]->flags
& IR3_REG_HALF
) == src_flags
);
1228 __ssa_dst(instr
)->flags
|= dst_flags
;
1229 __ssa_src(instr
, src
, 0);
1230 instr
->cat1
.src_type
= src_type
;
1231 instr
->cat1
.dst_type
= dst_type
;
1232 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_ARRAY
));
1236 static inline struct ir3_instruction
*
1237 ir3_NOP(struct ir3_block
*block
)
1239 return ir3_instr_create(block
, OPC_NOP
);
1242 #define IR3_INSTR_0 0
1244 #define __INSTR0(flag, name, opc) \
1245 static inline struct ir3_instruction * \
1246 ir3_##name(struct ir3_block *block) \
1248 struct ir3_instruction *instr = \
1249 ir3_instr_create(block, opc); \
1250 instr->flags |= flag; \
1253 #define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name)
1254 #define INSTR0(name) __INSTR0(0, name, OPC_##name)
1256 #define __INSTR1(flag, name, opc) \
1257 static inline struct ir3_instruction * \
1258 ir3_##name(struct ir3_block *block, \
1259 struct ir3_instruction *a, unsigned aflags) \
1261 struct ir3_instruction *instr = \
1262 ir3_instr_create(block, opc); \
1264 __ssa_src(instr, a, aflags); \
1265 instr->flags |= flag; \
1268 #define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name)
1269 #define INSTR1(name) __INSTR1(0, name, OPC_##name)
1271 #define __INSTR2(flag, name, opc) \
1272 static inline struct ir3_instruction * \
1273 ir3_##name(struct ir3_block *block, \
1274 struct ir3_instruction *a, unsigned aflags, \
1275 struct ir3_instruction *b, unsigned bflags) \
1277 struct ir3_instruction *instr = \
1278 ir3_instr_create(block, opc); \
1280 __ssa_src(instr, a, aflags); \
1281 __ssa_src(instr, b, bflags); \
1282 instr->flags |= flag; \
1285 #define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name)
1286 #define INSTR2(name) __INSTR2(0, name, OPC_##name)
1288 #define __INSTR3(flag, name, opc) \
1289 static inline struct ir3_instruction * \
1290 ir3_##name(struct ir3_block *block, \
1291 struct ir3_instruction *a, unsigned aflags, \
1292 struct ir3_instruction *b, unsigned bflags, \
1293 struct ir3_instruction *c, unsigned cflags) \
1295 struct ir3_instruction *instr = \
1296 ir3_instr_create2(block, opc, 4); \
1298 __ssa_src(instr, a, aflags); \
1299 __ssa_src(instr, b, bflags); \
1300 __ssa_src(instr, c, cflags); \
1301 instr->flags |= flag; \
1304 #define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name)
1305 #define INSTR3(name) __INSTR3(0, name, OPC_##name)
1307 #define __INSTR4(flag, name, opc) \
1308 static inline struct ir3_instruction * \
1309 ir3_##name(struct ir3_block *block, \
1310 struct ir3_instruction *a, unsigned aflags, \
1311 struct ir3_instruction *b, unsigned bflags, \
1312 struct ir3_instruction *c, unsigned cflags, \
1313 struct ir3_instruction *d, unsigned dflags) \
1315 struct ir3_instruction *instr = \
1316 ir3_instr_create2(block, opc, 5); \
1318 __ssa_src(instr, a, aflags); \
1319 __ssa_src(instr, b, bflags); \
1320 __ssa_src(instr, c, cflags); \
1321 __ssa_src(instr, d, dflags); \
1322 instr->flags |= flag; \
1325 #define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name)
1326 #define INSTR4(name) __INSTR4(0, name, OPC_##name)
1328 /* cat0 instructions: */
1338 /* cat2 instructions, most 2 src but some 1 src: */
1386 /* cat3 instructions: */
1404 /* cat4 instructions: */
1413 /* cat5 instructions: */
1420 static inline struct ir3_instruction
*
1421 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1422 unsigned wrmask
, unsigned flags
, struct ir3_instruction
*samp_tex
,
1423 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1425 struct ir3_instruction
*sam
;
1427 sam
= ir3_instr_create(block
, opc
);
1428 sam
->flags
|= flags
| IR3_INSTR_S2EN
;
1429 __ssa_dst(sam
)->wrmask
= wrmask
;
1430 __ssa_src(sam
, samp_tex
, IR3_REG_HALF
);
1432 __ssa_src(sam
, src0
, 0)->wrmask
= (1 << (src0
->regs_count
- 1)) - 1;
1435 __ssa_src(sam
, src1
, 0)->wrmask
=(1 << (src1
->regs_count
- 1)) - 1;
1437 sam
->cat5
.type
= type
;
1442 /* cat6 instructions: */
1457 INSTR2(ATOMIC_CMPXCHG
)
1466 INSTR3F(G
, ATOMIC_ADD
)
1467 INSTR3F(G
, ATOMIC_SUB
)
1468 INSTR3F(G
, ATOMIC_XCHG
)
1469 INSTR3F(G
, ATOMIC_INC
)
1470 INSTR3F(G
, ATOMIC_DEC
)
1471 INSTR3F(G
, ATOMIC_CMPXCHG
)
1472 INSTR3F(G
, ATOMIC_MIN
)
1473 INSTR3F(G
, ATOMIC_MAX
)
1474 INSTR3F(G
, ATOMIC_AND
)
1475 INSTR3F(G
, ATOMIC_OR
)
1476 INSTR3F(G
, ATOMIC_XOR
)
1481 INSTR4F(G
, ATOMIC_ADD
)
1482 INSTR4F(G
, ATOMIC_SUB
)
1483 INSTR4F(G
, ATOMIC_XCHG
)
1484 INSTR4F(G
, ATOMIC_INC
)
1485 INSTR4F(G
, ATOMIC_DEC
)
1486 INSTR4F(G
, ATOMIC_CMPXCHG
)
1487 INSTR4F(G
, ATOMIC_MIN
)
1488 INSTR4F(G
, ATOMIC_MAX
)
1489 INSTR4F(G
, ATOMIC_AND
)
1490 INSTR4F(G
, ATOMIC_OR
)
1491 INSTR4F(G
, ATOMIC_XOR
)
1496 /* cat7 instructions: */
1500 /* meta instructions: */
1501 INSTR0(META_TEX_PREFETCH
);
1503 /* ************************************************************************* */
1504 /* split this out or find some helper to use.. like main/bitset.h.. */
1510 typedef uint8_t regmask_t
[2 * MAX_REG
/ 8];
1512 static inline unsigned regmask_idx(struct ir3_register
*reg
)
1514 unsigned num
= (reg
->flags
& IR3_REG_RELATIV
) ? reg
->array
.offset
: reg
->num
;
1515 debug_assert(num
< MAX_REG
);
1516 if (reg
->flags
& IR3_REG_HALF
) {
1526 static inline void regmask_init(regmask_t
*regmask
)
1528 memset(regmask
, 0, sizeof(*regmask
));
1531 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1533 unsigned idx
= regmask_idx(reg
);
1534 if (reg
->flags
& IR3_REG_RELATIV
) {
1536 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1537 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1540 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1542 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1546 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1549 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1550 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1553 /* set bits in a if not set in b, conceptually:
1556 static inline void regmask_set_if_not(regmask_t
*a
,
1557 struct ir3_register
*reg
, regmask_t
*b
)
1559 unsigned idx
= regmask_idx(reg
);
1560 if (reg
->flags
& IR3_REG_RELATIV
) {
1562 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1563 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1564 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1567 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1569 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1570 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1574 static inline bool regmask_get(regmask_t
*regmask
,
1575 struct ir3_register
*reg
)
1577 unsigned idx
= regmask_idx(reg
);
1578 if (reg
->flags
& IR3_REG_RELATIV
) {
1580 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1581 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1585 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1587 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1593 /* ************************************************************************* */