2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "compiler/shader_enums.h"
32 #include "util/bitscan.h"
33 #include "util/list.h"
35 #include "util/u_debug.h"
37 #include "instr-a3xx.h"
39 /* low level intermediate representation of an adreno shader program */
43 struct ir3_instruction
;
49 uint16_t instrs_count
; /* expanded to account for rpt's */
50 uint16_t nops_count
; /* # of nop instructions, including nopN */
51 /* NOTE: max_reg, etc, does not include registers not touched
52 * by the shader (ie. vertex fetched via VFD_DECODE but not
55 int8_t max_reg
; /* highest GPR # used by shader */
59 /* number of sync bits: */
62 uint16_t last_baryf
; /* instruction # of last varying fetch */
67 IR3_REG_CONST
= 0x001,
68 IR3_REG_IMMED
= 0x002,
70 /* high registers are used for some things in compute shaders,
71 * for example. Seems to be for things that are global to all
72 * threads in a wave, so possibly these are global/shared by
73 * all the threads in the wave?
76 IR3_REG_RELATIV
= 0x010,
78 /* Most instructions, it seems, can do float abs/neg but not
79 * integer. The CP pass needs to know what is intended (int or
80 * float) in order to do the right thing. For this reason the
81 * abs/neg flags are split out into float and int variants. In
82 * addition, .b (bitwise) operations, the negate is actually a
83 * bitwise not, so split that out into a new flag to make it
92 IR3_REG_POS_INF
= 0x1000,
93 /* (ei) flag, end-input? Set on last bary, presumably to signal
94 * that the shader needs no more input:
97 /* meta-flags, for intermediate stages of IR, ie.
98 * before register assignment is done:
100 IR3_REG_SSA
= 0x4000, /* 'instr' is ptr to assigning instr */
101 IR3_REG_ARRAY
= 0x8000,
105 /* used for cat5 instructions, but also for internal/IR level
106 * tracking of what registers are read/written by an instruction.
107 * wrmask may be a bad name since it is used to represent both
108 * src and dst that touch multiple adjacent registers.
110 unsigned wrmask
: 16; /* up to vec16 */
112 /* for relative addressing, 32bits for array size is too small,
113 * but otoh we don't need to deal with disjoint sets, so instead
114 * use a simple size field (number of scalar components).
116 * Note the size field isn't important for relative const (since
117 * we don't have to do register allocation for constants).
121 bool merged
: 1; /* half-regs conflict with full regs (ie >= a6xx) */
124 * the component is in the low two bits of the reg #, so
125 * rN.x becomes: (N << 2) | x
140 /* For IR3_REG_SSA, src registers contain ptr back to assigning
143 * For IR3_REG_ARRAY, the pointer is back to the last dependent
144 * array access (although the net effect is the same, it points
145 * back to a previous instruction that we depend on).
147 struct ir3_instruction
*instr
;
151 * Stupid/simple growable array implementation:
153 #define DECLARE_ARRAY(type, name) \
154 unsigned name ## _count, name ## _sz; \
157 #define array_insert(ctx, arr, val) do { \
158 if (arr ## _count == arr ## _sz) { \
159 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
160 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
162 arr[arr ##_count++] = val; \
165 struct ir3_instruction
{
166 struct ir3_block
*block
;
169 /* (sy) flag is set on first instruction, and after sample
170 * instructions (probably just on RAW hazard).
172 IR3_INSTR_SY
= 0x001,
173 /* (ss) flag is set on first instruction, and first instruction
174 * to depend on the result of "long" instructions (RAW hazard):
176 * rcp, rsq, log2, exp2, sin, cos, sqrt
178 * It seems to synchronize until all in-flight instructions are
179 * completed, for example:
182 * add.f hr2.z, (neg)hr2.z, hc0.y
183 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
186 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
188 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
189 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
190 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
192 * The last mul.f does not have (ss) set, presumably because the
193 * (ss) on the previous instruction does the job.
195 * The blob driver also seems to set it on WAR hazards, although
196 * not really clear if this is needed or just blob compiler being
197 * sloppy. So far I haven't found a case where removing the (ss)
198 * causes problems for WAR hazard, but I could just be getting
202 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
205 IR3_INSTR_SS
= 0x002,
206 /* (jp) flag is set on jump targets:
208 IR3_INSTR_JP
= 0x004,
209 IR3_INSTR_UL
= 0x008,
210 IR3_INSTR_3D
= 0x010,
215 IR3_INSTR_S2EN
= 0x200,
217 IR3_INSTR_SAT
= 0x800,
218 /* meta-flags, for intermediate stages of IR, ie.
219 * before register assignment is done:
221 IR3_INSTR_MARK
= 0x1000,
222 IR3_INSTR_UNUSED
= 0x2000,
230 struct ir3_register
**regs
;
236 struct ir3_block
*target
;
239 type_t src_type
, dst_type
;
259 int iim_val
: 3; /* for ldgb/stgb, # of components */
264 unsigned w
: 1; /* write */
265 unsigned r
: 1; /* read */
266 unsigned l
: 1; /* local */
267 unsigned g
: 1; /* global */
269 /* for meta-instructions, just used to hold extra data
270 * before instruction scheduling, etc
273 int off
; /* component/offset */
276 /* for output collects, this maps back to the entry in the
277 * ir3_shader_variant::outputs table.
283 unsigned input_offset
;
286 /* maps back to entry in ir3_shader_variant::inputs table: */
288 /* for sysvals, identifies the sysval type. Mostly so we can
289 * identify the special cases where a sysval should not be DCE'd
290 * (currently, just pre-fs texture fetch)
292 gl_system_value sysval
;
296 /* transient values used during various algorithms: */
298 /* The instruction depth is the max dependency distance to output.
300 * You can also think of it as the "cost", if we did any sort of
301 * optimization for register footprint. Ie. a value that is just
302 * result of moving a const to a reg would have a low cost, so to
303 * it could make sense to duplicate the instruction at various
304 * points where the result is needed to reduce register footprint.
307 /* When we get to the RA stage, we no longer need depth, but
308 * we do need instruction's position/name:
316 /* used for per-pass extra instruction data.
318 * TODO we should remove the per-pass data like this and 'use_count'
319 * and do something similar to what RA does w/ ir3_ra_instr_data..
320 * ie. use the ir3_count_instructions pass, and then use instr->ip
321 * to index into a table of pass-private data.
325 int sun
; /* Sethi–Ullman number, used by sched */
326 int use_count
; /* currently just updated/used by cp */
328 /* Used during CP and RA stages. For collect and shader inputs/
329 * outputs where we need a sequence of consecutive registers,
330 * keep track of each src instructions left (ie 'n-1') and right
331 * (ie 'n+1') neighbor. The front-end must insert enough mov's
332 * to ensure that each instruction has at most one left and at
333 * most one right neighbor. During the copy-propagation pass,
334 * we only remove mov's when we can preserve this constraint.
335 * And during the RA stage, we use the neighbor information to
336 * allocate a block of registers in one shot.
338 * TODO: maybe just add something like:
339 * struct ir3_instruction_ref {
340 * struct ir3_instruction *instr;
344 * Or can we get away without the refcnt stuff? It seems like
345 * it should be overkill.. the problem is if, potentially after
346 * already eliminating some mov's, if you have a single mov that
347 * needs to be grouped with it's neighbors in two different
348 * places (ex. shader output and a collect).
351 struct ir3_instruction
*left
, *right
;
352 uint16_t left_cnt
, right_cnt
;
355 /* an instruction can reference at most one address register amongst
356 * it's src/dst registers. Beyond that, you need to insert mov's.
358 * NOTE: do not write this directly, use ir3_instr_set_address()
360 struct ir3_instruction
*address
;
362 /* Tracking for additional dependent instructions. Used to handle
363 * barriers, WAR hazards for arrays/SSBOs/etc.
365 DECLARE_ARRAY(struct ir3_instruction
*, deps
);
368 * From PoV of instruction scheduling, not execution (ie. ignores global/
369 * local distinction):
370 * shared image atomic SSBO everything
371 * barrier()/ - R/W R/W R/W R/W X
372 * groupMemoryBarrier()
373 * memoryBarrier() - R/W R/W
374 * (but only images declared coherent?)
375 * memoryBarrierAtomic() - R/W
376 * memoryBarrierBuffer() - R/W
377 * memoryBarrierImage() - R/W
378 * memoryBarrierShared() - R/W
380 * TODO I think for SSBO/image/shared, in cases where we can determine
381 * which variable is accessed, we don't need to care about accesses to
382 * different variables (unless declared coherent??)
385 IR3_BARRIER_EVERYTHING
= 1 << 0,
386 IR3_BARRIER_SHARED_R
= 1 << 1,
387 IR3_BARRIER_SHARED_W
= 1 << 2,
388 IR3_BARRIER_IMAGE_R
= 1 << 3,
389 IR3_BARRIER_IMAGE_W
= 1 << 4,
390 IR3_BARRIER_BUFFER_R
= 1 << 5,
391 IR3_BARRIER_BUFFER_W
= 1 << 6,
392 IR3_BARRIER_ARRAY_R
= 1 << 7,
393 IR3_BARRIER_ARRAY_W
= 1 << 8,
394 } barrier_class
, barrier_conflict
;
396 /* Entry in ir3_block's instruction list: */
397 struct list_head node
;
403 // TODO only computerator/assembler:
407 static inline struct ir3_instruction
*
408 ir3_neighbor_first(struct ir3_instruction
*instr
)
411 while (instr
->cp
.left
) {
412 instr
= instr
->cp
.left
;
413 if (++cnt
> 0xffff) {
421 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
425 debug_assert(!instr
->cp
.left
);
427 while (instr
->cp
.right
) {
429 instr
= instr
->cp
.right
;
440 struct ir3_compiler
*compiler
;
441 gl_shader_stage type
;
443 DECLARE_ARRAY(struct ir3_instruction
*, inputs
);
444 DECLARE_ARRAY(struct ir3_instruction
*, outputs
);
446 /* Track bary.f (and ldlv) instructions.. this is needed in
447 * scheduling to ensure that all varying fetches happen before
448 * any potential kill instructions. The hw gets grumpy if all
449 * threads in a group are killed before the last bary.f gets
450 * a chance to signal end of input (ei).
452 DECLARE_ARRAY(struct ir3_instruction
*, baryfs
);
454 /* Track all indirect instructions (read and write). To avoid
455 * deadlock scenario where an address register gets scheduled,
456 * but other dependent src instructions cannot be scheduled due
457 * to dependency on a *different* address register value, the
458 * scheduler needs to ensure that all dependencies other than
459 * the instruction other than the address register are scheduled
460 * before the one that writes the address register. Having a
461 * convenient list of instructions that reference some address
462 * register simplifies this.
464 DECLARE_ARRAY(struct ir3_instruction
*, indirects
);
466 /* and same for instructions that consume predicate register: */
467 DECLARE_ARRAY(struct ir3_instruction
*, predicates
);
469 /* Track texture sample instructions which need texture state
470 * patched in (for astc-srgb workaround):
472 DECLARE_ARRAY(struct ir3_instruction
*, astc_srgb
);
474 /* List of blocks: */
475 struct list_head block_list
;
477 /* List of ir3_array's: */
478 struct list_head array_list
;
480 unsigned max_sun
; /* max Sethi–Ullman number */
483 unsigned block_count
, instr_count
;
488 struct list_head node
;
492 struct nir_register
*r
;
494 /* To avoid array write's from getting DCE'd, keep track of the
495 * most recent write. Any array access depends on the most
496 * recent write. This way, nothing depends on writes after the
497 * last read. But all the writes that happen before that have
498 * something depending on them
500 struct ir3_instruction
*last_write
;
502 /* extra stuff used in RA pass: */
503 unsigned base
; /* base vreg name */
504 unsigned reg
; /* base physical reg */
505 uint16_t start_ip
, end_ip
;
507 /* Indicates if half-precision */
511 struct ir3_array
* ir3_lookup_array(struct ir3
*ir
, unsigned id
);
514 struct list_head node
;
517 const struct nir_block
*nblock
;
519 struct list_head instr_list
; /* list of ir3_instruction */
521 /* each block has either one or two successors.. in case of
522 * two successors, 'condition' decides which one to follow.
523 * A block preceding an if/else has two successors.
525 struct ir3_instruction
*condition
;
526 struct ir3_block
*successors
[2];
528 struct set
*predecessors
; /* set of ir3_block */
530 uint16_t start_ip
, end_ip
;
532 /* Track instructions which do not write a register but other-
533 * wise must not be discarded (such as kill, stg, etc)
535 DECLARE_ARRAY(struct ir3_instruction
*, keeps
);
537 /* used for per-pass extra block data. Mainly used right
538 * now in RA step to track livein/liveout.
547 static inline uint32_t
548 block_id(struct ir3_block
*block
)
551 return block
->serialno
;
553 return (uint32_t)(unsigned long)block
;
557 struct ir3
* ir3_create(struct ir3_compiler
*compiler
, gl_shader_stage type
);
558 void ir3_destroy(struct ir3
*shader
);
559 void * ir3_assemble(struct ir3
*shader
,
560 struct ir3_info
*info
, uint32_t gpu_id
);
561 void * ir3_alloc(struct ir3
*shader
, int sz
);
563 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
565 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
);
566 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
567 opc_t opc
, int nreg
);
568 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
569 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
);
570 const char *ir3_instr_name(struct ir3_instruction
*instr
);
572 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
574 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
575 struct ir3_register
*reg
);
577 void ir3_instr_set_address(struct ir3_instruction
*instr
,
578 struct ir3_instruction
*addr
);
580 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
582 if (instr
->flags
& IR3_INSTR_MARK
)
583 return true; /* already visited */
584 instr
->flags
|= IR3_INSTR_MARK
;
588 void ir3_block_clear_mark(struct ir3_block
*block
);
589 void ir3_clear_mark(struct ir3
*shader
);
591 unsigned ir3_count_instructions(struct ir3
*ir
);
593 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
594 struct ir3_register
*reg
)
597 for (i
= 0; i
< instr
->regs_count
; i
++)
598 if (reg
== instr
->regs
[i
])
604 #define MAX_ARRAYS 16
612 static inline uint32_t regid(int num
, int comp
)
614 return (num
<< 2) | (comp
& 0x3);
617 static inline uint32_t reg_num(struct ir3_register
*reg
)
619 return reg
->num
>> 2;
622 static inline uint32_t reg_comp(struct ir3_register
*reg
)
624 return reg
->num
& 0x3;
627 #define INVALID_REG regid(63, 0)
628 #define VALIDREG(r) ((r) != INVALID_REG)
629 #define CONDREG(r, val) COND(VALIDREG(r), (val))
631 static inline bool is_flow(struct ir3_instruction
*instr
)
633 return (opc_cat(instr
->opc
) == 0);
636 static inline bool is_kill(struct ir3_instruction
*instr
)
638 return instr
->opc
== OPC_KILL
;
641 static inline bool is_nop(struct ir3_instruction
*instr
)
643 return instr
->opc
== OPC_NOP
;
646 static inline bool is_same_type_reg(struct ir3_register
*reg1
,
647 struct ir3_register
*reg2
)
649 unsigned type_reg1
= (reg1
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
650 unsigned type_reg2
= (reg2
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
652 if (type_reg1
^ type_reg2
)
658 /* Is it a non-transformative (ie. not type changing) mov? This can
659 * also include absneg.s/absneg.f, which for the most part can be
660 * treated as a mov (single src argument).
662 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
664 struct ir3_register
*dst
;
666 switch (instr
->opc
) {
668 if (instr
->cat1
.src_type
!= instr
->cat1
.dst_type
)
670 /* If the type of dest reg and src reg are different,
671 * it shouldn't be considered as same type mov
673 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
678 if (instr
->flags
& IR3_INSTR_SAT
)
680 /* If the type of dest reg and src reg are different,
681 * it shouldn't be considered as same type mov
683 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
690 dst
= instr
->regs
[0];
692 /* mov's that write to a0.x or p0.x are special: */
693 if (dst
->num
== regid(REG_P0
, 0))
695 if (dst
->num
== regid(REG_A0
, 0))
698 if (dst
->flags
& (IR3_REG_RELATIV
| IR3_REG_ARRAY
))
704 /* A move from const, which changes size but not type, can also be
705 * folded into dest instruction in some cases.
707 static inline bool is_const_mov(struct ir3_instruction
*instr
)
709 if (instr
->opc
!= OPC_MOV
)
712 if (!(instr
->regs
[1]->flags
& IR3_REG_CONST
))
715 type_t src_type
= instr
->cat1
.src_type
;
716 type_t dst_type
= instr
->cat1
.dst_type
;
718 return (type_float(src_type
) && type_float(dst_type
)) ||
719 (type_uint(src_type
) && type_uint(dst_type
)) ||
720 (type_sint(src_type
) && type_sint(dst_type
));
723 static inline bool is_alu(struct ir3_instruction
*instr
)
725 return (1 <= opc_cat(instr
->opc
)) && (opc_cat(instr
->opc
) <= 3);
728 static inline bool is_sfu(struct ir3_instruction
*instr
)
730 return (opc_cat(instr
->opc
) == 4);
733 static inline bool is_tex(struct ir3_instruction
*instr
)
735 return (opc_cat(instr
->opc
) == 5);
738 static inline bool is_tex_or_prefetch(struct ir3_instruction
*instr
)
740 return is_tex(instr
) || (instr
->opc
== OPC_META_TEX_PREFETCH
);
743 static inline bool is_mem(struct ir3_instruction
*instr
)
745 return (opc_cat(instr
->opc
) == 6);
748 static inline bool is_barrier(struct ir3_instruction
*instr
)
750 return (opc_cat(instr
->opc
) == 7);
754 is_half(struct ir3_instruction
*instr
)
756 return !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
760 is_high(struct ir3_instruction
*instr
)
762 return !!(instr
->regs
[0]->flags
& IR3_REG_HIGH
);
766 is_store(struct ir3_instruction
*instr
)
768 /* these instructions, the "destination" register is
769 * actually a source, the address to store to.
771 switch (instr
->opc
) {
786 static inline bool is_load(struct ir3_instruction
*instr
)
788 switch (instr
->opc
) {
798 /* probably some others too.. */
805 static inline bool is_input(struct ir3_instruction
*instr
)
807 /* in some cases, ldlv is used to fetch varying without
808 * interpolation.. fortunately inloc is the first src
809 * register in either case
811 switch (instr
->opc
) {
820 static inline bool is_bool(struct ir3_instruction
*instr
)
822 switch (instr
->opc
) {
832 static inline bool is_meta(struct ir3_instruction
*instr
)
834 return (opc_cat(instr
->opc
) == -1);
837 static inline unsigned dest_regs(struct ir3_instruction
*instr
)
839 if ((instr
->regs_count
== 0) || is_store(instr
) || is_flow(instr
))
842 return util_last_bit(instr
->regs
[0]->wrmask
);
845 static inline bool writes_addr(struct ir3_instruction
*instr
)
847 if (instr
->regs_count
> 0) {
848 struct ir3_register
*dst
= instr
->regs
[0];
849 return reg_num(dst
) == REG_A0
;
854 static inline bool writes_pred(struct ir3_instruction
*instr
)
856 if (instr
->regs_count
> 0) {
857 struct ir3_register
*dst
= instr
->regs
[0];
858 return reg_num(dst
) == REG_P0
;
863 /* returns defining instruction for reg */
864 /* TODO better name */
865 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
867 if (reg
->flags
& (IR3_REG_SSA
| IR3_REG_ARRAY
)) {
873 static inline bool conflicts(struct ir3_instruction
*a
,
874 struct ir3_instruction
*b
)
876 return (a
&& b
) && (a
!= b
);
879 static inline bool reg_gpr(struct ir3_register
*r
)
881 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
883 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
888 static inline type_t
half_type(type_t type
)
891 case TYPE_F32
: return TYPE_F16
;
892 case TYPE_U32
: return TYPE_U16
;
893 case TYPE_S32
: return TYPE_S16
;
904 /* some cat2 instructions (ie. those which are not float) can embed an
907 static inline bool ir3_cat2_int(opc_t opc
)
947 static inline bool ir3_cat2_float(opc_t opc
)
970 static inline bool ir3_cat3_float(opc_t opc
)
983 /* map cat2 instruction to valid abs/neg flags: */
984 static inline unsigned ir3_cat2_absneg(opc_t opc
)
1001 return IR3_REG_FABS
| IR3_REG_FNEG
;
1022 return IR3_REG_SABS
| IR3_REG_SNEG
;
1036 return IR3_REG_BNOT
;
1043 /* map cat3 instructions to valid abs/neg flags: */
1044 static inline unsigned ir3_cat3_absneg(opc_t opc
)
1051 return IR3_REG_FNEG
;
1063 /* neg *may* work on 3rd src.. */
1073 #define MASK(n) ((1 << (n)) - 1)
1075 /* iterator for an instructions's sources (reg), also returns src #: */
1076 #define foreach_src_n(__srcreg, __n, __instr) \
1077 if ((__instr)->regs_count) \
1078 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
1079 if ((__srcreg = (__instr)->regs[__n + 1]))
1081 /* iterator for an instructions's sources (reg): */
1082 #define foreach_src(__srcreg, __instr) \
1083 foreach_src_n(__srcreg, __i, __instr)
1085 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
1087 unsigned cnt
= instr
->regs_count
+ instr
->deps_count
;
1093 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
1095 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1096 return instr
->address
;
1097 if (n
>= instr
->regs_count
)
1098 return instr
->deps
[n
- instr
->regs_count
];
1099 return ssa(instr
->regs
[n
]);
1102 static inline bool __is_false_dep(struct ir3_instruction
*instr
, unsigned n
)
1104 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1106 if (n
>= instr
->regs_count
)
1111 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
1113 /* iterator for an instruction's SSA sources (instr), also returns src #: */
1114 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
1115 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
1116 if ((__srcinst = __ssa_src_n(__instr, __n)))
1118 /* iterator for an instruction's SSA sources (instr): */
1119 #define foreach_ssa_src(__srcinst, __instr) \
1120 foreach_ssa_src_n(__srcinst, __i, __instr)
1122 /* iterators for shader inputs: */
1123 #define foreach_input_n(__ininstr, __cnt, __ir) \
1124 for (unsigned __cnt = 0; __cnt < (__ir)->inputs_count; __cnt++) \
1125 if ((__ininstr = (__ir)->inputs[__cnt]))
1126 #define foreach_input(__ininstr, __ir) \
1127 foreach_input_n(__ininstr, __i, __ir)
1129 /* iterators for shader outputs: */
1130 #define foreach_output_n(__outinstr, __cnt, __ir) \
1131 for (unsigned __cnt = 0; __cnt < (__ir)->outputs_count; __cnt++) \
1132 if ((__outinstr = (__ir)->outputs[__cnt]))
1133 #define foreach_output(__outinstr, __ir) \
1134 foreach_output_n(__outinstr, __i, __ir)
1136 /* iterators for instructions: */
1137 #define foreach_instr(__instr, __list) \
1138 list_for_each_entry(struct ir3_instruction, __instr, __list, node)
1139 #define foreach_instr_rev(__instr, __list) \
1140 list_for_each_entry_rev(struct ir3_instruction, __instr, __list, node)
1141 #define foreach_instr_safe(__instr, __list) \
1142 list_for_each_entry_safe(struct ir3_instruction, __instr, __list, node)
1144 /* iterators for blocks: */
1145 #define foreach_block(__block, __list) \
1146 list_for_each_entry(struct ir3_block, __block, __list, node)
1147 #define foreach_block_safe(__block, __list) \
1148 list_for_each_entry_safe(struct ir3_block, __block, __list, node)
1150 /* iterators for arrays: */
1151 #define foreach_array(__array, __list) \
1152 list_for_each_entry(struct ir3_array, __array, __list, node)
1155 void ir3_print(struct ir3
*ir
);
1156 void ir3_print_instr(struct ir3_instruction
*instr
);
1158 /* delay calculation: */
1159 int ir3_delayslots(struct ir3_instruction
*assigner
,
1160 struct ir3_instruction
*consumer
, unsigned n
, bool soft
);
1161 unsigned ir3_delay_calc(struct ir3_block
*block
, struct ir3_instruction
*instr
,
1162 bool soft
, bool pred
);
1163 void ir3_remove_nops(struct ir3
*ir
);
1165 /* depth calculation: */
1166 struct ir3_shader_variant
;
1167 void ir3_insert_by_depth(struct ir3_instruction
*instr
, struct list_head
*list
);
1168 void ir3_depth(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1170 /* fp16 conversion folding */
1171 void ir3_cf(struct ir3
*ir
);
1173 /* copy-propagate: */
1174 void ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1176 /* group neighbors and insert mov's to resolve conflicts: */
1177 void ir3_group(struct ir3
*ir
);
1179 /* Sethi–Ullman numbering: */
1180 void ir3_sun(struct ir3
*ir
);
1183 void ir3_sched_add_deps(struct ir3
*ir
);
1184 int ir3_sched(struct ir3
*ir
);
1187 int ir3_postsched(struct ir3_context
*ctx
);
1189 bool ir3_a6xx_fixup_atomic_dests(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1191 /* register assignment: */
1192 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(struct ir3_compiler
*compiler
);
1193 int ir3_ra(struct ir3_shader_variant
*v
, struct ir3_instruction
**precolor
, unsigned nprecolor
);
1196 void ir3_legalize(struct ir3
*ir
, struct ir3_shader_variant
*so
, int *max_bary
);
1198 /* ************************************************************************* */
1199 /* instruction helpers */
1201 /* creates SSA src of correct type (ie. half vs full precision) */
1202 static inline struct ir3_register
* __ssa_src(struct ir3_instruction
*instr
,
1203 struct ir3_instruction
*src
, unsigned flags
)
1205 struct ir3_register
*reg
;
1206 if (src
->regs
[0]->flags
& IR3_REG_HALF
)
1207 flags
|= IR3_REG_HALF
;
1208 reg
= ir3_reg_create(instr
, 0, IR3_REG_SSA
| flags
);
1210 reg
->wrmask
= src
->regs
[0]->wrmask
;
1214 static inline struct ir3_register
* __ssa_dst(struct ir3_instruction
*instr
)
1216 struct ir3_register
*reg
= ir3_reg_create(instr
, 0, 0);
1217 reg
->flags
|= IR3_REG_SSA
;
1221 static inline struct ir3_instruction
*
1222 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
1224 struct ir3_instruction
*mov
;
1225 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1227 mov
= ir3_instr_create(block
, OPC_MOV
);
1228 mov
->cat1
.src_type
= type
;
1229 mov
->cat1
.dst_type
= type
;
1230 __ssa_dst(mov
)->flags
|= flags
;
1231 ir3_reg_create(mov
, 0, IR3_REG_IMMED
| flags
)->uim_val
= val
;
1236 static inline struct ir3_instruction
*
1237 create_immed(struct ir3_block
*block
, uint32_t val
)
1239 return create_immed_typed(block
, val
, TYPE_U32
);
1242 static inline struct ir3_instruction
*
1243 create_uniform_typed(struct ir3_block
*block
, unsigned n
, type_t type
)
1245 struct ir3_instruction
*mov
;
1246 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1248 mov
= ir3_instr_create(block
, OPC_MOV
);
1249 mov
->cat1
.src_type
= type
;
1250 mov
->cat1
.dst_type
= type
;
1251 __ssa_dst(mov
)->flags
|= flags
;
1252 ir3_reg_create(mov
, n
, IR3_REG_CONST
| flags
);
1257 static inline struct ir3_instruction
*
1258 create_uniform(struct ir3_block
*block
, unsigned n
)
1260 return create_uniform_typed(block
, n
, TYPE_F32
);
1263 static inline struct ir3_instruction
*
1264 create_uniform_indirect(struct ir3_block
*block
, int n
,
1265 struct ir3_instruction
*address
)
1267 struct ir3_instruction
*mov
;
1269 mov
= ir3_instr_create(block
, OPC_MOV
);
1270 mov
->cat1
.src_type
= TYPE_U32
;
1271 mov
->cat1
.dst_type
= TYPE_U32
;
1273 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
1275 ir3_instr_set_address(mov
, address
);
1280 static inline struct ir3_instruction
*
1281 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
1283 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1285 if (src
->regs
[0]->flags
& IR3_REG_ARRAY
) {
1286 struct ir3_register
*src_reg
= __ssa_src(instr
, src
, IR3_REG_ARRAY
);
1287 src_reg
->array
= src
->regs
[0]->array
;
1289 __ssa_src(instr
, src
, src
->regs
[0]->flags
& IR3_REG_HIGH
);
1291 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_RELATIV
));
1292 instr
->cat1
.src_type
= type
;
1293 instr
->cat1
.dst_type
= type
;
1297 static inline struct ir3_instruction
*
1298 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
1299 type_t src_type
, type_t dst_type
)
1301 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1302 unsigned dst_flags
= (type_size(dst_type
) < 32) ? IR3_REG_HALF
: 0;
1303 unsigned src_flags
= (type_size(src_type
) < 32) ? IR3_REG_HALF
: 0;
1305 debug_assert((src
->regs
[0]->flags
& IR3_REG_HALF
) == src_flags
);
1307 __ssa_dst(instr
)->flags
|= dst_flags
;
1308 __ssa_src(instr
, src
, 0);
1309 instr
->cat1
.src_type
= src_type
;
1310 instr
->cat1
.dst_type
= dst_type
;
1311 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_ARRAY
));
1315 static inline struct ir3_instruction
*
1316 ir3_NOP(struct ir3_block
*block
)
1318 return ir3_instr_create(block
, OPC_NOP
);
1321 #define IR3_INSTR_0 0
1323 #define __INSTR0(flag, name, opc) \
1324 static inline struct ir3_instruction * \
1325 ir3_##name(struct ir3_block *block) \
1327 struct ir3_instruction *instr = \
1328 ir3_instr_create(block, opc); \
1329 instr->flags |= flag; \
1332 #define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name)
1333 #define INSTR0(name) __INSTR0(0, name, OPC_##name)
1335 #define __INSTR1(flag, name, opc) \
1336 static inline struct ir3_instruction * \
1337 ir3_##name(struct ir3_block *block, \
1338 struct ir3_instruction *a, unsigned aflags) \
1340 struct ir3_instruction *instr = \
1341 ir3_instr_create(block, opc); \
1343 __ssa_src(instr, a, aflags); \
1344 instr->flags |= flag; \
1347 #define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name)
1348 #define INSTR1(name) __INSTR1(0, name, OPC_##name)
1350 #define __INSTR2(flag, name, opc) \
1351 static inline struct ir3_instruction * \
1352 ir3_##name(struct ir3_block *block, \
1353 struct ir3_instruction *a, unsigned aflags, \
1354 struct ir3_instruction *b, unsigned bflags) \
1356 struct ir3_instruction *instr = \
1357 ir3_instr_create(block, opc); \
1359 __ssa_src(instr, a, aflags); \
1360 __ssa_src(instr, b, bflags); \
1361 instr->flags |= flag; \
1364 #define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name)
1365 #define INSTR2(name) __INSTR2(0, name, OPC_##name)
1367 #define __INSTR3(flag, name, opc) \
1368 static inline struct ir3_instruction * \
1369 ir3_##name(struct ir3_block *block, \
1370 struct ir3_instruction *a, unsigned aflags, \
1371 struct ir3_instruction *b, unsigned bflags, \
1372 struct ir3_instruction *c, unsigned cflags) \
1374 struct ir3_instruction *instr = \
1375 ir3_instr_create2(block, opc, 4); \
1377 __ssa_src(instr, a, aflags); \
1378 __ssa_src(instr, b, bflags); \
1379 __ssa_src(instr, c, cflags); \
1380 instr->flags |= flag; \
1383 #define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name)
1384 #define INSTR3(name) __INSTR3(0, name, OPC_##name)
1386 #define __INSTR4(flag, name, opc) \
1387 static inline struct ir3_instruction * \
1388 ir3_##name(struct ir3_block *block, \
1389 struct ir3_instruction *a, unsigned aflags, \
1390 struct ir3_instruction *b, unsigned bflags, \
1391 struct ir3_instruction *c, unsigned cflags, \
1392 struct ir3_instruction *d, unsigned dflags) \
1394 struct ir3_instruction *instr = \
1395 ir3_instr_create2(block, opc, 5); \
1397 __ssa_src(instr, a, aflags); \
1398 __ssa_src(instr, b, bflags); \
1399 __ssa_src(instr, c, cflags); \
1400 __ssa_src(instr, d, dflags); \
1401 instr->flags |= flag; \
1404 #define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name)
1405 #define INSTR4(name) __INSTR4(0, name, OPC_##name)
1407 /* cat0 instructions: */
1418 /* cat2 instructions, most 2 src but some 1 src: */
1466 /* cat3 instructions: */
1484 /* cat4 instructions: */
1496 /* cat5 instructions: */
1505 static inline struct ir3_instruction
*
1506 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1507 unsigned wrmask
, unsigned flags
, struct ir3_instruction
*samp_tex
,
1508 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1510 struct ir3_instruction
*sam
;
1512 sam
= ir3_instr_create(block
, opc
);
1513 sam
->flags
|= flags
| IR3_INSTR_S2EN
;
1514 __ssa_dst(sam
)->wrmask
= wrmask
;
1515 __ssa_src(sam
, samp_tex
, IR3_REG_HALF
);
1517 __ssa_src(sam
, src0
, 0)->wrmask
= (1 << (src0
->regs_count
- 1)) - 1;
1520 __ssa_src(sam
, src1
, 0)->wrmask
=(1 << (src1
->regs_count
- 1)) - 1;
1522 sam
->cat5
.type
= type
;
1527 /* cat6 instructions: */
1542 INSTR2(ATOMIC_CMPXCHG
)
1551 INSTR3F(G
, ATOMIC_ADD
)
1552 INSTR3F(G
, ATOMIC_SUB
)
1553 INSTR3F(G
, ATOMIC_XCHG
)
1554 INSTR3F(G
, ATOMIC_INC
)
1555 INSTR3F(G
, ATOMIC_DEC
)
1556 INSTR3F(G
, ATOMIC_CMPXCHG
)
1557 INSTR3F(G
, ATOMIC_MIN
)
1558 INSTR3F(G
, ATOMIC_MAX
)
1559 INSTR3F(G
, ATOMIC_AND
)
1560 INSTR3F(G
, ATOMIC_OR
)
1561 INSTR3F(G
, ATOMIC_XOR
)
1566 INSTR4F(G
, ATOMIC_ADD
)
1567 INSTR4F(G
, ATOMIC_SUB
)
1568 INSTR4F(G
, ATOMIC_XCHG
)
1569 INSTR4F(G
, ATOMIC_INC
)
1570 INSTR4F(G
, ATOMIC_DEC
)
1571 INSTR4F(G
, ATOMIC_CMPXCHG
)
1572 INSTR4F(G
, ATOMIC_MIN
)
1573 INSTR4F(G
, ATOMIC_MAX
)
1574 INSTR4F(G
, ATOMIC_AND
)
1575 INSTR4F(G
, ATOMIC_OR
)
1576 INSTR4F(G
, ATOMIC_XOR
)
1581 /* cat7 instructions: */
1585 /* meta instructions: */
1586 INSTR0(META_TEX_PREFETCH
);
1588 /* ************************************************************************* */
1589 /* split this out or find some helper to use.. like main/bitset.h.. */
1592 #include "util/bitset.h"
1596 typedef BITSET_DECLARE(regmask_t
, 2 * MAX_REG
);
1599 __regmask_get(regmask_t
*regmask
, struct ir3_register
*reg
, unsigned n
)
1602 /* a6xx+ case, with merged register file, we track things in terms
1603 * of half-precision registers, with a full precisions register
1604 * using two half-precision slots:
1606 if (reg
->flags
& IR3_REG_HALF
) {
1607 return BITSET_TEST(*regmask
, n
);
1610 return BITSET_TEST(*regmask
, n
) || BITSET_TEST(*regmask
, n
+1);
1613 /* pre a6xx case, with separate register file for half and full
1616 if (reg
->flags
& IR3_REG_HALF
)
1618 return BITSET_TEST(*regmask
, n
);
1623 __regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
, unsigned n
)
1626 /* a6xx+ case, with merged register file, we track things in terms
1627 * of half-precision registers, with a full precisions register
1628 * using two half-precision slots:
1630 if (reg
->flags
& IR3_REG_HALF
) {
1631 BITSET_SET(*regmask
, n
);
1634 BITSET_SET(*regmask
, n
);
1635 BITSET_SET(*regmask
, n
+1);
1638 /* pre a6xx case, with separate register file for half and full
1641 if (reg
->flags
& IR3_REG_HALF
)
1643 BITSET_SET(*regmask
, n
);
1647 static inline void regmask_init(regmask_t
*regmask
)
1649 memset(regmask
, 0, sizeof(*regmask
));
1652 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1654 if (reg
->flags
& IR3_REG_RELATIV
) {
1655 for (unsigned i
= 0; i
< reg
->size
; i
++)
1656 __regmask_set(regmask
, reg
, reg
->array
.offset
+ i
);
1658 for (unsigned mask
= reg
->wrmask
, n
= reg
->num
; mask
; mask
>>= 1, n
++)
1660 __regmask_set(regmask
, reg
, n
);
1664 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1667 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1668 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1671 static inline bool regmask_get(regmask_t
*regmask
,
1672 struct ir3_register
*reg
)
1674 if (reg
->flags
& IR3_REG_RELATIV
) {
1675 for (unsigned i
= 0; i
< reg
->size
; i
++)
1676 if (__regmask_get(regmask
, reg
, reg
->array
.offset
+ i
))
1679 for (unsigned mask
= reg
->wrmask
, n
= reg
->num
; mask
; mask
>>= 1, n
++)
1681 if (__regmask_get(regmask
, reg
, n
))
1687 /* ************************************************************************* */