2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "compiler/shader_enums.h"
32 #include "util/bitscan.h"
33 #include "util/list.h"
34 #include "util/u_debug.h"
36 #include "instr-a3xx.h"
38 /* low level intermediate representation of an adreno shader program */
42 struct ir3_instruction
;
48 uint16_t instrs_count
; /* expanded to account for rpt's */
49 /* NOTE: max_reg, etc, does not include registers not touched
50 * by the shader (ie. vertex fetched via VFD_DECODE but not
53 int8_t max_reg
; /* highest GPR # used by shader */
57 /* number of sync bits: */
63 IR3_REG_CONST
= 0x001,
64 IR3_REG_IMMED
= 0x002,
66 /* high registers are used for some things in compute shaders,
67 * for example. Seems to be for things that are global to all
68 * threads in a wave, so possibly these are global/shared by
69 * all the threads in the wave?
72 IR3_REG_RELATIV
= 0x010,
74 /* Most instructions, it seems, can do float abs/neg but not
75 * integer. The CP pass needs to know what is intended (int or
76 * float) in order to do the right thing. For this reason the
77 * abs/neg flags are split out into float and int variants. In
78 * addition, .b (bitwise) operations, the negate is actually a
79 * bitwise not, so split that out into a new flag to make it
88 IR3_REG_POS_INF
= 0x1000,
89 /* (ei) flag, end-input? Set on last bary, presumably to signal
90 * that the shader needs no more input:
93 /* meta-flags, for intermediate stages of IR, ie.
94 * before register assignment is done:
96 IR3_REG_SSA
= 0x4000, /* 'instr' is ptr to assigning instr */
97 IR3_REG_ARRAY
= 0x8000,
101 bool merged
: 1; /* half-regs conflict with full regs (ie >= a6xx) */
104 * the component is in the low two bits of the reg #, so
105 * rN.x becomes: (N << 2) | x
120 /* For IR3_REG_SSA, src registers contain ptr back to assigning
123 * For IR3_REG_ARRAY, the pointer is back to the last dependent
124 * array access (although the net effect is the same, it points
125 * back to a previous instruction that we depend on).
127 struct ir3_instruction
*instr
;
130 /* used for cat5 instructions, but also for internal/IR level
131 * tracking of what registers are read/written by an instruction.
132 * wrmask may be a bad name since it is used to represent both
133 * src and dst that touch multiple adjacent registers.
136 /* for relative addressing, 32bits for array size is too small,
137 * but otoh we don't need to deal with disjoint sets, so instead
138 * use a simple size field (number of scalar components).
145 * Stupid/simple growable array implementation:
147 #define DECLARE_ARRAY(type, name) \
148 unsigned name ## _count, name ## _sz; \
151 #define array_insert(ctx, arr, val) do { \
152 if (arr ## _count == arr ## _sz) { \
153 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
154 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
156 arr[arr ##_count++] = val; \
159 struct ir3_instruction
{
160 struct ir3_block
*block
;
163 /* (sy) flag is set on first instruction, and after sample
164 * instructions (probably just on RAW hazard).
166 IR3_INSTR_SY
= 0x001,
167 /* (ss) flag is set on first instruction, and first instruction
168 * to depend on the result of "long" instructions (RAW hazard):
170 * rcp, rsq, log2, exp2, sin, cos, sqrt
172 * It seems to synchronize until all in-flight instructions are
173 * completed, for example:
176 * add.f hr2.z, (neg)hr2.z, hc0.y
177 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
180 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
182 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
183 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
184 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
186 * The last mul.f does not have (ss) set, presumably because the
187 * (ss) on the previous instruction does the job.
189 * The blob driver also seems to set it on WAR hazards, although
190 * not really clear if this is needed or just blob compiler being
191 * sloppy. So far I haven't found a case where removing the (ss)
192 * causes problems for WAR hazard, but I could just be getting
196 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
199 IR3_INSTR_SS
= 0x002,
200 /* (jp) flag is set on jump targets:
202 IR3_INSTR_JP
= 0x004,
203 IR3_INSTR_UL
= 0x008,
204 IR3_INSTR_3D
= 0x010,
209 IR3_INSTR_S2EN
= 0x200,
211 IR3_INSTR_SAT
= 0x800,
212 /* meta-flags, for intermediate stages of IR, ie.
213 * before register assignment is done:
215 IR3_INSTR_MARK
= 0x1000,
216 IR3_INSTR_UNUSED
= 0x2000,
224 struct ir3_register
**regs
;
230 struct ir3_block
*target
;
233 type_t src_type
, dst_type
;
253 int iim_val
: 3; /* for ldgb/stgb, # of components */
258 unsigned w
: 1; /* write */
259 unsigned r
: 1; /* read */
260 unsigned l
: 1; /* local */
261 unsigned g
: 1; /* global */
263 /* for meta-instructions, just used to hold extra data
264 * before instruction scheduling, etc
267 int off
; /* component/offset */
270 struct ir3_block
*block
;
274 /* transient values used during various algorithms: */
276 /* The instruction depth is the max dependency distance to output.
278 * You can also think of it as the "cost", if we did any sort of
279 * optimization for register footprint. Ie. a value that is just
280 * result of moving a const to a reg would have a low cost, so to
281 * it could make sense to duplicate the instruction at various
282 * points where the result is needed to reduce register footprint.
285 /* When we get to the RA stage, we no longer need depth, but
286 * we do need instruction's position/name:
294 /* used for per-pass extra instruction data.
296 * TODO we should remove the per-pass data like this and 'use_count'
297 * and do something similar to what RA does w/ ir3_ra_instr_data..
298 * ie. use the ir3_count_instructions pass, and then use instr->ip
299 * to index into a table of pass-private data.
303 int sun
; /* Sethi–Ullman number, used by sched */
304 int use_count
; /* currently just updated/used by cp */
306 /* Used during CP and RA stages. For fanin and shader inputs/
307 * outputs where we need a sequence of consecutive registers,
308 * keep track of each src instructions left (ie 'n-1') and right
309 * (ie 'n+1') neighbor. The front-end must insert enough mov's
310 * to ensure that each instruction has at most one left and at
311 * most one right neighbor. During the copy-propagation pass,
312 * we only remove mov's when we can preserve this constraint.
313 * And during the RA stage, we use the neighbor information to
314 * allocate a block of registers in one shot.
316 * TODO: maybe just add something like:
317 * struct ir3_instruction_ref {
318 * struct ir3_instruction *instr;
322 * Or can we get away without the refcnt stuff? It seems like
323 * it should be overkill.. the problem is if, potentially after
324 * already eliminating some mov's, if you have a single mov that
325 * needs to be grouped with it's neighbors in two different
326 * places (ex. shader output and a fanin).
329 struct ir3_instruction
*left
, *right
;
330 uint16_t left_cnt
, right_cnt
;
333 /* an instruction can reference at most one address register amongst
334 * it's src/dst registers. Beyond that, you need to insert mov's.
336 * NOTE: do not write this directly, use ir3_instr_set_address()
338 struct ir3_instruction
*address
;
340 /* Tracking for additional dependent instructions. Used to handle
341 * barriers, WAR hazards for arrays/SSBOs/etc.
343 DECLARE_ARRAY(struct ir3_instruction
*, deps
);
346 * From PoV of instruction scheduling, not execution (ie. ignores global/
347 * local distinction):
348 * shared image atomic SSBO everything
349 * barrier()/ - R/W R/W R/W R/W X
350 * groupMemoryBarrier()
351 * memoryBarrier() - R/W R/W
352 * (but only images declared coherent?)
353 * memoryBarrierAtomic() - R/W
354 * memoryBarrierBuffer() - R/W
355 * memoryBarrierImage() - R/W
356 * memoryBarrierShared() - R/W
358 * TODO I think for SSBO/image/shared, in cases where we can determine
359 * which variable is accessed, we don't need to care about accesses to
360 * different variables (unless declared coherent??)
363 IR3_BARRIER_EVERYTHING
= 1 << 0,
364 IR3_BARRIER_SHARED_R
= 1 << 1,
365 IR3_BARRIER_SHARED_W
= 1 << 2,
366 IR3_BARRIER_IMAGE_R
= 1 << 3,
367 IR3_BARRIER_IMAGE_W
= 1 << 4,
368 IR3_BARRIER_BUFFER_R
= 1 << 5,
369 IR3_BARRIER_BUFFER_W
= 1 << 6,
370 IR3_BARRIER_ARRAY_R
= 1 << 7,
371 IR3_BARRIER_ARRAY_W
= 1 << 8,
372 } barrier_class
, barrier_conflict
;
374 /* Entry in ir3_block's instruction list: */
375 struct list_head node
;
382 static inline struct ir3_instruction
*
383 ir3_neighbor_first(struct ir3_instruction
*instr
)
386 while (instr
->cp
.left
) {
387 instr
= instr
->cp
.left
;
388 if (++cnt
> 0xffff) {
396 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
400 debug_assert(!instr
->cp
.left
);
402 while (instr
->cp
.right
) {
404 instr
= instr
->cp
.right
;
415 struct ir3_compiler
*compiler
;
416 gl_shader_stage type
;
418 unsigned ninputs
, noutputs
;
419 struct ir3_instruction
**inputs
;
420 struct ir3_instruction
**outputs
;
422 /* Track bary.f (and ldlv) instructions.. this is needed in
423 * scheduling to ensure that all varying fetches happen before
424 * any potential kill instructions. The hw gets grumpy if all
425 * threads in a group are killed before the last bary.f gets
426 * a chance to signal end of input (ei).
428 DECLARE_ARRAY(struct ir3_instruction
*, baryfs
);
430 /* Track all indirect instructions (read and write). To avoid
431 * deadlock scenario where an address register gets scheduled,
432 * but other dependent src instructions cannot be scheduled due
433 * to dependency on a *different* address register value, the
434 * scheduler needs to ensure that all dependencies other than
435 * the instruction other than the address register are scheduled
436 * before the one that writes the address register. Having a
437 * convenient list of instructions that reference some address
438 * register simplifies this.
440 DECLARE_ARRAY(struct ir3_instruction
*, indirects
);
442 /* and same for instructions that consume predicate register: */
443 DECLARE_ARRAY(struct ir3_instruction
*, predicates
);
445 /* Track texture sample instructions which need texture state
446 * patched in (for astc-srgb workaround):
448 DECLARE_ARRAY(struct ir3_instruction
*, astc_srgb
);
450 /* List of blocks: */
451 struct list_head block_list
;
453 /* List of ir3_array's: */
454 struct list_head array_list
;
456 unsigned max_sun
; /* max Sethi–Ullman number */
459 unsigned block_count
, instr_count
;
464 struct list_head node
;
468 struct nir_register
*r
;
470 /* To avoid array write's from getting DCE'd, keep track of the
471 * most recent write. Any array access depends on the most
472 * recent write. This way, nothing depends on writes after the
473 * last read. But all the writes that happen before that have
474 * something depending on them
476 struct ir3_instruction
*last_write
;
478 /* extra stuff used in RA pass: */
479 unsigned base
; /* base vreg name */
480 unsigned reg
; /* base physical reg */
481 uint16_t start_ip
, end_ip
;
484 struct ir3_array
* ir3_lookup_array(struct ir3
*ir
, unsigned id
);
487 struct list_head node
;
490 const struct nir_block
*nblock
;
492 struct list_head instr_list
; /* list of ir3_instruction */
494 /* each block has either one or two successors.. in case of
495 * two successors, 'condition' decides which one to follow.
496 * A block preceding an if/else has two successors.
498 struct ir3_instruction
*condition
;
499 struct ir3_block
*successors
[2];
501 unsigned predecessors_count
;
502 struct ir3_block
**predecessors
;
504 uint16_t start_ip
, end_ip
;
506 /* Track instructions which do not write a register but other-
507 * wise must not be discarded (such as kill, stg, etc)
509 DECLARE_ARRAY(struct ir3_instruction
*, keeps
);
511 /* used for per-pass extra block data. Mainly used right
512 * now in RA step to track livein/liveout.
521 static inline uint32_t
522 block_id(struct ir3_block
*block
)
525 return block
->serialno
;
527 return (uint32_t)(unsigned long)block
;
531 struct ir3
* ir3_create(struct ir3_compiler
*compiler
,
532 gl_shader_stage type
, unsigned nin
, unsigned nout
);
533 void ir3_destroy(struct ir3
*shader
);
534 void * ir3_assemble(struct ir3
*shader
,
535 struct ir3_info
*info
, uint32_t gpu_id
);
536 void * ir3_alloc(struct ir3
*shader
, int sz
);
538 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
540 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
);
541 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
542 opc_t opc
, int nreg
);
543 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
544 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
);
545 const char *ir3_instr_name(struct ir3_instruction
*instr
);
547 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
549 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
550 struct ir3_register
*reg
);
552 void ir3_instr_set_address(struct ir3_instruction
*instr
,
553 struct ir3_instruction
*addr
);
555 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
557 if (instr
->flags
& IR3_INSTR_MARK
)
558 return true; /* already visited */
559 instr
->flags
|= IR3_INSTR_MARK
;
563 void ir3_block_clear_mark(struct ir3_block
*block
);
564 void ir3_clear_mark(struct ir3
*shader
);
566 unsigned ir3_count_instructions(struct ir3
*ir
);
568 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
569 struct ir3_register
*reg
)
572 for (i
= 0; i
< instr
->regs_count
; i
++)
573 if (reg
== instr
->regs
[i
])
579 #define MAX_ARRAYS 16
587 static inline uint32_t regid(int num
, int comp
)
589 return (num
<< 2) | (comp
& 0x3);
592 static inline uint32_t reg_num(struct ir3_register
*reg
)
594 return reg
->num
>> 2;
597 static inline uint32_t reg_comp(struct ir3_register
*reg
)
599 return reg
->num
& 0x3;
602 static inline bool is_flow(struct ir3_instruction
*instr
)
604 return (opc_cat(instr
->opc
) == 0);
607 static inline bool is_kill(struct ir3_instruction
*instr
)
609 return instr
->opc
== OPC_KILL
;
612 static inline bool is_nop(struct ir3_instruction
*instr
)
614 return instr
->opc
== OPC_NOP
;
617 static inline bool is_same_type_reg(struct ir3_register
*reg1
,
618 struct ir3_register
*reg2
)
620 unsigned type_reg1
= (reg1
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
621 unsigned type_reg2
= (reg2
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
623 if (type_reg1
^ type_reg2
)
629 /* Is it a non-transformative (ie. not type changing) mov? This can
630 * also include absneg.s/absneg.f, which for the most part can be
631 * treated as a mov (single src argument).
633 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
635 struct ir3_register
*dst
;
637 switch (instr
->opc
) {
639 if (instr
->cat1
.src_type
!= instr
->cat1
.dst_type
)
644 if (instr
->flags
& IR3_INSTR_SAT
)
646 /* If the type of dest reg and src reg are different,
647 * it shouldn't be considered as same type mov */
648 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
655 dst
= instr
->regs
[0];
657 /* mov's that write to a0.x or p0.x are special: */
658 if (dst
->num
== regid(REG_P0
, 0))
660 if (dst
->num
== regid(REG_A0
, 0))
663 if (dst
->flags
& (IR3_REG_RELATIV
| IR3_REG_ARRAY
))
669 static inline bool is_alu(struct ir3_instruction
*instr
)
671 return (1 <= opc_cat(instr
->opc
)) && (opc_cat(instr
->opc
) <= 3);
674 static inline bool is_sfu(struct ir3_instruction
*instr
)
676 return (opc_cat(instr
->opc
) == 4);
679 static inline bool is_tex(struct ir3_instruction
*instr
)
681 return (opc_cat(instr
->opc
) == 5);
684 static inline bool is_mem(struct ir3_instruction
*instr
)
686 return (opc_cat(instr
->opc
) == 6);
689 static inline bool is_barrier(struct ir3_instruction
*instr
)
691 return (opc_cat(instr
->opc
) == 7);
695 is_store(struct ir3_instruction
*instr
)
697 /* these instructions, the "destination" register is
698 * actually a source, the address to store to.
700 switch (instr
->opc
) {
715 static inline bool is_load(struct ir3_instruction
*instr
)
717 switch (instr
->opc
) {
727 /* probably some others too.. */
734 static inline bool is_input(struct ir3_instruction
*instr
)
736 /* in some cases, ldlv is used to fetch varying without
737 * interpolation.. fortunately inloc is the first src
738 * register in either case
740 switch (instr
->opc
) {
749 static inline bool is_bool(struct ir3_instruction
*instr
)
751 switch (instr
->opc
) {
761 static inline bool is_meta(struct ir3_instruction
*instr
)
763 /* TODO how should we count PHI (and maybe fan-in/out) which
764 * might actually contribute some instructions to the final
767 return (opc_cat(instr
->opc
) == -1);
770 static inline unsigned dest_regs(struct ir3_instruction
*instr
)
772 if ((instr
->regs_count
== 0) || is_store(instr
))
775 return util_last_bit(instr
->regs
[0]->wrmask
);
778 static inline bool writes_addr(struct ir3_instruction
*instr
)
780 if (instr
->regs_count
> 0) {
781 struct ir3_register
*dst
= instr
->regs
[0];
782 return reg_num(dst
) == REG_A0
;
787 static inline bool writes_pred(struct ir3_instruction
*instr
)
789 if (instr
->regs_count
> 0) {
790 struct ir3_register
*dst
= instr
->regs
[0];
791 return reg_num(dst
) == REG_P0
;
796 /* returns defining instruction for reg */
797 /* TODO better name */
798 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
800 if (reg
->flags
& (IR3_REG_SSA
| IR3_REG_ARRAY
)) {
806 static inline bool conflicts(struct ir3_instruction
*a
,
807 struct ir3_instruction
*b
)
809 return (a
&& b
) && (a
!= b
);
812 static inline bool reg_gpr(struct ir3_register
*r
)
814 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
816 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
821 static inline type_t
half_type(type_t type
)
824 case TYPE_F32
: return TYPE_F16
;
825 case TYPE_U32
: return TYPE_U16
;
826 case TYPE_S32
: return TYPE_S16
;
837 /* some cat2 instructions (ie. those which are not float) can embed an
840 static inline bool ir3_cat2_int(opc_t opc
)
880 static inline bool ir3_cat2_float(opc_t opc
)
903 static inline bool ir3_cat3_float(opc_t opc
)
916 /* map cat2 instruction to valid abs/neg flags: */
917 static inline unsigned ir3_cat2_absneg(opc_t opc
)
934 return IR3_REG_FABS
| IR3_REG_FNEG
;
955 return IR3_REG_SABS
| IR3_REG_SNEG
;
976 /* map cat3 instructions to valid abs/neg flags: */
977 static inline unsigned ir3_cat3_absneg(opc_t opc
)
996 /* neg *may* work on 3rd src.. */
1006 #define MASK(n) ((1 << (n)) - 1)
1008 /* iterator for an instructions's sources (reg), also returns src #: */
1009 #define foreach_src_n(__srcreg, __n, __instr) \
1010 if ((__instr)->regs_count) \
1011 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
1012 if ((__srcreg = (__instr)->regs[__n + 1]))
1014 /* iterator for an instructions's sources (reg): */
1015 #define foreach_src(__srcreg, __instr) \
1016 foreach_src_n(__srcreg, __i, __instr)
1018 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
1020 unsigned cnt
= instr
->regs_count
+ instr
->deps_count
;
1026 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
1028 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1029 return instr
->address
;
1030 if (n
>= instr
->regs_count
)
1031 return instr
->deps
[n
- instr
->regs_count
];
1032 return ssa(instr
->regs
[n
]);
1035 static inline bool __is_false_dep(struct ir3_instruction
*instr
, unsigned n
)
1037 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1039 if (n
>= instr
->regs_count
)
1044 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
1046 /* iterator for an instruction's SSA sources (instr), also returns src #: */
1047 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
1048 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
1049 if ((__srcinst = __ssa_src_n(__instr, __n)))
1051 /* iterator for an instruction's SSA sources (instr): */
1052 #define foreach_ssa_src(__srcinst, __instr) \
1053 foreach_ssa_src_n(__srcinst, __i, __instr)
1057 void ir3_print(struct ir3
*ir
);
1058 void ir3_print_instr(struct ir3_instruction
*instr
);
1060 /* depth calculation: */
1061 int ir3_delayslots(struct ir3_instruction
*assigner
,
1062 struct ir3_instruction
*consumer
, unsigned n
);
1063 void ir3_insert_by_depth(struct ir3_instruction
*instr
, struct list_head
*list
);
1064 void ir3_depth(struct ir3
*ir
);
1066 /* copy-propagate: */
1067 struct ir3_shader_variant
;
1068 void ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1070 /* group neighbors and insert mov's to resolve conflicts: */
1071 void ir3_group(struct ir3
*ir
);
1073 /* Sethi–Ullman numbering: */
1074 void ir3_sun(struct ir3
*ir
);
1077 void ir3_sched_add_deps(struct ir3
*ir
);
1078 int ir3_sched(struct ir3
*ir
);
1080 void ir3_a6xx_fixup_atomic_dests(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1082 /* register assignment: */
1083 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(struct ir3_compiler
*compiler
);
1084 int ir3_ra(struct ir3
*ir3
);
1087 void ir3_legalize(struct ir3
*ir
, bool *has_ssbo
, bool *need_pixlod
, int *max_bary
);
1089 /* ************************************************************************* */
1090 /* instruction helpers */
1092 static inline struct ir3_instruction
*
1093 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
1095 struct ir3_instruction
*mov
;
1096 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1098 mov
= ir3_instr_create(block
, OPC_MOV
);
1099 mov
->cat1
.src_type
= type
;
1100 mov
->cat1
.dst_type
= type
;
1101 ir3_reg_create(mov
, 0, flags
);
1102 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
1107 static inline struct ir3_instruction
*
1108 create_immed(struct ir3_block
*block
, uint32_t val
)
1110 return create_immed_typed(block
, val
, TYPE_U32
);
1113 static inline struct ir3_instruction
*
1114 create_uniform_typed(struct ir3_block
*block
, unsigned n
, type_t type
)
1116 struct ir3_instruction
*mov
;
1117 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1119 mov
= ir3_instr_create(block
, OPC_MOV
);
1120 mov
->cat1
.src_type
= type
;
1121 mov
->cat1
.dst_type
= type
;
1122 ir3_reg_create(mov
, 0, flags
);
1123 ir3_reg_create(mov
, n
, IR3_REG_CONST
| flags
);
1128 static inline struct ir3_instruction
*
1129 create_uniform(struct ir3_block
*block
, unsigned n
)
1131 return create_uniform_typed(block
, n
, TYPE_F32
);
1134 static inline struct ir3_instruction
*
1135 create_uniform_indirect(struct ir3_block
*block
, int n
,
1136 struct ir3_instruction
*address
)
1138 struct ir3_instruction
*mov
;
1140 mov
= ir3_instr_create(block
, OPC_MOV
);
1141 mov
->cat1
.src_type
= TYPE_U32
;
1142 mov
->cat1
.dst_type
= TYPE_U32
;
1143 ir3_reg_create(mov
, 0, 0);
1144 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
1146 ir3_instr_set_address(mov
, address
);
1151 /* creates SSA src of correct type (ie. half vs full precision) */
1152 static inline struct ir3_register
* __ssa_src(struct ir3_instruction
*instr
,
1153 struct ir3_instruction
*src
, unsigned flags
)
1155 struct ir3_register
*reg
;
1156 if (src
->regs
[0]->flags
& IR3_REG_HALF
)
1157 flags
|= IR3_REG_HALF
;
1158 reg
= ir3_reg_create(instr
, 0, IR3_REG_SSA
| flags
);
1160 reg
->wrmask
= src
->regs
[0]->wrmask
;
1164 static inline struct ir3_instruction
*
1165 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
1167 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1168 ir3_reg_create(instr
, 0, 0); /* dst */
1169 if (src
->regs
[0]->flags
& IR3_REG_ARRAY
) {
1170 struct ir3_register
*src_reg
= __ssa_src(instr
, src
, IR3_REG_ARRAY
);
1171 src_reg
->array
= src
->regs
[0]->array
;
1173 __ssa_src(instr
, src
, src
->regs
[0]->flags
& IR3_REG_HIGH
);
1175 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_RELATIV
));
1176 instr
->cat1
.src_type
= type
;
1177 instr
->cat1
.dst_type
= type
;
1181 static inline struct ir3_instruction
*
1182 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
1183 type_t src_type
, type_t dst_type
)
1185 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1186 unsigned dst_flags
= (type_size(dst_type
) < 32) ? IR3_REG_HALF
: 0;
1187 unsigned src_flags
= (type_size(src_type
) < 32) ? IR3_REG_HALF
: 0;
1189 debug_assert((src
->regs
[0]->flags
& IR3_REG_HALF
) == src_flags
);
1191 ir3_reg_create(instr
, 0, dst_flags
); /* dst */
1192 __ssa_src(instr
, src
, 0);
1193 instr
->cat1
.src_type
= src_type
;
1194 instr
->cat1
.dst_type
= dst_type
;
1195 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_ARRAY
));
1199 static inline struct ir3_instruction
*
1200 ir3_NOP(struct ir3_block
*block
)
1202 return ir3_instr_create(block
, OPC_NOP
);
1205 #define IR3_INSTR_0 0
1207 #define __INSTR0(flag, name, opc) \
1208 static inline struct ir3_instruction * \
1209 ir3_##name(struct ir3_block *block) \
1211 struct ir3_instruction *instr = \
1212 ir3_instr_create(block, opc); \
1213 instr->flags |= flag; \
1216 #define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name)
1217 #define INSTR0(name) __INSTR0(0, name, OPC_##name)
1219 #define __INSTR1(flag, name, opc) \
1220 static inline struct ir3_instruction * \
1221 ir3_##name(struct ir3_block *block, \
1222 struct ir3_instruction *a, unsigned aflags) \
1224 struct ir3_instruction *instr = \
1225 ir3_instr_create(block, opc); \
1226 ir3_reg_create(instr, 0, 0); /* dst */ \
1227 __ssa_src(instr, a, aflags); \
1228 instr->flags |= flag; \
1231 #define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name)
1232 #define INSTR1(name) __INSTR1(0, name, OPC_##name)
1234 #define __INSTR2(flag, name, opc) \
1235 static inline struct ir3_instruction * \
1236 ir3_##name(struct ir3_block *block, \
1237 struct ir3_instruction *a, unsigned aflags, \
1238 struct ir3_instruction *b, unsigned bflags) \
1240 struct ir3_instruction *instr = \
1241 ir3_instr_create(block, opc); \
1242 ir3_reg_create(instr, 0, 0); /* dst */ \
1243 __ssa_src(instr, a, aflags); \
1244 __ssa_src(instr, b, bflags); \
1245 instr->flags |= flag; \
1248 #define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name)
1249 #define INSTR2(name) __INSTR2(0, name, OPC_##name)
1251 #define __INSTR3(flag, name, opc) \
1252 static inline struct ir3_instruction * \
1253 ir3_##name(struct ir3_block *block, \
1254 struct ir3_instruction *a, unsigned aflags, \
1255 struct ir3_instruction *b, unsigned bflags, \
1256 struct ir3_instruction *c, unsigned cflags) \
1258 struct ir3_instruction *instr = \
1259 ir3_instr_create2(block, opc, 4); \
1260 ir3_reg_create(instr, 0, 0); /* dst */ \
1261 __ssa_src(instr, a, aflags); \
1262 __ssa_src(instr, b, bflags); \
1263 __ssa_src(instr, c, cflags); \
1264 instr->flags |= flag; \
1267 #define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name)
1268 #define INSTR3(name) __INSTR3(0, name, OPC_##name)
1270 #define __INSTR4(flag, name, opc) \
1271 static inline struct ir3_instruction * \
1272 ir3_##name(struct ir3_block *block, \
1273 struct ir3_instruction *a, unsigned aflags, \
1274 struct ir3_instruction *b, unsigned bflags, \
1275 struct ir3_instruction *c, unsigned cflags, \
1276 struct ir3_instruction *d, unsigned dflags) \
1278 struct ir3_instruction *instr = \
1279 ir3_instr_create2(block, opc, 5); \
1280 ir3_reg_create(instr, 0, 0); /* dst */ \
1281 __ssa_src(instr, a, aflags); \
1282 __ssa_src(instr, b, bflags); \
1283 __ssa_src(instr, c, cflags); \
1284 __ssa_src(instr, d, dflags); \
1285 instr->flags |= flag; \
1288 #define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name)
1289 #define INSTR4(name) __INSTR4(0, name, OPC_##name)
1291 /* cat0 instructions: */
1297 /* cat2 instructions, most 2 src but some 1 src: */
1345 /* cat3 instructions: */
1363 /* cat4 instructions: */
1372 /* cat5 instructions: */
1379 static inline struct ir3_instruction
*
1380 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1381 unsigned wrmask
, unsigned flags
, struct ir3_instruction
*samp_tex
,
1382 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1384 struct ir3_instruction
*sam
;
1385 struct ir3_register
*reg
;
1387 sam
= ir3_instr_create(block
, opc
);
1388 sam
->flags
|= flags
| IR3_INSTR_S2EN
;
1389 ir3_reg_create(sam
, 0, 0)->wrmask
= wrmask
;
1390 __ssa_src(sam
, samp_tex
, IR3_REG_HALF
);
1392 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
1393 reg
->wrmask
= (1 << (src0
->regs_count
- 1)) - 1;
1397 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
1399 reg
->wrmask
= (1 << (src1
->regs_count
- 1)) - 1;
1401 sam
->cat5
.type
= type
;
1406 /* cat6 instructions: */
1419 INSTR2(ATOMIC_CMPXCHG
)
1428 INSTR3F(G
, ATOMIC_ADD
)
1429 INSTR3F(G
, ATOMIC_SUB
)
1430 INSTR3F(G
, ATOMIC_XCHG
)
1431 INSTR3F(G
, ATOMIC_INC
)
1432 INSTR3F(G
, ATOMIC_DEC
)
1433 INSTR3F(G
, ATOMIC_CMPXCHG
)
1434 INSTR3F(G
, ATOMIC_MIN
)
1435 INSTR3F(G
, ATOMIC_MAX
)
1436 INSTR3F(G
, ATOMIC_AND
)
1437 INSTR3F(G
, ATOMIC_OR
)
1438 INSTR3F(G
, ATOMIC_XOR
)
1443 INSTR4F(G
, ATOMIC_ADD
)
1444 INSTR4F(G
, ATOMIC_SUB
)
1445 INSTR4F(G
, ATOMIC_XCHG
)
1446 INSTR4F(G
, ATOMIC_INC
)
1447 INSTR4F(G
, ATOMIC_DEC
)
1448 INSTR4F(G
, ATOMIC_CMPXCHG
)
1449 INSTR4F(G
, ATOMIC_MIN
)
1450 INSTR4F(G
, ATOMIC_MAX
)
1451 INSTR4F(G
, ATOMIC_AND
)
1452 INSTR4F(G
, ATOMIC_OR
)
1453 INSTR4F(G
, ATOMIC_XOR
)
1456 /* cat7 instructions: */
1460 /* ************************************************************************* */
1461 /* split this out or find some helper to use.. like main/bitset.h.. */
1467 typedef uint8_t regmask_t
[2 * MAX_REG
/ 8];
1469 static inline unsigned regmask_idx(struct ir3_register
*reg
)
1471 unsigned num
= (reg
->flags
& IR3_REG_RELATIV
) ? reg
->array
.offset
: reg
->num
;
1472 debug_assert(num
< MAX_REG
);
1473 if (reg
->flags
& IR3_REG_HALF
) {
1483 static inline void regmask_init(regmask_t
*regmask
)
1485 memset(regmask
, 0, sizeof(*regmask
));
1488 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1490 unsigned idx
= regmask_idx(reg
);
1491 if (reg
->flags
& IR3_REG_RELATIV
) {
1493 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1494 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1497 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1499 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1503 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1506 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1507 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1510 /* set bits in a if not set in b, conceptually:
1513 static inline void regmask_set_if_not(regmask_t
*a
,
1514 struct ir3_register
*reg
, regmask_t
*b
)
1516 unsigned idx
= regmask_idx(reg
);
1517 if (reg
->flags
& IR3_REG_RELATIV
) {
1519 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1520 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1521 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1524 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1526 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1527 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1531 static inline bool regmask_get(regmask_t
*regmask
,
1532 struct ir3_register
*reg
)
1534 unsigned idx
= regmask_idx(reg
);
1535 if (reg
->flags
& IR3_REG_RELATIV
) {
1537 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1538 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1542 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1544 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1550 /* ************************************************************************* */