2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "compiler/shader_enums.h"
32 #include "util/bitscan.h"
33 #include "util/list.h"
34 #include "util/u_debug.h"
36 #include "instr-a3xx.h"
38 /* low level intermediate representation of an adreno shader program */
42 struct ir3_instruction
;
48 uint16_t instrs_count
; /* expanded to account for rpt's */
49 /* NOTE: max_reg, etc, does not include registers not touched
50 * by the shader (ie. vertex fetched via VFD_DECODE but not
53 int8_t max_reg
; /* highest GPR # used by shader */
57 /* number of sync bits: */
63 IR3_REG_CONST
= 0x001,
64 IR3_REG_IMMED
= 0x002,
66 /* high registers are used for some things in compute shaders,
67 * for example. Seems to be for things that are global to all
68 * threads in a wave, so possibly these are global/shared by
69 * all the threads in the wave?
72 IR3_REG_RELATIV
= 0x010,
74 /* Most instructions, it seems, can do float abs/neg but not
75 * integer. The CP pass needs to know what is intended (int or
76 * float) in order to do the right thing. For this reason the
77 * abs/neg flags are split out into float and int variants. In
78 * addition, .b (bitwise) operations, the negate is actually a
79 * bitwise not, so split that out into a new flag to make it
88 IR3_REG_POS_INF
= 0x1000,
89 /* (ei) flag, end-input? Set on last bary, presumably to signal
90 * that the shader needs no more input:
93 /* meta-flags, for intermediate stages of IR, ie.
94 * before register assignment is done:
96 IR3_REG_SSA
= 0x4000, /* 'instr' is ptr to assigning instr */
97 IR3_REG_ARRAY
= 0x8000,
101 bool merged
: 1; /* half-regs conflict with full regs (ie >= a6xx) */
104 * the component is in the low two bits of the reg #, so
105 * rN.x becomes: (N << 2) | x
120 /* For IR3_REG_SSA, src registers contain ptr back to assigning
123 * For IR3_REG_ARRAY, the pointer is back to the last dependent
124 * array access (although the net effect is the same, it points
125 * back to a previous instruction that we depend on).
127 struct ir3_instruction
*instr
;
130 /* used for cat5 instructions, but also for internal/IR level
131 * tracking of what registers are read/written by an instruction.
132 * wrmask may be a bad name since it is used to represent both
133 * src and dst that touch multiple adjacent registers.
136 /* for relative addressing, 32bits for array size is too small,
137 * but otoh we don't need to deal with disjoint sets, so instead
138 * use a simple size field (number of scalar components).
145 * Stupid/simple growable array implementation:
147 #define DECLARE_ARRAY(type, name) \
148 unsigned name ## _count, name ## _sz; \
151 #define array_insert(ctx, arr, val) do { \
152 if (arr ## _count == arr ## _sz) { \
153 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
154 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
156 arr[arr ##_count++] = val; \
159 struct ir3_instruction
{
160 struct ir3_block
*block
;
163 /* (sy) flag is set on first instruction, and after sample
164 * instructions (probably just on RAW hazard).
166 IR3_INSTR_SY
= 0x001,
167 /* (ss) flag is set on first instruction, and first instruction
168 * to depend on the result of "long" instructions (RAW hazard):
170 * rcp, rsq, log2, exp2, sin, cos, sqrt
172 * It seems to synchronize until all in-flight instructions are
173 * completed, for example:
176 * add.f hr2.z, (neg)hr2.z, hc0.y
177 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
180 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
182 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
183 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
184 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
186 * The last mul.f does not have (ss) set, presumably because the
187 * (ss) on the previous instruction does the job.
189 * The blob driver also seems to set it on WAR hazards, although
190 * not really clear if this is needed or just blob compiler being
191 * sloppy. So far I haven't found a case where removing the (ss)
192 * causes problems for WAR hazard, but I could just be getting
196 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
199 IR3_INSTR_SS
= 0x002,
200 /* (jp) flag is set on jump targets:
202 IR3_INSTR_JP
= 0x004,
203 IR3_INSTR_UL
= 0x008,
204 IR3_INSTR_3D
= 0x010,
209 IR3_INSTR_S2EN
= 0x200,
211 IR3_INSTR_SAT
= 0x800,
212 /* meta-flags, for intermediate stages of IR, ie.
213 * before register assignment is done:
215 IR3_INSTR_MARK
= 0x1000,
216 IR3_INSTR_UNUSED
= 0x2000,
224 struct ir3_register
**regs
;
230 struct ir3_block
*target
;
233 type_t src_type
, dst_type
;
253 int iim_val
: 3; /* for ldgb/stgb, # of components */
258 unsigned w
: 1; /* write */
259 unsigned r
: 1; /* read */
260 unsigned l
: 1; /* local */
261 unsigned g
: 1; /* global */
263 /* for meta-instructions, just used to hold extra data
264 * before instruction scheduling, etc
267 int off
; /* component/offset */
270 struct ir3_block
*block
;
274 /* transient values used during various algorithms: */
276 /* The instruction depth is the max dependency distance to output.
278 * You can also think of it as the "cost", if we did any sort of
279 * optimization for register footprint. Ie. a value that is just
280 * result of moving a const to a reg would have a low cost, so to
281 * it could make sense to duplicate the instruction at various
282 * points where the result is needed to reduce register footprint.
285 /* When we get to the RA stage, we no longer need depth, but
286 * we do need instruction's position/name:
294 /* used for per-pass extra instruction data.
298 int sun
; /* Sethi–Ullman number, used by sched */
299 int use_count
; /* currently just updated/used by cp */
301 /* Used during CP and RA stages. For fanin and shader inputs/
302 * outputs where we need a sequence of consecutive registers,
303 * keep track of each src instructions left (ie 'n-1') and right
304 * (ie 'n+1') neighbor. The front-end must insert enough mov's
305 * to ensure that each instruction has at most one left and at
306 * most one right neighbor. During the copy-propagation pass,
307 * we only remove mov's when we can preserve this constraint.
308 * And during the RA stage, we use the neighbor information to
309 * allocate a block of registers in one shot.
311 * TODO: maybe just add something like:
312 * struct ir3_instruction_ref {
313 * struct ir3_instruction *instr;
317 * Or can we get away without the refcnt stuff? It seems like
318 * it should be overkill.. the problem is if, potentially after
319 * already eliminating some mov's, if you have a single mov that
320 * needs to be grouped with it's neighbors in two different
321 * places (ex. shader output and a fanin).
324 struct ir3_instruction
*left
, *right
;
325 uint16_t left_cnt
, right_cnt
;
328 /* an instruction can reference at most one address register amongst
329 * it's src/dst registers. Beyond that, you need to insert mov's.
331 * NOTE: do not write this directly, use ir3_instr_set_address()
333 struct ir3_instruction
*address
;
335 /* Tracking for additional dependent instructions. Used to handle
336 * barriers, WAR hazards for arrays/SSBOs/etc.
338 DECLARE_ARRAY(struct ir3_instruction
*, deps
);
341 * From PoV of instruction scheduling, not execution (ie. ignores global/
342 * local distinction):
343 * shared image atomic SSBO everything
344 * barrier()/ - R/W R/W R/W R/W X
345 * groupMemoryBarrier()
346 * memoryBarrier() - R/W R/W
347 * (but only images declared coherent?)
348 * memoryBarrierAtomic() - R/W
349 * memoryBarrierBuffer() - R/W
350 * memoryBarrierImage() - R/W
351 * memoryBarrierShared() - R/W
353 * TODO I think for SSBO/image/shared, in cases where we can determine
354 * which variable is accessed, we don't need to care about accesses to
355 * different variables (unless declared coherent??)
358 IR3_BARRIER_EVERYTHING
= 1 << 0,
359 IR3_BARRIER_SHARED_R
= 1 << 1,
360 IR3_BARRIER_SHARED_W
= 1 << 2,
361 IR3_BARRIER_IMAGE_R
= 1 << 3,
362 IR3_BARRIER_IMAGE_W
= 1 << 4,
363 IR3_BARRIER_BUFFER_R
= 1 << 5,
364 IR3_BARRIER_BUFFER_W
= 1 << 6,
365 IR3_BARRIER_ARRAY_R
= 1 << 7,
366 IR3_BARRIER_ARRAY_W
= 1 << 8,
367 } barrier_class
, barrier_conflict
;
369 /* Entry in ir3_block's instruction list: */
370 struct list_head node
;
377 static inline struct ir3_instruction
*
378 ir3_neighbor_first(struct ir3_instruction
*instr
)
381 while (instr
->cp
.left
) {
382 instr
= instr
->cp
.left
;
383 if (++cnt
> 0xffff) {
391 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
395 debug_assert(!instr
->cp
.left
);
397 while (instr
->cp
.right
) {
399 instr
= instr
->cp
.right
;
410 struct ir3_compiler
*compiler
;
411 gl_shader_stage type
;
413 unsigned ninputs
, noutputs
;
414 struct ir3_instruction
**inputs
;
415 struct ir3_instruction
**outputs
;
417 /* Track bary.f (and ldlv) instructions.. this is needed in
418 * scheduling to ensure that all varying fetches happen before
419 * any potential kill instructions. The hw gets grumpy if all
420 * threads in a group are killed before the last bary.f gets
421 * a chance to signal end of input (ei).
423 DECLARE_ARRAY(struct ir3_instruction
*, baryfs
);
425 /* Track all indirect instructions (read and write). To avoid
426 * deadlock scenario where an address register gets scheduled,
427 * but other dependent src instructions cannot be scheduled due
428 * to dependency on a *different* address register value, the
429 * scheduler needs to ensure that all dependencies other than
430 * the instruction other than the address register are scheduled
431 * before the one that writes the address register. Having a
432 * convenient list of instructions that reference some address
433 * register simplifies this.
435 DECLARE_ARRAY(struct ir3_instruction
*, indirects
);
437 /* and same for instructions that consume predicate register: */
438 DECLARE_ARRAY(struct ir3_instruction
*, predicates
);
440 /* Track texture sample instructions which need texture state
441 * patched in (for astc-srgb workaround):
443 DECLARE_ARRAY(struct ir3_instruction
*, astc_srgb
);
445 /* List of blocks: */
446 struct list_head block_list
;
448 /* List of ir3_array's: */
449 struct list_head array_list
;
451 unsigned max_sun
; /* max Sethi–Ullman number */
454 unsigned block_count
, instr_count
;
459 struct list_head node
;
463 struct nir_register
*r
;
465 /* To avoid array write's from getting DCE'd, keep track of the
466 * most recent write. Any array access depends on the most
467 * recent write. This way, nothing depends on writes after the
468 * last read. But all the writes that happen before that have
469 * something depending on them
471 struct ir3_instruction
*last_write
;
473 /* extra stuff used in RA pass: */
474 unsigned base
; /* base vreg name */
475 unsigned reg
; /* base physical reg */
476 uint16_t start_ip
, end_ip
;
479 struct ir3_array
* ir3_lookup_array(struct ir3
*ir
, unsigned id
);
482 struct list_head node
;
485 const struct nir_block
*nblock
;
487 struct list_head instr_list
; /* list of ir3_instruction */
489 /* each block has either one or two successors.. in case of
490 * two successors, 'condition' decides which one to follow.
491 * A block preceding an if/else has two successors.
493 struct ir3_instruction
*condition
;
494 struct ir3_block
*successors
[2];
496 unsigned predecessors_count
;
497 struct ir3_block
**predecessors
;
499 uint16_t start_ip
, end_ip
;
501 /* Track instructions which do not write a register but other-
502 * wise must not be discarded (such as kill, stg, etc)
504 DECLARE_ARRAY(struct ir3_instruction
*, keeps
);
506 /* used for per-pass extra block data. Mainly used right
507 * now in RA step to track livein/liveout.
516 static inline uint32_t
517 block_id(struct ir3_block
*block
)
520 return block
->serialno
;
522 return (uint32_t)(unsigned long)block
;
526 struct ir3
* ir3_create(struct ir3_compiler
*compiler
,
527 gl_shader_stage type
, unsigned nin
, unsigned nout
);
528 void ir3_destroy(struct ir3
*shader
);
529 void * ir3_assemble(struct ir3
*shader
,
530 struct ir3_info
*info
, uint32_t gpu_id
);
531 void * ir3_alloc(struct ir3
*shader
, int sz
);
533 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
535 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
);
536 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
537 opc_t opc
, int nreg
);
538 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
539 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
);
540 const char *ir3_instr_name(struct ir3_instruction
*instr
);
542 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
544 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
545 struct ir3_register
*reg
);
547 void ir3_instr_set_address(struct ir3_instruction
*instr
,
548 struct ir3_instruction
*addr
);
550 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
552 if (instr
->flags
& IR3_INSTR_MARK
)
553 return true; /* already visited */
554 instr
->flags
|= IR3_INSTR_MARK
;
558 void ir3_block_clear_mark(struct ir3_block
*block
);
559 void ir3_clear_mark(struct ir3
*shader
);
561 unsigned ir3_count_instructions(struct ir3
*ir
);
563 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
564 struct ir3_register
*reg
)
567 for (i
= 0; i
< instr
->regs_count
; i
++)
568 if (reg
== instr
->regs
[i
])
574 #define MAX_ARRAYS 16
582 static inline uint32_t regid(int num
, int comp
)
584 return (num
<< 2) | (comp
& 0x3);
587 static inline uint32_t reg_num(struct ir3_register
*reg
)
589 return reg
->num
>> 2;
592 static inline uint32_t reg_comp(struct ir3_register
*reg
)
594 return reg
->num
& 0x3;
597 static inline bool is_flow(struct ir3_instruction
*instr
)
599 return (opc_cat(instr
->opc
) == 0);
602 static inline bool is_kill(struct ir3_instruction
*instr
)
604 return instr
->opc
== OPC_KILL
;
607 static inline bool is_nop(struct ir3_instruction
*instr
)
609 return instr
->opc
== OPC_NOP
;
612 /* Is it a non-transformative (ie. not type changing) mov? This can
613 * also include absneg.s/absneg.f, which for the most part can be
614 * treated as a mov (single src argument).
616 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
618 struct ir3_register
*dst
;
620 switch (instr
->opc
) {
622 if (instr
->cat1
.src_type
!= instr
->cat1
.dst_type
)
627 if (instr
->flags
& IR3_INSTR_SAT
)
634 dst
= instr
->regs
[0];
636 /* mov's that write to a0.x or p0.x are special: */
637 if (dst
->num
== regid(REG_P0
, 0))
639 if (dst
->num
== regid(REG_A0
, 0))
642 if (dst
->flags
& (IR3_REG_RELATIV
| IR3_REG_ARRAY
))
648 static inline bool is_alu(struct ir3_instruction
*instr
)
650 return (1 <= opc_cat(instr
->opc
)) && (opc_cat(instr
->opc
) <= 3);
653 static inline bool is_sfu(struct ir3_instruction
*instr
)
655 return (opc_cat(instr
->opc
) == 4);
658 static inline bool is_tex(struct ir3_instruction
*instr
)
660 return (opc_cat(instr
->opc
) == 5);
663 static inline bool is_mem(struct ir3_instruction
*instr
)
665 return (opc_cat(instr
->opc
) == 6);
668 static inline bool is_barrier(struct ir3_instruction
*instr
)
670 return (opc_cat(instr
->opc
) == 7);
674 is_store(struct ir3_instruction
*instr
)
676 /* these instructions, the "destination" register is
677 * actually a source, the address to store to.
679 switch (instr
->opc
) {
694 static inline bool is_load(struct ir3_instruction
*instr
)
696 switch (instr
->opc
) {
706 /* probably some others too.. */
713 static inline bool is_input(struct ir3_instruction
*instr
)
715 /* in some cases, ldlv is used to fetch varying without
716 * interpolation.. fortunately inloc is the first src
717 * register in either case
719 switch (instr
->opc
) {
728 static inline bool is_bool(struct ir3_instruction
*instr
)
730 switch (instr
->opc
) {
740 static inline bool is_meta(struct ir3_instruction
*instr
)
742 /* TODO how should we count PHI (and maybe fan-in/out) which
743 * might actually contribute some instructions to the final
746 return (opc_cat(instr
->opc
) == -1);
749 static inline unsigned dest_regs(struct ir3_instruction
*instr
)
751 if ((instr
->regs_count
== 0) || is_store(instr
))
754 return util_last_bit(instr
->regs
[0]->wrmask
);
757 static inline bool writes_addr(struct ir3_instruction
*instr
)
759 if (instr
->regs_count
> 0) {
760 struct ir3_register
*dst
= instr
->regs
[0];
761 return reg_num(dst
) == REG_A0
;
766 static inline bool writes_pred(struct ir3_instruction
*instr
)
768 if (instr
->regs_count
> 0) {
769 struct ir3_register
*dst
= instr
->regs
[0];
770 return reg_num(dst
) == REG_P0
;
775 /* returns defining instruction for reg */
776 /* TODO better name */
777 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
779 if (reg
->flags
& (IR3_REG_SSA
| IR3_REG_ARRAY
)) {
785 static inline bool conflicts(struct ir3_instruction
*a
,
786 struct ir3_instruction
*b
)
788 return (a
&& b
) && (a
!= b
);
791 static inline bool reg_gpr(struct ir3_register
*r
)
793 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
795 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
800 static inline type_t
half_type(type_t type
)
803 case TYPE_F32
: return TYPE_F16
;
804 case TYPE_U32
: return TYPE_U16
;
805 case TYPE_S32
: return TYPE_S16
;
816 /* some cat2 instructions (ie. those which are not float) can embed an
819 static inline bool ir3_cat2_int(opc_t opc
)
860 /* map cat2 instruction to valid abs/neg flags: */
861 static inline unsigned ir3_cat2_absneg(opc_t opc
)
878 return IR3_REG_FABS
| IR3_REG_FNEG
;
899 return IR3_REG_SABS
| IR3_REG_SNEG
;
920 /* map cat3 instructions to valid abs/neg flags: */
921 static inline unsigned ir3_cat3_absneg(opc_t opc
)
940 /* neg *may* work on 3rd src.. */
950 #define MASK(n) ((1 << (n)) - 1)
952 /* iterator for an instructions's sources (reg), also returns src #: */
953 #define foreach_src_n(__srcreg, __n, __instr) \
954 if ((__instr)->regs_count) \
955 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
956 if ((__srcreg = (__instr)->regs[__n + 1]))
958 /* iterator for an instructions's sources (reg): */
959 #define foreach_src(__srcreg, __instr) \
960 foreach_src_n(__srcreg, __i, __instr)
962 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
964 unsigned cnt
= instr
->regs_count
+ instr
->deps_count
;
970 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
972 if (n
== (instr
->regs_count
+ instr
->deps_count
))
973 return instr
->address
;
974 if (n
>= instr
->regs_count
)
975 return instr
->deps
[n
- instr
->regs_count
];
976 return ssa(instr
->regs
[n
]);
979 static inline bool __is_false_dep(struct ir3_instruction
*instr
, unsigned n
)
981 if (n
== (instr
->regs_count
+ instr
->deps_count
))
983 if (n
>= instr
->regs_count
)
988 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
990 /* iterator for an instruction's SSA sources (instr), also returns src #: */
991 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
992 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
993 if ((__srcinst = __ssa_src_n(__instr, __n)))
995 /* iterator for an instruction's SSA sources (instr): */
996 #define foreach_ssa_src(__srcinst, __instr) \
997 foreach_ssa_src_n(__srcinst, __i, __instr)
1001 void ir3_print(struct ir3
*ir
);
1002 void ir3_print_instr(struct ir3_instruction
*instr
);
1004 /* depth calculation: */
1005 int ir3_delayslots(struct ir3_instruction
*assigner
,
1006 struct ir3_instruction
*consumer
, unsigned n
);
1007 void ir3_insert_by_depth(struct ir3_instruction
*instr
, struct list_head
*list
);
1008 void ir3_depth(struct ir3
*ir
);
1010 /* copy-propagate: */
1011 struct ir3_shader_variant
;
1012 void ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1014 /* group neighbors and insert mov's to resolve conflicts: */
1015 void ir3_group(struct ir3
*ir
);
1017 /* Sethi–Ullman numbering: */
1018 void ir3_sun(struct ir3
*ir
);
1021 void ir3_sched_add_deps(struct ir3
*ir
);
1022 int ir3_sched(struct ir3
*ir
);
1024 void ir3_a6xx_fixup_atomic_dests(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1026 /* register assignment: */
1027 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(struct ir3_compiler
*compiler
);
1028 int ir3_ra(struct ir3
*ir3
, gl_shader_stage type
,
1029 bool frag_coord
, bool frag_face
);
1032 void ir3_legalize(struct ir3
*ir
, bool *has_ssbo
, bool *need_pixlod
, int *max_bary
);
1034 /* ************************************************************************* */
1035 /* instruction helpers */
1037 static inline struct ir3_instruction
*
1038 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
1040 struct ir3_instruction
*mov
;
1041 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1043 mov
= ir3_instr_create(block
, OPC_MOV
);
1044 mov
->cat1
.src_type
= type
;
1045 mov
->cat1
.dst_type
= type
;
1046 ir3_reg_create(mov
, 0, flags
);
1047 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
1052 static inline struct ir3_instruction
*
1053 create_immed(struct ir3_block
*block
, uint32_t val
)
1055 return create_immed_typed(block
, val
, TYPE_U32
);
1058 static inline struct ir3_instruction
*
1059 create_uniform(struct ir3_block
*block
, unsigned n
)
1061 struct ir3_instruction
*mov
;
1063 mov
= ir3_instr_create(block
, OPC_MOV
);
1064 /* TODO get types right? */
1065 mov
->cat1
.src_type
= TYPE_F32
;
1066 mov
->cat1
.dst_type
= TYPE_F32
;
1067 ir3_reg_create(mov
, 0, 0);
1068 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
1073 static inline struct ir3_instruction
*
1074 create_uniform_indirect(struct ir3_block
*block
, int n
,
1075 struct ir3_instruction
*address
)
1077 struct ir3_instruction
*mov
;
1079 mov
= ir3_instr_create(block
, OPC_MOV
);
1080 mov
->cat1
.src_type
= TYPE_U32
;
1081 mov
->cat1
.dst_type
= TYPE_U32
;
1082 ir3_reg_create(mov
, 0, 0);
1083 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
1085 ir3_instr_set_address(mov
, address
);
1090 /* creates SSA src of correct type (ie. half vs full precision) */
1091 static inline struct ir3_register
* __ssa_src(struct ir3_instruction
*instr
,
1092 struct ir3_instruction
*src
, unsigned flags
)
1094 struct ir3_register
*reg
;
1095 if (src
->regs
[0]->flags
& IR3_REG_HALF
)
1096 flags
|= IR3_REG_HALF
;
1097 reg
= ir3_reg_create(instr
, 0, IR3_REG_SSA
| flags
);
1099 reg
->wrmask
= src
->regs
[0]->wrmask
;
1103 static inline struct ir3_instruction
*
1104 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
1106 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1107 ir3_reg_create(instr
, 0, 0); /* dst */
1108 if (src
->regs
[0]->flags
& IR3_REG_ARRAY
) {
1109 struct ir3_register
*src_reg
= __ssa_src(instr
, src
, IR3_REG_ARRAY
);
1110 src_reg
->array
= src
->regs
[0]->array
;
1112 __ssa_src(instr
, src
, src
->regs
[0]->flags
& IR3_REG_HIGH
);
1114 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_RELATIV
));
1115 instr
->cat1
.src_type
= type
;
1116 instr
->cat1
.dst_type
= type
;
1120 static inline struct ir3_instruction
*
1121 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
1122 type_t src_type
, type_t dst_type
)
1124 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1125 unsigned dst_flags
= (type_size(dst_type
) < 32) ? IR3_REG_HALF
: 0;
1126 unsigned src_flags
= (type_size(src_type
) < 32) ? IR3_REG_HALF
: 0;
1128 debug_assert((src
->regs
[0]->flags
& IR3_REG_HALF
) == src_flags
);
1130 ir3_reg_create(instr
, 0, dst_flags
); /* dst */
1131 __ssa_src(instr
, src
, 0);
1132 instr
->cat1
.src_type
= src_type
;
1133 instr
->cat1
.dst_type
= dst_type
;
1134 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_ARRAY
));
1138 static inline struct ir3_instruction
*
1139 ir3_NOP(struct ir3_block
*block
)
1141 return ir3_instr_create(block
, OPC_NOP
);
1144 #define IR3_INSTR_0 0
1146 #define __INSTR0(flag, name, opc) \
1147 static inline struct ir3_instruction * \
1148 ir3_##name(struct ir3_block *block) \
1150 struct ir3_instruction *instr = \
1151 ir3_instr_create(block, opc); \
1152 instr->flags |= flag; \
1155 #define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name)
1156 #define INSTR0(name) __INSTR0(0, name, OPC_##name)
1158 #define __INSTR1(flag, name, opc) \
1159 static inline struct ir3_instruction * \
1160 ir3_##name(struct ir3_block *block, \
1161 struct ir3_instruction *a, unsigned aflags) \
1163 struct ir3_instruction *instr = \
1164 ir3_instr_create(block, opc); \
1165 ir3_reg_create(instr, 0, 0); /* dst */ \
1166 __ssa_src(instr, a, aflags); \
1167 instr->flags |= flag; \
1170 #define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name)
1171 #define INSTR1(name) __INSTR1(0, name, OPC_##name)
1173 #define __INSTR2(flag, name, opc) \
1174 static inline struct ir3_instruction * \
1175 ir3_##name(struct ir3_block *block, \
1176 struct ir3_instruction *a, unsigned aflags, \
1177 struct ir3_instruction *b, unsigned bflags) \
1179 struct ir3_instruction *instr = \
1180 ir3_instr_create(block, opc); \
1181 ir3_reg_create(instr, 0, 0); /* dst */ \
1182 __ssa_src(instr, a, aflags); \
1183 __ssa_src(instr, b, bflags); \
1184 instr->flags |= flag; \
1187 #define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name)
1188 #define INSTR2(name) __INSTR2(0, name, OPC_##name)
1190 #define __INSTR3(flag, name, opc) \
1191 static inline struct ir3_instruction * \
1192 ir3_##name(struct ir3_block *block, \
1193 struct ir3_instruction *a, unsigned aflags, \
1194 struct ir3_instruction *b, unsigned bflags, \
1195 struct ir3_instruction *c, unsigned cflags) \
1197 struct ir3_instruction *instr = \
1198 ir3_instr_create2(block, opc, 4); \
1199 ir3_reg_create(instr, 0, 0); /* dst */ \
1200 __ssa_src(instr, a, aflags); \
1201 __ssa_src(instr, b, bflags); \
1202 __ssa_src(instr, c, cflags); \
1203 instr->flags |= flag; \
1206 #define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name)
1207 #define INSTR3(name) __INSTR3(0, name, OPC_##name)
1209 #define __INSTR4(flag, name, opc) \
1210 static inline struct ir3_instruction * \
1211 ir3_##name(struct ir3_block *block, \
1212 struct ir3_instruction *a, unsigned aflags, \
1213 struct ir3_instruction *b, unsigned bflags, \
1214 struct ir3_instruction *c, unsigned cflags, \
1215 struct ir3_instruction *d, unsigned dflags) \
1217 struct ir3_instruction *instr = \
1218 ir3_instr_create2(block, opc, 5); \
1219 ir3_reg_create(instr, 0, 0); /* dst */ \
1220 __ssa_src(instr, a, aflags); \
1221 __ssa_src(instr, b, bflags); \
1222 __ssa_src(instr, c, cflags); \
1223 __ssa_src(instr, d, dflags); \
1224 instr->flags |= flag; \
1227 #define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name)
1228 #define INSTR4(name) __INSTR4(0, name, OPC_##name)
1230 /* cat0 instructions: */
1236 /* cat2 instructions, most 2 src but some 1 src: */
1284 /* cat3 instructions: */
1302 /* cat4 instructions: */
1311 /* cat5 instructions: */
1318 static inline struct ir3_instruction
*
1319 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1320 unsigned wrmask
, unsigned flags
, struct ir3_instruction
*samp_tex
,
1321 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1323 struct ir3_instruction
*sam
;
1324 struct ir3_register
*reg
;
1326 sam
= ir3_instr_create(block
, opc
);
1327 sam
->flags
|= flags
| IR3_INSTR_S2EN
;
1328 ir3_reg_create(sam
, 0, 0)->wrmask
= wrmask
;
1329 __ssa_src(sam
, samp_tex
, IR3_REG_HALF
);
1331 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
1332 reg
->wrmask
= (1 << (src0
->regs_count
- 1)) - 1;
1336 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
1338 reg
->wrmask
= (1 << (src1
->regs_count
- 1)) - 1;
1340 sam
->cat5
.type
= type
;
1345 /* cat6 instructions: */
1358 INSTR2(ATOMIC_CMPXCHG
)
1367 INSTR3F(G
, ATOMIC_ADD
)
1368 INSTR3F(G
, ATOMIC_SUB
)
1369 INSTR3F(G
, ATOMIC_XCHG
)
1370 INSTR3F(G
, ATOMIC_INC
)
1371 INSTR3F(G
, ATOMIC_DEC
)
1372 INSTR3F(G
, ATOMIC_CMPXCHG
)
1373 INSTR3F(G
, ATOMIC_MIN
)
1374 INSTR3F(G
, ATOMIC_MAX
)
1375 INSTR3F(G
, ATOMIC_AND
)
1376 INSTR3F(G
, ATOMIC_OR
)
1377 INSTR3F(G
, ATOMIC_XOR
)
1382 INSTR4F(G
, ATOMIC_ADD
)
1383 INSTR4F(G
, ATOMIC_SUB
)
1384 INSTR4F(G
, ATOMIC_XCHG
)
1385 INSTR4F(G
, ATOMIC_INC
)
1386 INSTR4F(G
, ATOMIC_DEC
)
1387 INSTR4F(G
, ATOMIC_CMPXCHG
)
1388 INSTR4F(G
, ATOMIC_MIN
)
1389 INSTR4F(G
, ATOMIC_MAX
)
1390 INSTR4F(G
, ATOMIC_AND
)
1391 INSTR4F(G
, ATOMIC_OR
)
1392 INSTR4F(G
, ATOMIC_XOR
)
1395 /* cat7 instructions: */
1399 /* ************************************************************************* */
1400 /* split this out or find some helper to use.. like main/bitset.h.. */
1406 typedef uint8_t regmask_t
[2 * MAX_REG
/ 8];
1408 static inline unsigned regmask_idx(struct ir3_register
*reg
)
1410 unsigned num
= (reg
->flags
& IR3_REG_RELATIV
) ? reg
->array
.offset
: reg
->num
;
1411 debug_assert(num
< MAX_REG
);
1412 if (reg
->flags
& IR3_REG_HALF
) {
1422 static inline void regmask_init(regmask_t
*regmask
)
1424 memset(regmask
, 0, sizeof(*regmask
));
1427 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1429 unsigned idx
= regmask_idx(reg
);
1430 if (reg
->flags
& IR3_REG_RELATIV
) {
1432 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1433 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1436 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1438 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1442 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1445 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1446 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1449 /* set bits in a if not set in b, conceptually:
1452 static inline void regmask_set_if_not(regmask_t
*a
,
1453 struct ir3_register
*reg
, regmask_t
*b
)
1455 unsigned idx
= regmask_idx(reg
);
1456 if (reg
->flags
& IR3_REG_RELATIV
) {
1458 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1459 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1460 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1463 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1465 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1466 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1470 static inline bool regmask_get(regmask_t
*regmask
,
1471 struct ir3_register
*reg
)
1473 unsigned idx
= regmask_idx(reg
);
1474 if (reg
->flags
& IR3_REG_RELATIV
) {
1476 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1477 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1481 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1483 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1489 /* ************************************************************************* */