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freedreno/ir3: enable indirect tex/samp (sam.s2en)
[mesa.git] / src / freedreno / ir3 / ir3.h
1 /*
2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #ifndef IR3_H_
25 #define IR3_H_
26
27 #include <stdint.h>
28 #include <stdbool.h>
29
30 #include "compiler/shader_enums.h"
31
32 #include "util/bitscan.h"
33 #include "util/list.h"
34 #include "util/u_debug.h"
35
36 #include "instr-a3xx.h"
37
38 /* low level intermediate representation of an adreno shader program */
39
40 struct ir3_compiler;
41 struct ir3;
42 struct ir3_instruction;
43 struct ir3_block;
44
45 struct ir3_info {
46 uint32_t gpu_id;
47 uint16_t sizedwords;
48 uint16_t instrs_count; /* expanded to account for rpt's */
49 /* NOTE: max_reg, etc, does not include registers not touched
50 * by the shader (ie. vertex fetched via VFD_DECODE but not
51 * touched by shader)
52 */
53 int8_t max_reg; /* highest GPR # used by shader */
54 int8_t max_half_reg;
55 int16_t max_const;
56
57 /* number of sync bits: */
58 uint16_t ss, sy;
59 };
60
61 struct ir3_register {
62 enum {
63 IR3_REG_CONST = 0x001,
64 IR3_REG_IMMED = 0x002,
65 IR3_REG_HALF = 0x004,
66 /* high registers are used for some things in compute shaders,
67 * for example. Seems to be for things that are global to all
68 * threads in a wave, so possibly these are global/shared by
69 * all the threads in the wave?
70 */
71 IR3_REG_HIGH = 0x008,
72 IR3_REG_RELATIV= 0x010,
73 IR3_REG_R = 0x020,
74 /* Most instructions, it seems, can do float abs/neg but not
75 * integer. The CP pass needs to know what is intended (int or
76 * float) in order to do the right thing. For this reason the
77 * abs/neg flags are split out into float and int variants. In
78 * addition, .b (bitwise) operations, the negate is actually a
79 * bitwise not, so split that out into a new flag to make it
80 * more clear.
81 */
82 IR3_REG_FNEG = 0x040,
83 IR3_REG_FABS = 0x080,
84 IR3_REG_SNEG = 0x100,
85 IR3_REG_SABS = 0x200,
86 IR3_REG_BNOT = 0x400,
87 IR3_REG_EVEN = 0x800,
88 IR3_REG_POS_INF= 0x1000,
89 /* (ei) flag, end-input? Set on last bary, presumably to signal
90 * that the shader needs no more input:
91 */
92 IR3_REG_EI = 0x2000,
93 /* meta-flags, for intermediate stages of IR, ie.
94 * before register assignment is done:
95 */
96 IR3_REG_SSA = 0x4000, /* 'instr' is ptr to assigning instr */
97 IR3_REG_ARRAY = 0x8000,
98
99 } flags;
100
101 bool merged : 1; /* half-regs conflict with full regs (ie >= a6xx) */
102
103 /* normal registers:
104 * the component is in the low two bits of the reg #, so
105 * rN.x becomes: (N << 2) | x
106 */
107 uint16_t num;
108 union {
109 /* immediate: */
110 int32_t iim_val;
111 uint32_t uim_val;
112 float fim_val;
113 /* relative: */
114 struct {
115 uint16_t id;
116 int16_t offset;
117 } array;
118 };
119
120 /* For IR3_REG_SSA, src registers contain ptr back to assigning
121 * instruction.
122 *
123 * For IR3_REG_ARRAY, the pointer is back to the last dependent
124 * array access (although the net effect is the same, it points
125 * back to a previous instruction that we depend on).
126 */
127 struct ir3_instruction *instr;
128
129 union {
130 /* used for cat5 instructions, but also for internal/IR level
131 * tracking of what registers are read/written by an instruction.
132 * wrmask may be a bad name since it is used to represent both
133 * src and dst that touch multiple adjacent registers.
134 */
135 unsigned wrmask;
136 /* for relative addressing, 32bits for array size is too small,
137 * but otoh we don't need to deal with disjoint sets, so instead
138 * use a simple size field (number of scalar components).
139 */
140 unsigned size;
141 };
142 };
143
144 /*
145 * Stupid/simple growable array implementation:
146 */
147 #define DECLARE_ARRAY(type, name) \
148 unsigned name ## _count, name ## _sz; \
149 type * name;
150
151 #define array_insert(ctx, arr, val) do { \
152 if (arr ## _count == arr ## _sz) { \
153 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
154 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
155 } \
156 arr[arr ##_count++] = val; \
157 } while (0)
158
159 struct ir3_instruction {
160 struct ir3_block *block;
161 opc_t opc;
162 enum {
163 /* (sy) flag is set on first instruction, and after sample
164 * instructions (probably just on RAW hazard).
165 */
166 IR3_INSTR_SY = 0x001,
167 /* (ss) flag is set on first instruction, and first instruction
168 * to depend on the result of "long" instructions (RAW hazard):
169 *
170 * rcp, rsq, log2, exp2, sin, cos, sqrt
171 *
172 * It seems to synchronize until all in-flight instructions are
173 * completed, for example:
174 *
175 * rsq hr1.w, hr1.w
176 * add.f hr2.z, (neg)hr2.z, hc0.y
177 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
178 * rsq hr2.x, hr2.x
179 * (rpt1)nop
180 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
181 * nop
182 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
183 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
184 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
185 *
186 * The last mul.f does not have (ss) set, presumably because the
187 * (ss) on the previous instruction does the job.
188 *
189 * The blob driver also seems to set it on WAR hazards, although
190 * not really clear if this is needed or just blob compiler being
191 * sloppy. So far I haven't found a case where removing the (ss)
192 * causes problems for WAR hazard, but I could just be getting
193 * lucky:
194 *
195 * rcp r1.y, r3.y
196 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
197 *
198 */
199 IR3_INSTR_SS = 0x002,
200 /* (jp) flag is set on jump targets:
201 */
202 IR3_INSTR_JP = 0x004,
203 IR3_INSTR_UL = 0x008,
204 IR3_INSTR_3D = 0x010,
205 IR3_INSTR_A = 0x020,
206 IR3_INSTR_O = 0x040,
207 IR3_INSTR_P = 0x080,
208 IR3_INSTR_S = 0x100,
209 IR3_INSTR_S2EN = 0x200,
210 IR3_INSTR_G = 0x400,
211 IR3_INSTR_SAT = 0x800,
212 /* meta-flags, for intermediate stages of IR, ie.
213 * before register assignment is done:
214 */
215 IR3_INSTR_MARK = 0x1000,
216 IR3_INSTR_UNUSED= 0x2000,
217 } flags;
218 uint8_t repeat;
219 uint8_t nop;
220 #ifdef DEBUG
221 unsigned regs_max;
222 #endif
223 unsigned regs_count;
224 struct ir3_register **regs;
225 union {
226 struct {
227 char inv;
228 char comp;
229 int immed;
230 struct ir3_block *target;
231 } cat0;
232 struct {
233 type_t src_type, dst_type;
234 } cat1;
235 struct {
236 enum {
237 IR3_COND_LT = 0,
238 IR3_COND_LE = 1,
239 IR3_COND_GT = 2,
240 IR3_COND_GE = 3,
241 IR3_COND_EQ = 4,
242 IR3_COND_NE = 5,
243 } condition;
244 } cat2;
245 struct {
246 unsigned samp, tex;
247 type_t type;
248 } cat5;
249 struct {
250 type_t type;
251 int src_offset;
252 int dst_offset;
253 int iim_val : 3; /* for ldgb/stgb, # of components */
254 unsigned d : 3;
255 bool typed : 1;
256 } cat6;
257 struct {
258 unsigned w : 1; /* write */
259 unsigned r : 1; /* read */
260 unsigned l : 1; /* local */
261 unsigned g : 1; /* global */
262 } cat7;
263 /* for meta-instructions, just used to hold extra data
264 * before instruction scheduling, etc
265 */
266 struct {
267 int off; /* component/offset */
268 } fo;
269 struct {
270 struct ir3_block *block;
271 } inout;
272 };
273
274 /* transient values used during various algorithms: */
275 union {
276 /* The instruction depth is the max dependency distance to output.
277 *
278 * You can also think of it as the "cost", if we did any sort of
279 * optimization for register footprint. Ie. a value that is just
280 * result of moving a const to a reg would have a low cost, so to
281 * it could make sense to duplicate the instruction at various
282 * points where the result is needed to reduce register footprint.
283 */
284 unsigned depth;
285 /* When we get to the RA stage, we no longer need depth, but
286 * we do need instruction's position/name:
287 */
288 struct {
289 uint16_t ip;
290 uint16_t name;
291 };
292 };
293
294 /* used for per-pass extra instruction data.
295 */
296 void *data;
297
298 int sun; /* Sethi–Ullman number, used by sched */
299 int use_count; /* currently just updated/used by cp */
300
301 /* Used during CP and RA stages. For fanin and shader inputs/
302 * outputs where we need a sequence of consecutive registers,
303 * keep track of each src instructions left (ie 'n-1') and right
304 * (ie 'n+1') neighbor. The front-end must insert enough mov's
305 * to ensure that each instruction has at most one left and at
306 * most one right neighbor. During the copy-propagation pass,
307 * we only remove mov's when we can preserve this constraint.
308 * And during the RA stage, we use the neighbor information to
309 * allocate a block of registers in one shot.
310 *
311 * TODO: maybe just add something like:
312 * struct ir3_instruction_ref {
313 * struct ir3_instruction *instr;
314 * unsigned cnt;
315 * }
316 *
317 * Or can we get away without the refcnt stuff? It seems like
318 * it should be overkill.. the problem is if, potentially after
319 * already eliminating some mov's, if you have a single mov that
320 * needs to be grouped with it's neighbors in two different
321 * places (ex. shader output and a fanin).
322 */
323 struct {
324 struct ir3_instruction *left, *right;
325 uint16_t left_cnt, right_cnt;
326 } cp;
327
328 /* an instruction can reference at most one address register amongst
329 * it's src/dst registers. Beyond that, you need to insert mov's.
330 *
331 * NOTE: do not write this directly, use ir3_instr_set_address()
332 */
333 struct ir3_instruction *address;
334
335 /* Tracking for additional dependent instructions. Used to handle
336 * barriers, WAR hazards for arrays/SSBOs/etc.
337 */
338 DECLARE_ARRAY(struct ir3_instruction *, deps);
339
340 /*
341 * From PoV of instruction scheduling, not execution (ie. ignores global/
342 * local distinction):
343 * shared image atomic SSBO everything
344 * barrier()/ - R/W R/W R/W R/W X
345 * groupMemoryBarrier()
346 * memoryBarrier() - R/W R/W
347 * (but only images declared coherent?)
348 * memoryBarrierAtomic() - R/W
349 * memoryBarrierBuffer() - R/W
350 * memoryBarrierImage() - R/W
351 * memoryBarrierShared() - R/W
352 *
353 * TODO I think for SSBO/image/shared, in cases where we can determine
354 * which variable is accessed, we don't need to care about accesses to
355 * different variables (unless declared coherent??)
356 */
357 enum {
358 IR3_BARRIER_EVERYTHING = 1 << 0,
359 IR3_BARRIER_SHARED_R = 1 << 1,
360 IR3_BARRIER_SHARED_W = 1 << 2,
361 IR3_BARRIER_IMAGE_R = 1 << 3,
362 IR3_BARRIER_IMAGE_W = 1 << 4,
363 IR3_BARRIER_BUFFER_R = 1 << 5,
364 IR3_BARRIER_BUFFER_W = 1 << 6,
365 IR3_BARRIER_ARRAY_R = 1 << 7,
366 IR3_BARRIER_ARRAY_W = 1 << 8,
367 } barrier_class, barrier_conflict;
368
369 /* Entry in ir3_block's instruction list: */
370 struct list_head node;
371
372 #ifdef DEBUG
373 uint32_t serialno;
374 #endif
375 };
376
377 static inline struct ir3_instruction *
378 ir3_neighbor_first(struct ir3_instruction *instr)
379 {
380 int cnt = 0;
381 while (instr->cp.left) {
382 instr = instr->cp.left;
383 if (++cnt > 0xffff) {
384 debug_assert(0);
385 break;
386 }
387 }
388 return instr;
389 }
390
391 static inline int ir3_neighbor_count(struct ir3_instruction *instr)
392 {
393 int num = 1;
394
395 debug_assert(!instr->cp.left);
396
397 while (instr->cp.right) {
398 num++;
399 instr = instr->cp.right;
400 if (num > 0xffff) {
401 debug_assert(0);
402 break;
403 }
404 }
405
406 return num;
407 }
408
409 struct ir3 {
410 struct ir3_compiler *compiler;
411
412 unsigned ninputs, noutputs;
413 struct ir3_instruction **inputs;
414 struct ir3_instruction **outputs;
415
416 /* Track bary.f (and ldlv) instructions.. this is needed in
417 * scheduling to ensure that all varying fetches happen before
418 * any potential kill instructions. The hw gets grumpy if all
419 * threads in a group are killed before the last bary.f gets
420 * a chance to signal end of input (ei).
421 */
422 DECLARE_ARRAY(struct ir3_instruction *, baryfs);
423
424 /* Track all indirect instructions (read and write). To avoid
425 * deadlock scenario where an address register gets scheduled,
426 * but other dependent src instructions cannot be scheduled due
427 * to dependency on a *different* address register value, the
428 * scheduler needs to ensure that all dependencies other than
429 * the instruction other than the address register are scheduled
430 * before the one that writes the address register. Having a
431 * convenient list of instructions that reference some address
432 * register simplifies this.
433 */
434 DECLARE_ARRAY(struct ir3_instruction *, indirects);
435
436 /* and same for instructions that consume predicate register: */
437 DECLARE_ARRAY(struct ir3_instruction *, predicates);
438
439 /* Track texture sample instructions which need texture state
440 * patched in (for astc-srgb workaround):
441 */
442 DECLARE_ARRAY(struct ir3_instruction *, astc_srgb);
443
444 /* List of blocks: */
445 struct list_head block_list;
446
447 /* List of ir3_array's: */
448 struct list_head array_list;
449
450 unsigned max_sun; /* max Sethi–Ullman number */
451
452 #ifdef DEBUG
453 unsigned block_count, instr_count;
454 #endif
455 };
456
457 struct ir3_array {
458 struct list_head node;
459 unsigned length;
460 unsigned id;
461
462 struct nir_register *r;
463
464 /* To avoid array write's from getting DCE'd, keep track of the
465 * most recent write. Any array access depends on the most
466 * recent write. This way, nothing depends on writes after the
467 * last read. But all the writes that happen before that have
468 * something depending on them
469 */
470 struct ir3_instruction *last_write;
471
472 /* extra stuff used in RA pass: */
473 unsigned base; /* base vreg name */
474 unsigned reg; /* base physical reg */
475 uint16_t start_ip, end_ip;
476 };
477
478 struct ir3_array * ir3_lookup_array(struct ir3 *ir, unsigned id);
479
480 struct ir3_block {
481 struct list_head node;
482 struct ir3 *shader;
483
484 const struct nir_block *nblock;
485
486 struct list_head instr_list; /* list of ir3_instruction */
487
488 /* each block has either one or two successors.. in case of
489 * two successors, 'condition' decides which one to follow.
490 * A block preceding an if/else has two successors.
491 */
492 struct ir3_instruction *condition;
493 struct ir3_block *successors[2];
494
495 unsigned predecessors_count;
496 struct ir3_block **predecessors;
497
498 uint16_t start_ip, end_ip;
499
500 /* Track instructions which do not write a register but other-
501 * wise must not be discarded (such as kill, stg, etc)
502 */
503 DECLARE_ARRAY(struct ir3_instruction *, keeps);
504
505 /* used for per-pass extra block data. Mainly used right
506 * now in RA step to track livein/liveout.
507 */
508 void *data;
509
510 #ifdef DEBUG
511 uint32_t serialno;
512 #endif
513 };
514
515 static inline uint32_t
516 block_id(struct ir3_block *block)
517 {
518 #ifdef DEBUG
519 return block->serialno;
520 #else
521 return (uint32_t)(unsigned long)block;
522 #endif
523 }
524
525 struct ir3 * ir3_create(struct ir3_compiler *compiler,
526 unsigned nin, unsigned nout);
527 void ir3_destroy(struct ir3 *shader);
528 void * ir3_assemble(struct ir3 *shader,
529 struct ir3_info *info, uint32_t gpu_id);
530 void * ir3_alloc(struct ir3 *shader, int sz);
531
532 struct ir3_block * ir3_block_create(struct ir3 *shader);
533
534 struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc);
535 struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
536 opc_t opc, int nreg);
537 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
538 void ir3_instr_add_dep(struct ir3_instruction *instr, struct ir3_instruction *dep);
539 const char *ir3_instr_name(struct ir3_instruction *instr);
540
541 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
542 int num, int flags);
543 struct ir3_register * ir3_reg_clone(struct ir3 *shader,
544 struct ir3_register *reg);
545
546 void ir3_instr_set_address(struct ir3_instruction *instr,
547 struct ir3_instruction *addr);
548
549 static inline bool ir3_instr_check_mark(struct ir3_instruction *instr)
550 {
551 if (instr->flags & IR3_INSTR_MARK)
552 return true; /* already visited */
553 instr->flags |= IR3_INSTR_MARK;
554 return false;
555 }
556
557 void ir3_block_clear_mark(struct ir3_block *block);
558 void ir3_clear_mark(struct ir3 *shader);
559
560 unsigned ir3_count_instructions(struct ir3 *ir);
561
562 static inline int ir3_instr_regno(struct ir3_instruction *instr,
563 struct ir3_register *reg)
564 {
565 unsigned i;
566 for (i = 0; i < instr->regs_count; i++)
567 if (reg == instr->regs[i])
568 return i;
569 return -1;
570 }
571
572
573 #define MAX_ARRAYS 16
574
575 /* comp:
576 * 0 - x
577 * 1 - y
578 * 2 - z
579 * 3 - w
580 */
581 static inline uint32_t regid(int num, int comp)
582 {
583 return (num << 2) | (comp & 0x3);
584 }
585
586 static inline uint32_t reg_num(struct ir3_register *reg)
587 {
588 return reg->num >> 2;
589 }
590
591 static inline uint32_t reg_comp(struct ir3_register *reg)
592 {
593 return reg->num & 0x3;
594 }
595
596 static inline bool is_flow(struct ir3_instruction *instr)
597 {
598 return (opc_cat(instr->opc) == 0);
599 }
600
601 static inline bool is_kill(struct ir3_instruction *instr)
602 {
603 return instr->opc == OPC_KILL;
604 }
605
606 static inline bool is_nop(struct ir3_instruction *instr)
607 {
608 return instr->opc == OPC_NOP;
609 }
610
611 /* Is it a non-transformative (ie. not type changing) mov? This can
612 * also include absneg.s/absneg.f, which for the most part can be
613 * treated as a mov (single src argument).
614 */
615 static inline bool is_same_type_mov(struct ir3_instruction *instr)
616 {
617 struct ir3_register *dst;
618
619 switch (instr->opc) {
620 case OPC_MOV:
621 if (instr->cat1.src_type != instr->cat1.dst_type)
622 return false;
623 break;
624 case OPC_ABSNEG_F:
625 case OPC_ABSNEG_S:
626 if (instr->flags & IR3_INSTR_SAT)
627 return false;
628 break;
629 default:
630 return false;
631 }
632
633 dst = instr->regs[0];
634
635 /* mov's that write to a0.x or p0.x are special: */
636 if (dst->num == regid(REG_P0, 0))
637 return false;
638 if (dst->num == regid(REG_A0, 0))
639 return false;
640
641 if (dst->flags & (IR3_REG_RELATIV | IR3_REG_ARRAY))
642 return false;
643
644 return true;
645 }
646
647 static inline bool is_alu(struct ir3_instruction *instr)
648 {
649 return (1 <= opc_cat(instr->opc)) && (opc_cat(instr->opc) <= 3);
650 }
651
652 static inline bool is_sfu(struct ir3_instruction *instr)
653 {
654 return (opc_cat(instr->opc) == 4);
655 }
656
657 static inline bool is_tex(struct ir3_instruction *instr)
658 {
659 return (opc_cat(instr->opc) == 5);
660 }
661
662 static inline bool is_mem(struct ir3_instruction *instr)
663 {
664 return (opc_cat(instr->opc) == 6);
665 }
666
667 static inline bool is_barrier(struct ir3_instruction *instr)
668 {
669 return (opc_cat(instr->opc) == 7);
670 }
671
672 static inline bool
673 is_store(struct ir3_instruction *instr)
674 {
675 /* these instructions, the "destination" register is
676 * actually a source, the address to store to.
677 */
678 switch (instr->opc) {
679 case OPC_STG:
680 case OPC_STGB:
681 case OPC_STIB:
682 case OPC_STP:
683 case OPC_STL:
684 case OPC_STLW:
685 case OPC_L2G:
686 case OPC_G2L:
687 return true;
688 default:
689 return false;
690 }
691 }
692
693 static inline bool is_load(struct ir3_instruction *instr)
694 {
695 switch (instr->opc) {
696 case OPC_LDG:
697 case OPC_LDGB:
698 case OPC_LDIB:
699 case OPC_LDL:
700 case OPC_LDP:
701 case OPC_L2G:
702 case OPC_LDLW:
703 case OPC_LDC:
704 case OPC_LDLV:
705 /* probably some others too.. */
706 return true;
707 default:
708 return false;
709 }
710 }
711
712 static inline bool is_input(struct ir3_instruction *instr)
713 {
714 /* in some cases, ldlv is used to fetch varying without
715 * interpolation.. fortunately inloc is the first src
716 * register in either case
717 */
718 switch (instr->opc) {
719 case OPC_LDLV:
720 case OPC_BARY_F:
721 return true;
722 default:
723 return false;
724 }
725 }
726
727 static inline bool is_bool(struct ir3_instruction *instr)
728 {
729 switch (instr->opc) {
730 case OPC_CMPS_F:
731 case OPC_CMPS_S:
732 case OPC_CMPS_U:
733 return true;
734 default:
735 return false;
736 }
737 }
738
739 static inline bool is_meta(struct ir3_instruction *instr)
740 {
741 /* TODO how should we count PHI (and maybe fan-in/out) which
742 * might actually contribute some instructions to the final
743 * result?
744 */
745 return (opc_cat(instr->opc) == -1);
746 }
747
748 static inline unsigned dest_regs(struct ir3_instruction *instr)
749 {
750 if ((instr->regs_count == 0) || is_store(instr))
751 return 0;
752
753 return util_last_bit(instr->regs[0]->wrmask);
754 }
755
756 static inline bool writes_addr(struct ir3_instruction *instr)
757 {
758 if (instr->regs_count > 0) {
759 struct ir3_register *dst = instr->regs[0];
760 return reg_num(dst) == REG_A0;
761 }
762 return false;
763 }
764
765 static inline bool writes_pred(struct ir3_instruction *instr)
766 {
767 if (instr->regs_count > 0) {
768 struct ir3_register *dst = instr->regs[0];
769 return reg_num(dst) == REG_P0;
770 }
771 return false;
772 }
773
774 /* returns defining instruction for reg */
775 /* TODO better name */
776 static inline struct ir3_instruction *ssa(struct ir3_register *reg)
777 {
778 if (reg->flags & (IR3_REG_SSA | IR3_REG_ARRAY)) {
779 return reg->instr;
780 }
781 return NULL;
782 }
783
784 static inline bool conflicts(struct ir3_instruction *a,
785 struct ir3_instruction *b)
786 {
787 return (a && b) && (a != b);
788 }
789
790 static inline bool reg_gpr(struct ir3_register *r)
791 {
792 if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED))
793 return false;
794 if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0))
795 return false;
796 return true;
797 }
798
799 static inline type_t half_type(type_t type)
800 {
801 switch (type) {
802 case TYPE_F32: return TYPE_F16;
803 case TYPE_U32: return TYPE_U16;
804 case TYPE_S32: return TYPE_S16;
805 case TYPE_F16:
806 case TYPE_U16:
807 case TYPE_S16:
808 return type;
809 default:
810 assert(0);
811 return ~0;
812 }
813 }
814
815 /* some cat2 instructions (ie. those which are not float) can embed an
816 * immediate:
817 */
818 static inline bool ir3_cat2_int(opc_t opc)
819 {
820 switch (opc) {
821 case OPC_ADD_U:
822 case OPC_ADD_S:
823 case OPC_SUB_U:
824 case OPC_SUB_S:
825 case OPC_CMPS_U:
826 case OPC_CMPS_S:
827 case OPC_MIN_U:
828 case OPC_MIN_S:
829 case OPC_MAX_U:
830 case OPC_MAX_S:
831 case OPC_CMPV_U:
832 case OPC_CMPV_S:
833 case OPC_MUL_U:
834 case OPC_MUL_S:
835 case OPC_MULL_U:
836 case OPC_CLZ_S:
837 case OPC_ABSNEG_S:
838 case OPC_AND_B:
839 case OPC_OR_B:
840 case OPC_NOT_B:
841 case OPC_XOR_B:
842 case OPC_BFREV_B:
843 case OPC_CLZ_B:
844 case OPC_SHL_B:
845 case OPC_SHR_B:
846 case OPC_ASHR_B:
847 case OPC_MGEN_B:
848 case OPC_GETBIT_B:
849 case OPC_CBITS_B:
850 case OPC_BARY_F:
851 return true;
852
853 default:
854 return false;
855 }
856 }
857
858
859 /* map cat2 instruction to valid abs/neg flags: */
860 static inline unsigned ir3_cat2_absneg(opc_t opc)
861 {
862 switch (opc) {
863 case OPC_ADD_F:
864 case OPC_MIN_F:
865 case OPC_MAX_F:
866 case OPC_MUL_F:
867 case OPC_SIGN_F:
868 case OPC_CMPS_F:
869 case OPC_ABSNEG_F:
870 case OPC_CMPV_F:
871 case OPC_FLOOR_F:
872 case OPC_CEIL_F:
873 case OPC_RNDNE_F:
874 case OPC_RNDAZ_F:
875 case OPC_TRUNC_F:
876 case OPC_BARY_F:
877 return IR3_REG_FABS | IR3_REG_FNEG;
878
879 case OPC_ADD_U:
880 case OPC_ADD_S:
881 case OPC_SUB_U:
882 case OPC_SUB_S:
883 case OPC_CMPS_U:
884 case OPC_CMPS_S:
885 case OPC_MIN_U:
886 case OPC_MIN_S:
887 case OPC_MAX_U:
888 case OPC_MAX_S:
889 case OPC_CMPV_U:
890 case OPC_CMPV_S:
891 case OPC_MUL_U:
892 case OPC_MUL_S:
893 case OPC_MULL_U:
894 case OPC_CLZ_S:
895 return 0;
896
897 case OPC_ABSNEG_S:
898 return IR3_REG_SABS | IR3_REG_SNEG;
899
900 case OPC_AND_B:
901 case OPC_OR_B:
902 case OPC_NOT_B:
903 case OPC_XOR_B:
904 case OPC_BFREV_B:
905 case OPC_CLZ_B:
906 case OPC_SHL_B:
907 case OPC_SHR_B:
908 case OPC_ASHR_B:
909 case OPC_MGEN_B:
910 case OPC_GETBIT_B:
911 case OPC_CBITS_B:
912 return IR3_REG_BNOT;
913
914 default:
915 return 0;
916 }
917 }
918
919 /* map cat3 instructions to valid abs/neg flags: */
920 static inline unsigned ir3_cat3_absneg(opc_t opc)
921 {
922 switch (opc) {
923 case OPC_MAD_F16:
924 case OPC_MAD_F32:
925 case OPC_SEL_F16:
926 case OPC_SEL_F32:
927 return IR3_REG_FNEG;
928
929 case OPC_MAD_U16:
930 case OPC_MADSH_U16:
931 case OPC_MAD_S16:
932 case OPC_MADSH_M16:
933 case OPC_MAD_U24:
934 case OPC_MAD_S24:
935 case OPC_SEL_S16:
936 case OPC_SEL_S32:
937 case OPC_SAD_S16:
938 case OPC_SAD_S32:
939 /* neg *may* work on 3rd src.. */
940
941 case OPC_SEL_B16:
942 case OPC_SEL_B32:
943
944 default:
945 return 0;
946 }
947 }
948
949 #define MASK(n) ((1 << (n)) - 1)
950
951 /* iterator for an instructions's sources (reg), also returns src #: */
952 #define foreach_src_n(__srcreg, __n, __instr) \
953 if ((__instr)->regs_count) \
954 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
955 if ((__srcreg = (__instr)->regs[__n + 1]))
956
957 /* iterator for an instructions's sources (reg): */
958 #define foreach_src(__srcreg, __instr) \
959 foreach_src_n(__srcreg, __i, __instr)
960
961 static inline unsigned __ssa_src_cnt(struct ir3_instruction *instr)
962 {
963 unsigned cnt = instr->regs_count + instr->deps_count;
964 if (instr->address)
965 cnt++;
966 return cnt;
967 }
968
969 static inline struct ir3_instruction * __ssa_src_n(struct ir3_instruction *instr, unsigned n)
970 {
971 if (n == (instr->regs_count + instr->deps_count))
972 return instr->address;
973 if (n >= instr->regs_count)
974 return instr->deps[n - instr->regs_count];
975 return ssa(instr->regs[n]);
976 }
977
978 static inline bool __is_false_dep(struct ir3_instruction *instr, unsigned n)
979 {
980 if (n == (instr->regs_count + instr->deps_count))
981 return false;
982 if (n >= instr->regs_count)
983 return true;
984 return false;
985 }
986
987 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
988
989 /* iterator for an instruction's SSA sources (instr), also returns src #: */
990 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
991 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
992 if ((__srcinst = __ssa_src_n(__instr, __n)))
993
994 /* iterator for an instruction's SSA sources (instr): */
995 #define foreach_ssa_src(__srcinst, __instr) \
996 foreach_ssa_src_n(__srcinst, __i, __instr)
997
998
999 /* dump: */
1000 void ir3_print(struct ir3 *ir);
1001 void ir3_print_instr(struct ir3_instruction *instr);
1002
1003 /* depth calculation: */
1004 int ir3_delayslots(struct ir3_instruction *assigner,
1005 struct ir3_instruction *consumer, unsigned n);
1006 void ir3_insert_by_depth(struct ir3_instruction *instr, struct list_head *list);
1007 void ir3_depth(struct ir3 *ir);
1008
1009 /* copy-propagate: */
1010 struct ir3_shader_variant;
1011 void ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so);
1012
1013 /* group neighbors and insert mov's to resolve conflicts: */
1014 void ir3_group(struct ir3 *ir);
1015
1016 /* Sethi–Ullman numbering: */
1017 void ir3_sun(struct ir3 *ir);
1018
1019 /* scheduling: */
1020 void ir3_sched_add_deps(struct ir3 *ir);
1021 int ir3_sched(struct ir3 *ir);
1022
1023 void ir3_a6xx_fixup_atomic_dests(struct ir3 *ir, struct ir3_shader_variant *so);
1024
1025 /* register assignment: */
1026 struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler);
1027 int ir3_ra(struct ir3 *ir3, gl_shader_stage type,
1028 bool frag_coord, bool frag_face);
1029
1030 /* legalize: */
1031 void ir3_legalize(struct ir3 *ir, bool *has_ssbo, int *max_bary);
1032
1033 /* ************************************************************************* */
1034 /* instruction helpers */
1035
1036 static inline struct ir3_instruction *
1037 create_immed_typed(struct ir3_block *block, uint32_t val, type_t type)
1038 {
1039 struct ir3_instruction *mov;
1040 unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0;
1041
1042 mov = ir3_instr_create(block, OPC_MOV);
1043 mov->cat1.src_type = type;
1044 mov->cat1.dst_type = type;
1045 ir3_reg_create(mov, 0, flags);
1046 ir3_reg_create(mov, 0, IR3_REG_IMMED)->uim_val = val;
1047
1048 return mov;
1049 }
1050
1051 static inline struct ir3_instruction *
1052 create_immed(struct ir3_block *block, uint32_t val)
1053 {
1054 return create_immed_typed(block, val, TYPE_U32);
1055 }
1056
1057 static inline struct ir3_instruction *
1058 create_uniform(struct ir3_block *block, unsigned n)
1059 {
1060 struct ir3_instruction *mov;
1061
1062 mov = ir3_instr_create(block, OPC_MOV);
1063 /* TODO get types right? */
1064 mov->cat1.src_type = TYPE_F32;
1065 mov->cat1.dst_type = TYPE_F32;
1066 ir3_reg_create(mov, 0, 0);
1067 ir3_reg_create(mov, n, IR3_REG_CONST);
1068
1069 return mov;
1070 }
1071
1072 static inline struct ir3_instruction *
1073 create_uniform_indirect(struct ir3_block *block, int n,
1074 struct ir3_instruction *address)
1075 {
1076 struct ir3_instruction *mov;
1077
1078 mov = ir3_instr_create(block, OPC_MOV);
1079 mov->cat1.src_type = TYPE_U32;
1080 mov->cat1.dst_type = TYPE_U32;
1081 ir3_reg_create(mov, 0, 0);
1082 ir3_reg_create(mov, 0, IR3_REG_CONST | IR3_REG_RELATIV)->array.offset = n;
1083
1084 ir3_instr_set_address(mov, address);
1085
1086 return mov;
1087 }
1088
1089 /* creates SSA src of correct type (ie. half vs full precision) */
1090 static inline struct ir3_register * __ssa_src(struct ir3_instruction *instr,
1091 struct ir3_instruction *src, unsigned flags)
1092 {
1093 struct ir3_register *reg;
1094 if (src->regs[0]->flags & IR3_REG_HALF)
1095 flags |= IR3_REG_HALF;
1096 reg = ir3_reg_create(instr, 0, IR3_REG_SSA | flags);
1097 reg->instr = src;
1098 reg->wrmask = src->regs[0]->wrmask;
1099 return reg;
1100 }
1101
1102 static inline struct ir3_instruction *
1103 ir3_MOV(struct ir3_block *block, struct ir3_instruction *src, type_t type)
1104 {
1105 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1106 ir3_reg_create(instr, 0, 0); /* dst */
1107 if (src->regs[0]->flags & IR3_REG_ARRAY) {
1108 struct ir3_register *src_reg = __ssa_src(instr, src, IR3_REG_ARRAY);
1109 src_reg->array = src->regs[0]->array;
1110 } else {
1111 __ssa_src(instr, src, src->regs[0]->flags & IR3_REG_HIGH);
1112 }
1113 debug_assert(!(src->regs[0]->flags & IR3_REG_RELATIV));
1114 instr->cat1.src_type = type;
1115 instr->cat1.dst_type = type;
1116 return instr;
1117 }
1118
1119 static inline struct ir3_instruction *
1120 ir3_COV(struct ir3_block *block, struct ir3_instruction *src,
1121 type_t src_type, type_t dst_type)
1122 {
1123 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1124 unsigned dst_flags = (type_size(dst_type) < 32) ? IR3_REG_HALF : 0;
1125 unsigned src_flags = (type_size(src_type) < 32) ? IR3_REG_HALF : 0;
1126
1127 debug_assert((src->regs[0]->flags & IR3_REG_HALF) == src_flags);
1128
1129 ir3_reg_create(instr, 0, dst_flags); /* dst */
1130 __ssa_src(instr, src, 0);
1131 instr->cat1.src_type = src_type;
1132 instr->cat1.dst_type = dst_type;
1133 debug_assert(!(src->regs[0]->flags & IR3_REG_ARRAY));
1134 return instr;
1135 }
1136
1137 static inline struct ir3_instruction *
1138 ir3_NOP(struct ir3_block *block)
1139 {
1140 return ir3_instr_create(block, OPC_NOP);
1141 }
1142
1143 #define INSTR0(name) \
1144 static inline struct ir3_instruction * \
1145 ir3_##name(struct ir3_block *block) \
1146 { \
1147 struct ir3_instruction *instr = \
1148 ir3_instr_create(block, OPC_##name); \
1149 return instr; \
1150 }
1151
1152 #define INSTR1(name) \
1153 static inline struct ir3_instruction * \
1154 ir3_##name(struct ir3_block *block, \
1155 struct ir3_instruction *a, unsigned aflags) \
1156 { \
1157 struct ir3_instruction *instr = \
1158 ir3_instr_create(block, OPC_##name); \
1159 ir3_reg_create(instr, 0, 0); /* dst */ \
1160 __ssa_src(instr, a, aflags); \
1161 return instr; \
1162 }
1163
1164 #define INSTR2(name) \
1165 static inline struct ir3_instruction * \
1166 ir3_##name(struct ir3_block *block, \
1167 struct ir3_instruction *a, unsigned aflags, \
1168 struct ir3_instruction *b, unsigned bflags) \
1169 { \
1170 struct ir3_instruction *instr = \
1171 ir3_instr_create(block, OPC_##name); \
1172 ir3_reg_create(instr, 0, 0); /* dst */ \
1173 __ssa_src(instr, a, aflags); \
1174 __ssa_src(instr, b, bflags); \
1175 return instr; \
1176 }
1177
1178 #define INSTR3(name) \
1179 static inline struct ir3_instruction * \
1180 ir3_##name(struct ir3_block *block, \
1181 struct ir3_instruction *a, unsigned aflags, \
1182 struct ir3_instruction *b, unsigned bflags, \
1183 struct ir3_instruction *c, unsigned cflags) \
1184 { \
1185 struct ir3_instruction *instr = \
1186 ir3_instr_create(block, OPC_##name); \
1187 ir3_reg_create(instr, 0, 0); /* dst */ \
1188 __ssa_src(instr, a, aflags); \
1189 __ssa_src(instr, b, bflags); \
1190 __ssa_src(instr, c, cflags); \
1191 return instr; \
1192 }
1193
1194 #define INSTR3F(f, name) \
1195 static inline struct ir3_instruction * \
1196 ir3_##name##_##f(struct ir3_block *block, \
1197 struct ir3_instruction *a, unsigned aflags, \
1198 struct ir3_instruction *b, unsigned bflags, \
1199 struct ir3_instruction *c, unsigned cflags) \
1200 { \
1201 struct ir3_instruction *instr = \
1202 ir3_instr_create2(block, OPC_##name, 5); \
1203 ir3_reg_create(instr, 0, 0); /* dst */ \
1204 __ssa_src(instr, a, aflags); \
1205 __ssa_src(instr, b, bflags); \
1206 __ssa_src(instr, c, cflags); \
1207 instr->flags |= IR3_INSTR_##f; \
1208 return instr; \
1209 }
1210
1211 #define INSTR4(name) \
1212 static inline struct ir3_instruction * \
1213 ir3_##name(struct ir3_block *block, \
1214 struct ir3_instruction *a, unsigned aflags, \
1215 struct ir3_instruction *b, unsigned bflags, \
1216 struct ir3_instruction *c, unsigned cflags, \
1217 struct ir3_instruction *d, unsigned dflags) \
1218 { \
1219 struct ir3_instruction *instr = \
1220 ir3_instr_create2(block, OPC_##name, 5); \
1221 ir3_reg_create(instr, 0, 0); /* dst */ \
1222 __ssa_src(instr, a, aflags); \
1223 __ssa_src(instr, b, bflags); \
1224 __ssa_src(instr, c, cflags); \
1225 __ssa_src(instr, d, dflags); \
1226 return instr; \
1227 }
1228
1229 #define INSTR4F(f, name) \
1230 static inline struct ir3_instruction * \
1231 ir3_##name##_##f(struct ir3_block *block, \
1232 struct ir3_instruction *a, unsigned aflags, \
1233 struct ir3_instruction *b, unsigned bflags, \
1234 struct ir3_instruction *c, unsigned cflags, \
1235 struct ir3_instruction *d, unsigned dflags) \
1236 { \
1237 struct ir3_instruction *instr = \
1238 ir3_instr_create2(block, OPC_##name, 5); \
1239 ir3_reg_create(instr, 0, 0); /* dst */ \
1240 __ssa_src(instr, a, aflags); \
1241 __ssa_src(instr, b, bflags); \
1242 __ssa_src(instr, c, cflags); \
1243 __ssa_src(instr, d, dflags); \
1244 instr->flags |= IR3_INSTR_##f; \
1245 return instr; \
1246 }
1247
1248 /* cat0 instructions: */
1249 INSTR0(BR)
1250 INSTR0(JUMP)
1251 INSTR1(KILL)
1252 INSTR0(END)
1253
1254 /* cat2 instructions, most 2 src but some 1 src: */
1255 INSTR2(ADD_F)
1256 INSTR2(MIN_F)
1257 INSTR2(MAX_F)
1258 INSTR2(MUL_F)
1259 INSTR1(SIGN_F)
1260 INSTR2(CMPS_F)
1261 INSTR1(ABSNEG_F)
1262 INSTR2(CMPV_F)
1263 INSTR1(FLOOR_F)
1264 INSTR1(CEIL_F)
1265 INSTR1(RNDNE_F)
1266 INSTR1(RNDAZ_F)
1267 INSTR1(TRUNC_F)
1268 INSTR2(ADD_U)
1269 INSTR2(ADD_S)
1270 INSTR2(SUB_U)
1271 INSTR2(SUB_S)
1272 INSTR2(CMPS_U)
1273 INSTR2(CMPS_S)
1274 INSTR2(MIN_U)
1275 INSTR2(MIN_S)
1276 INSTR2(MAX_U)
1277 INSTR2(MAX_S)
1278 INSTR1(ABSNEG_S)
1279 INSTR2(AND_B)
1280 INSTR2(OR_B)
1281 INSTR1(NOT_B)
1282 INSTR2(XOR_B)
1283 INSTR2(CMPV_U)
1284 INSTR2(CMPV_S)
1285 INSTR2(MUL_U)
1286 INSTR2(MUL_S)
1287 INSTR2(MULL_U)
1288 INSTR1(BFREV_B)
1289 INSTR1(CLZ_S)
1290 INSTR1(CLZ_B)
1291 INSTR2(SHL_B)
1292 INSTR2(SHR_B)
1293 INSTR2(ASHR_B)
1294 INSTR2(BARY_F)
1295 INSTR2(MGEN_B)
1296 INSTR2(GETBIT_B)
1297 INSTR1(SETRM)
1298 INSTR1(CBITS_B)
1299 INSTR2(SHB)
1300 INSTR2(MSAD)
1301
1302 /* cat3 instructions: */
1303 INSTR3(MAD_U16)
1304 INSTR3(MADSH_U16)
1305 INSTR3(MAD_S16)
1306 INSTR3(MADSH_M16)
1307 INSTR3(MAD_U24)
1308 INSTR3(MAD_S24)
1309 INSTR3(MAD_F16)
1310 INSTR3(MAD_F32)
1311 INSTR3(SEL_B16)
1312 INSTR3(SEL_B32)
1313 INSTR3(SEL_S16)
1314 INSTR3(SEL_S32)
1315 INSTR3(SEL_F16)
1316 INSTR3(SEL_F32)
1317 INSTR3(SAD_S16)
1318 INSTR3(SAD_S32)
1319
1320 /* cat4 instructions: */
1321 INSTR1(RCP)
1322 INSTR1(RSQ)
1323 INSTR1(LOG2)
1324 INSTR1(EXP2)
1325 INSTR1(SIN)
1326 INSTR1(COS)
1327 INSTR1(SQRT)
1328
1329 /* cat5 instructions: */
1330 INSTR1(DSX)
1331 INSTR1(DSY)
1332
1333 static inline struct ir3_instruction *
1334 ir3_SAM(struct ir3_block *block, opc_t opc, type_t type,
1335 unsigned wrmask, unsigned flags, struct ir3_instruction *samp_tex,
1336 struct ir3_instruction *src0, struct ir3_instruction *src1)
1337 {
1338 struct ir3_instruction *sam;
1339 struct ir3_register *reg;
1340
1341 sam = ir3_instr_create(block, opc);
1342 sam->flags |= flags | IR3_INSTR_S2EN;
1343 ir3_reg_create(sam, 0, 0)->wrmask = wrmask;
1344 __ssa_src(sam, samp_tex, IR3_REG_HALF);
1345 if (src0) {
1346 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
1347 reg->wrmask = (1 << (src0->regs_count - 1)) - 1;
1348 reg->instr = src0;
1349 }
1350 if (src1) {
1351 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
1352 reg->instr = src1;
1353 reg->wrmask = (1 << (src1->regs_count - 1)) - 1;
1354 }
1355 sam->cat5.type = type;
1356
1357 return sam;
1358 }
1359
1360 /* cat6 instructions: */
1361 INSTR2(LDLV)
1362 INSTR2(LDG)
1363 INSTR2(LDL)
1364 INSTR3(STG)
1365 INSTR3(STL)
1366 INSTR1(RESINFO)
1367 INSTR1(RESFMT)
1368 INSTR2(ATOMIC_ADD)
1369 INSTR2(ATOMIC_SUB)
1370 INSTR2(ATOMIC_XCHG)
1371 INSTR2(ATOMIC_INC)
1372 INSTR2(ATOMIC_DEC)
1373 INSTR2(ATOMIC_CMPXCHG)
1374 INSTR2(ATOMIC_MIN)
1375 INSTR2(ATOMIC_MAX)
1376 INSTR2(ATOMIC_AND)
1377 INSTR2(ATOMIC_OR)
1378 INSTR2(ATOMIC_XOR)
1379 #if GPU >= 600
1380 INSTR3(STIB);
1381 INSTR2(LDIB);
1382 INSTR3F(G, ATOMIC_ADD)
1383 INSTR3F(G, ATOMIC_SUB)
1384 INSTR3F(G, ATOMIC_XCHG)
1385 INSTR3F(G, ATOMIC_INC)
1386 INSTR3F(G, ATOMIC_DEC)
1387 INSTR3F(G, ATOMIC_CMPXCHG)
1388 INSTR3F(G, ATOMIC_MIN)
1389 INSTR3F(G, ATOMIC_MAX)
1390 INSTR3F(G, ATOMIC_AND)
1391 INSTR3F(G, ATOMIC_OR)
1392 INSTR3F(G, ATOMIC_XOR)
1393 #elif GPU >= 400
1394 INSTR3(LDGB)
1395 INSTR4(STGB)
1396 INSTR4(STIB)
1397 INSTR4F(G, ATOMIC_ADD)
1398 INSTR4F(G, ATOMIC_SUB)
1399 INSTR4F(G, ATOMIC_XCHG)
1400 INSTR4F(G, ATOMIC_INC)
1401 INSTR4F(G, ATOMIC_DEC)
1402 INSTR4F(G, ATOMIC_CMPXCHG)
1403 INSTR4F(G, ATOMIC_MIN)
1404 INSTR4F(G, ATOMIC_MAX)
1405 INSTR4F(G, ATOMIC_AND)
1406 INSTR4F(G, ATOMIC_OR)
1407 INSTR4F(G, ATOMIC_XOR)
1408 #endif
1409
1410 /* cat7 instructions: */
1411 INSTR0(BAR)
1412 INSTR0(FENCE)
1413
1414 /* ************************************************************************* */
1415 /* split this out or find some helper to use.. like main/bitset.h.. */
1416
1417 #include <string.h>
1418
1419 #define MAX_REG 256
1420
1421 typedef uint8_t regmask_t[2 * MAX_REG / 8];
1422
1423 static inline unsigned regmask_idx(struct ir3_register *reg)
1424 {
1425 unsigned num = (reg->flags & IR3_REG_RELATIV) ? reg->array.offset : reg->num;
1426 debug_assert(num < MAX_REG);
1427 if (reg->flags & IR3_REG_HALF) {
1428 if (reg->merged) {
1429 num /= 2;
1430 } else {
1431 num += MAX_REG;
1432 }
1433 }
1434 return num;
1435 }
1436
1437 static inline void regmask_init(regmask_t *regmask)
1438 {
1439 memset(regmask, 0, sizeof(*regmask));
1440 }
1441
1442 static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg)
1443 {
1444 unsigned idx = regmask_idx(reg);
1445 if (reg->flags & IR3_REG_RELATIV) {
1446 unsigned i;
1447 for (i = 0; i < reg->size; i++, idx++)
1448 (*regmask)[idx / 8] |= 1 << (idx % 8);
1449 } else {
1450 unsigned mask;
1451 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1452 if (mask & 1)
1453 (*regmask)[idx / 8] |= 1 << (idx % 8);
1454 }
1455 }
1456
1457 static inline void regmask_or(regmask_t *dst, regmask_t *a, regmask_t *b)
1458 {
1459 unsigned i;
1460 for (i = 0; i < ARRAY_SIZE(*dst); i++)
1461 (*dst)[i] = (*a)[i] | (*b)[i];
1462 }
1463
1464 /* set bits in a if not set in b, conceptually:
1465 * a |= (reg & ~b)
1466 */
1467 static inline void regmask_set_if_not(regmask_t *a,
1468 struct ir3_register *reg, regmask_t *b)
1469 {
1470 unsigned idx = regmask_idx(reg);
1471 if (reg->flags & IR3_REG_RELATIV) {
1472 unsigned i;
1473 for (i = 0; i < reg->size; i++, idx++)
1474 if (!((*b)[idx / 8] & (1 << (idx % 8))))
1475 (*a)[idx / 8] |= 1 << (idx % 8);
1476 } else {
1477 unsigned mask;
1478 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1479 if (mask & 1)
1480 if (!((*b)[idx / 8] & (1 << (idx % 8))))
1481 (*a)[idx / 8] |= 1 << (idx % 8);
1482 }
1483 }
1484
1485 static inline bool regmask_get(regmask_t *regmask,
1486 struct ir3_register *reg)
1487 {
1488 unsigned idx = regmask_idx(reg);
1489 if (reg->flags & IR3_REG_RELATIV) {
1490 unsigned i;
1491 for (i = 0; i < reg->size; i++, idx++)
1492 if ((*regmask)[idx / 8] & (1 << (idx % 8)))
1493 return true;
1494 } else {
1495 unsigned mask;
1496 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1497 if (mask & 1)
1498 if ((*regmask)[idx / 8] & (1 << (idx % 8)))
1499 return true;
1500 }
1501 return false;
1502 }
1503
1504 /* ************************************************************************* */
1505
1506 #endif /* IR3_H_ */