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freedreno/ir3: remove unused ir3_instruction::inout
[mesa.git] / src / freedreno / ir3 / ir3.h
1 /*
2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #ifndef IR3_H_
25 #define IR3_H_
26
27 #include <stdint.h>
28 #include <stdbool.h>
29
30 #include "compiler/shader_enums.h"
31
32 #include "util/bitscan.h"
33 #include "util/list.h"
34 #include "util/set.h"
35 #include "util/u_debug.h"
36
37 #include "instr-a3xx.h"
38
39 /* low level intermediate representation of an adreno shader program */
40
41 struct ir3_compiler;
42 struct ir3;
43 struct ir3_instruction;
44 struct ir3_block;
45
46 struct ir3_info {
47 uint32_t gpu_id;
48 uint16_t sizedwords;
49 uint16_t instrs_count; /* expanded to account for rpt's */
50 /* NOTE: max_reg, etc, does not include registers not touched
51 * by the shader (ie. vertex fetched via VFD_DECODE but not
52 * touched by shader)
53 */
54 int8_t max_reg; /* highest GPR # used by shader */
55 int8_t max_half_reg;
56 int16_t max_const;
57
58 /* number of sync bits: */
59 uint16_t ss, sy;
60 };
61
62 struct ir3_register {
63 enum {
64 IR3_REG_CONST = 0x001,
65 IR3_REG_IMMED = 0x002,
66 IR3_REG_HALF = 0x004,
67 /* high registers are used for some things in compute shaders,
68 * for example. Seems to be for things that are global to all
69 * threads in a wave, so possibly these are global/shared by
70 * all the threads in the wave?
71 */
72 IR3_REG_HIGH = 0x008,
73 IR3_REG_RELATIV= 0x010,
74 IR3_REG_R = 0x020,
75 /* Most instructions, it seems, can do float abs/neg but not
76 * integer. The CP pass needs to know what is intended (int or
77 * float) in order to do the right thing. For this reason the
78 * abs/neg flags are split out into float and int variants. In
79 * addition, .b (bitwise) operations, the negate is actually a
80 * bitwise not, so split that out into a new flag to make it
81 * more clear.
82 */
83 IR3_REG_FNEG = 0x040,
84 IR3_REG_FABS = 0x080,
85 IR3_REG_SNEG = 0x100,
86 IR3_REG_SABS = 0x200,
87 IR3_REG_BNOT = 0x400,
88 IR3_REG_EVEN = 0x800,
89 IR3_REG_POS_INF= 0x1000,
90 /* (ei) flag, end-input? Set on last bary, presumably to signal
91 * that the shader needs no more input:
92 */
93 IR3_REG_EI = 0x2000,
94 /* meta-flags, for intermediate stages of IR, ie.
95 * before register assignment is done:
96 */
97 IR3_REG_SSA = 0x4000, /* 'instr' is ptr to assigning instr */
98 IR3_REG_ARRAY = 0x8000,
99
100 } flags;
101
102 bool merged : 1; /* half-regs conflict with full regs (ie >= a6xx) */
103
104 /* normal registers:
105 * the component is in the low two bits of the reg #, so
106 * rN.x becomes: (N << 2) | x
107 */
108 uint16_t num;
109 union {
110 /* immediate: */
111 int32_t iim_val;
112 uint32_t uim_val;
113 float fim_val;
114 /* relative: */
115 struct {
116 uint16_t id;
117 int16_t offset;
118 } array;
119 };
120
121 /* For IR3_REG_SSA, src registers contain ptr back to assigning
122 * instruction.
123 *
124 * For IR3_REG_ARRAY, the pointer is back to the last dependent
125 * array access (although the net effect is the same, it points
126 * back to a previous instruction that we depend on).
127 */
128 struct ir3_instruction *instr;
129
130 union {
131 /* used for cat5 instructions, but also for internal/IR level
132 * tracking of what registers are read/written by an instruction.
133 * wrmask may be a bad name since it is used to represent both
134 * src and dst that touch multiple adjacent registers.
135 */
136 unsigned wrmask;
137 /* for relative addressing, 32bits for array size is too small,
138 * but otoh we don't need to deal with disjoint sets, so instead
139 * use a simple size field (number of scalar components).
140 */
141 unsigned size;
142 };
143 };
144
145 /*
146 * Stupid/simple growable array implementation:
147 */
148 #define DECLARE_ARRAY(type, name) \
149 unsigned name ## _count, name ## _sz; \
150 type * name;
151
152 #define array_insert(ctx, arr, val) do { \
153 if (arr ## _count == arr ## _sz) { \
154 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
155 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
156 } \
157 arr[arr ##_count++] = val; \
158 } while (0)
159
160 struct ir3_instruction {
161 struct ir3_block *block;
162 opc_t opc;
163 enum {
164 /* (sy) flag is set on first instruction, and after sample
165 * instructions (probably just on RAW hazard).
166 */
167 IR3_INSTR_SY = 0x001,
168 /* (ss) flag is set on first instruction, and first instruction
169 * to depend on the result of "long" instructions (RAW hazard):
170 *
171 * rcp, rsq, log2, exp2, sin, cos, sqrt
172 *
173 * It seems to synchronize until all in-flight instructions are
174 * completed, for example:
175 *
176 * rsq hr1.w, hr1.w
177 * add.f hr2.z, (neg)hr2.z, hc0.y
178 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
179 * rsq hr2.x, hr2.x
180 * (rpt1)nop
181 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
182 * nop
183 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
184 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
185 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
186 *
187 * The last mul.f does not have (ss) set, presumably because the
188 * (ss) on the previous instruction does the job.
189 *
190 * The blob driver also seems to set it on WAR hazards, although
191 * not really clear if this is needed or just blob compiler being
192 * sloppy. So far I haven't found a case where removing the (ss)
193 * causes problems for WAR hazard, but I could just be getting
194 * lucky:
195 *
196 * rcp r1.y, r3.y
197 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
198 *
199 */
200 IR3_INSTR_SS = 0x002,
201 /* (jp) flag is set on jump targets:
202 */
203 IR3_INSTR_JP = 0x004,
204 IR3_INSTR_UL = 0x008,
205 IR3_INSTR_3D = 0x010,
206 IR3_INSTR_A = 0x020,
207 IR3_INSTR_O = 0x040,
208 IR3_INSTR_P = 0x080,
209 IR3_INSTR_S = 0x100,
210 IR3_INSTR_S2EN = 0x200,
211 IR3_INSTR_G = 0x400,
212 IR3_INSTR_SAT = 0x800,
213 /* meta-flags, for intermediate stages of IR, ie.
214 * before register assignment is done:
215 */
216 IR3_INSTR_MARK = 0x1000,
217 IR3_INSTR_UNUSED= 0x2000,
218 } flags;
219 uint8_t repeat;
220 uint8_t nop;
221 #ifdef DEBUG
222 unsigned regs_max;
223 #endif
224 unsigned regs_count;
225 struct ir3_register **regs;
226 union {
227 struct {
228 char inv;
229 char comp;
230 int immed;
231 struct ir3_block *target;
232 } cat0;
233 struct {
234 type_t src_type, dst_type;
235 } cat1;
236 struct {
237 enum {
238 IR3_COND_LT = 0,
239 IR3_COND_LE = 1,
240 IR3_COND_GT = 2,
241 IR3_COND_GE = 3,
242 IR3_COND_EQ = 4,
243 IR3_COND_NE = 5,
244 } condition;
245 } cat2;
246 struct {
247 unsigned samp, tex;
248 type_t type;
249 } cat5;
250 struct {
251 type_t type;
252 int src_offset;
253 int dst_offset;
254 int iim_val : 3; /* for ldgb/stgb, # of components */
255 unsigned d : 3;
256 bool typed : 1;
257 } cat6;
258 struct {
259 unsigned w : 1; /* write */
260 unsigned r : 1; /* read */
261 unsigned l : 1; /* local */
262 unsigned g : 1; /* global */
263 } cat7;
264 /* for meta-instructions, just used to hold extra data
265 * before instruction scheduling, etc
266 */
267 struct {
268 int off; /* component/offset */
269 } fo;
270 };
271
272 /* transient values used during various algorithms: */
273 union {
274 /* The instruction depth is the max dependency distance to output.
275 *
276 * You can also think of it as the "cost", if we did any sort of
277 * optimization for register footprint. Ie. a value that is just
278 * result of moving a const to a reg would have a low cost, so to
279 * it could make sense to duplicate the instruction at various
280 * points where the result is needed to reduce register footprint.
281 */
282 unsigned depth;
283 /* When we get to the RA stage, we no longer need depth, but
284 * we do need instruction's position/name:
285 */
286 struct {
287 uint16_t ip;
288 uint16_t name;
289 };
290 };
291
292 /* used for per-pass extra instruction data.
293 *
294 * TODO we should remove the per-pass data like this and 'use_count'
295 * and do something similar to what RA does w/ ir3_ra_instr_data..
296 * ie. use the ir3_count_instructions pass, and then use instr->ip
297 * to index into a table of pass-private data.
298 */
299 void *data;
300
301 int sun; /* Sethi–Ullman number, used by sched */
302 int use_count; /* currently just updated/used by cp */
303
304 /* Used during CP and RA stages. For fanin and shader inputs/
305 * outputs where we need a sequence of consecutive registers,
306 * keep track of each src instructions left (ie 'n-1') and right
307 * (ie 'n+1') neighbor. The front-end must insert enough mov's
308 * to ensure that each instruction has at most one left and at
309 * most one right neighbor. During the copy-propagation pass,
310 * we only remove mov's when we can preserve this constraint.
311 * And during the RA stage, we use the neighbor information to
312 * allocate a block of registers in one shot.
313 *
314 * TODO: maybe just add something like:
315 * struct ir3_instruction_ref {
316 * struct ir3_instruction *instr;
317 * unsigned cnt;
318 * }
319 *
320 * Or can we get away without the refcnt stuff? It seems like
321 * it should be overkill.. the problem is if, potentially after
322 * already eliminating some mov's, if you have a single mov that
323 * needs to be grouped with it's neighbors in two different
324 * places (ex. shader output and a fanin).
325 */
326 struct {
327 struct ir3_instruction *left, *right;
328 uint16_t left_cnt, right_cnt;
329 } cp;
330
331 /* an instruction can reference at most one address register amongst
332 * it's src/dst registers. Beyond that, you need to insert mov's.
333 *
334 * NOTE: do not write this directly, use ir3_instr_set_address()
335 */
336 struct ir3_instruction *address;
337
338 /* Tracking for additional dependent instructions. Used to handle
339 * barriers, WAR hazards for arrays/SSBOs/etc.
340 */
341 DECLARE_ARRAY(struct ir3_instruction *, deps);
342
343 /*
344 * From PoV of instruction scheduling, not execution (ie. ignores global/
345 * local distinction):
346 * shared image atomic SSBO everything
347 * barrier()/ - R/W R/W R/W R/W X
348 * groupMemoryBarrier()
349 * memoryBarrier() - R/W R/W
350 * (but only images declared coherent?)
351 * memoryBarrierAtomic() - R/W
352 * memoryBarrierBuffer() - R/W
353 * memoryBarrierImage() - R/W
354 * memoryBarrierShared() - R/W
355 *
356 * TODO I think for SSBO/image/shared, in cases where we can determine
357 * which variable is accessed, we don't need to care about accesses to
358 * different variables (unless declared coherent??)
359 */
360 enum {
361 IR3_BARRIER_EVERYTHING = 1 << 0,
362 IR3_BARRIER_SHARED_R = 1 << 1,
363 IR3_BARRIER_SHARED_W = 1 << 2,
364 IR3_BARRIER_IMAGE_R = 1 << 3,
365 IR3_BARRIER_IMAGE_W = 1 << 4,
366 IR3_BARRIER_BUFFER_R = 1 << 5,
367 IR3_BARRIER_BUFFER_W = 1 << 6,
368 IR3_BARRIER_ARRAY_R = 1 << 7,
369 IR3_BARRIER_ARRAY_W = 1 << 8,
370 } barrier_class, barrier_conflict;
371
372 /* Entry in ir3_block's instruction list: */
373 struct list_head node;
374
375 #ifdef DEBUG
376 uint32_t serialno;
377 #endif
378 };
379
380 static inline struct ir3_instruction *
381 ir3_neighbor_first(struct ir3_instruction *instr)
382 {
383 int cnt = 0;
384 while (instr->cp.left) {
385 instr = instr->cp.left;
386 if (++cnt > 0xffff) {
387 debug_assert(0);
388 break;
389 }
390 }
391 return instr;
392 }
393
394 static inline int ir3_neighbor_count(struct ir3_instruction *instr)
395 {
396 int num = 1;
397
398 debug_assert(!instr->cp.left);
399
400 while (instr->cp.right) {
401 num++;
402 instr = instr->cp.right;
403 if (num > 0xffff) {
404 debug_assert(0);
405 break;
406 }
407 }
408
409 return num;
410 }
411
412 struct ir3 {
413 struct ir3_compiler *compiler;
414 gl_shader_stage type;
415
416 unsigned ninputs, noutputs;
417 struct ir3_instruction **inputs;
418 struct ir3_instruction **outputs;
419
420 /* Track bary.f (and ldlv) instructions.. this is needed in
421 * scheduling to ensure that all varying fetches happen before
422 * any potential kill instructions. The hw gets grumpy if all
423 * threads in a group are killed before the last bary.f gets
424 * a chance to signal end of input (ei).
425 */
426 DECLARE_ARRAY(struct ir3_instruction *, baryfs);
427
428 /* Track all indirect instructions (read and write). To avoid
429 * deadlock scenario where an address register gets scheduled,
430 * but other dependent src instructions cannot be scheduled due
431 * to dependency on a *different* address register value, the
432 * scheduler needs to ensure that all dependencies other than
433 * the instruction other than the address register are scheduled
434 * before the one that writes the address register. Having a
435 * convenient list of instructions that reference some address
436 * register simplifies this.
437 */
438 DECLARE_ARRAY(struct ir3_instruction *, indirects);
439
440 /* and same for instructions that consume predicate register: */
441 DECLARE_ARRAY(struct ir3_instruction *, predicates);
442
443 /* Track texture sample instructions which need texture state
444 * patched in (for astc-srgb workaround):
445 */
446 DECLARE_ARRAY(struct ir3_instruction *, astc_srgb);
447
448 /* List of blocks: */
449 struct list_head block_list;
450
451 /* List of ir3_array's: */
452 struct list_head array_list;
453
454 unsigned max_sun; /* max Sethi–Ullman number */
455
456 #ifdef DEBUG
457 unsigned block_count, instr_count;
458 #endif
459 };
460
461 struct ir3_array {
462 struct list_head node;
463 unsigned length;
464 unsigned id;
465
466 struct nir_register *r;
467
468 /* To avoid array write's from getting DCE'd, keep track of the
469 * most recent write. Any array access depends on the most
470 * recent write. This way, nothing depends on writes after the
471 * last read. But all the writes that happen before that have
472 * something depending on them
473 */
474 struct ir3_instruction *last_write;
475
476 /* extra stuff used in RA pass: */
477 unsigned base; /* base vreg name */
478 unsigned reg; /* base physical reg */
479 uint16_t start_ip, end_ip;
480 };
481
482 struct ir3_array * ir3_lookup_array(struct ir3 *ir, unsigned id);
483
484 struct ir3_block {
485 struct list_head node;
486 struct ir3 *shader;
487
488 const struct nir_block *nblock;
489
490 struct list_head instr_list; /* list of ir3_instruction */
491
492 /* each block has either one or two successors.. in case of
493 * two successors, 'condition' decides which one to follow.
494 * A block preceding an if/else has two successors.
495 */
496 struct ir3_instruction *condition;
497 struct ir3_block *successors[2];
498
499 struct set *predecessors; /* set of ir3_block */
500
501 uint16_t start_ip, end_ip;
502
503 /* Track instructions which do not write a register but other-
504 * wise must not be discarded (such as kill, stg, etc)
505 */
506 DECLARE_ARRAY(struct ir3_instruction *, keeps);
507
508 /* used for per-pass extra block data. Mainly used right
509 * now in RA step to track livein/liveout.
510 */
511 void *data;
512
513 #ifdef DEBUG
514 uint32_t serialno;
515 #endif
516 };
517
518 static inline uint32_t
519 block_id(struct ir3_block *block)
520 {
521 #ifdef DEBUG
522 return block->serialno;
523 #else
524 return (uint32_t)(unsigned long)block;
525 #endif
526 }
527
528 struct ir3 * ir3_create(struct ir3_compiler *compiler,
529 gl_shader_stage type, unsigned nin, unsigned nout);
530 void ir3_destroy(struct ir3 *shader);
531 void * ir3_assemble(struct ir3 *shader,
532 struct ir3_info *info, uint32_t gpu_id);
533 void * ir3_alloc(struct ir3 *shader, int sz);
534
535 struct ir3_block * ir3_block_create(struct ir3 *shader);
536
537 struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc);
538 struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
539 opc_t opc, int nreg);
540 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
541 void ir3_instr_add_dep(struct ir3_instruction *instr, struct ir3_instruction *dep);
542 const char *ir3_instr_name(struct ir3_instruction *instr);
543
544 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
545 int num, int flags);
546 struct ir3_register * ir3_reg_clone(struct ir3 *shader,
547 struct ir3_register *reg);
548
549 void ir3_instr_set_address(struct ir3_instruction *instr,
550 struct ir3_instruction *addr);
551
552 static inline bool ir3_instr_check_mark(struct ir3_instruction *instr)
553 {
554 if (instr->flags & IR3_INSTR_MARK)
555 return true; /* already visited */
556 instr->flags |= IR3_INSTR_MARK;
557 return false;
558 }
559
560 void ir3_block_clear_mark(struct ir3_block *block);
561 void ir3_clear_mark(struct ir3 *shader);
562
563 unsigned ir3_count_instructions(struct ir3 *ir);
564
565 static inline int ir3_instr_regno(struct ir3_instruction *instr,
566 struct ir3_register *reg)
567 {
568 unsigned i;
569 for (i = 0; i < instr->regs_count; i++)
570 if (reg == instr->regs[i])
571 return i;
572 return -1;
573 }
574
575
576 #define MAX_ARRAYS 16
577
578 /* comp:
579 * 0 - x
580 * 1 - y
581 * 2 - z
582 * 3 - w
583 */
584 static inline uint32_t regid(int num, int comp)
585 {
586 return (num << 2) | (comp & 0x3);
587 }
588
589 static inline uint32_t reg_num(struct ir3_register *reg)
590 {
591 return reg->num >> 2;
592 }
593
594 static inline uint32_t reg_comp(struct ir3_register *reg)
595 {
596 return reg->num & 0x3;
597 }
598
599 static inline bool is_flow(struct ir3_instruction *instr)
600 {
601 return (opc_cat(instr->opc) == 0);
602 }
603
604 static inline bool is_kill(struct ir3_instruction *instr)
605 {
606 return instr->opc == OPC_KILL;
607 }
608
609 static inline bool is_nop(struct ir3_instruction *instr)
610 {
611 return instr->opc == OPC_NOP;
612 }
613
614 static inline bool is_same_type_reg(struct ir3_register *reg1,
615 struct ir3_register *reg2)
616 {
617 unsigned type_reg1 = (reg1->flags & (IR3_REG_HIGH | IR3_REG_HALF));
618 unsigned type_reg2 = (reg2->flags & (IR3_REG_HIGH | IR3_REG_HALF));
619
620 if (type_reg1 ^ type_reg2)
621 return false;
622 else
623 return true;
624 }
625
626 /* Is it a non-transformative (ie. not type changing) mov? This can
627 * also include absneg.s/absneg.f, which for the most part can be
628 * treated as a mov (single src argument).
629 */
630 static inline bool is_same_type_mov(struct ir3_instruction *instr)
631 {
632 struct ir3_register *dst;
633
634 switch (instr->opc) {
635 case OPC_MOV:
636 if (instr->cat1.src_type != instr->cat1.dst_type)
637 return false;
638 break;
639 case OPC_ABSNEG_F:
640 case OPC_ABSNEG_S:
641 if (instr->flags & IR3_INSTR_SAT)
642 return false;
643 /* If the type of dest reg and src reg are different,
644 * it shouldn't be considered as same type mov */
645 if (!is_same_type_reg(instr->regs[0], instr->regs[1]))
646 return false;
647 break;
648 default:
649 return false;
650 }
651
652 dst = instr->regs[0];
653
654 /* mov's that write to a0.x or p0.x are special: */
655 if (dst->num == regid(REG_P0, 0))
656 return false;
657 if (dst->num == regid(REG_A0, 0))
658 return false;
659
660 if (dst->flags & (IR3_REG_RELATIV | IR3_REG_ARRAY))
661 return false;
662
663 return true;
664 }
665
666 static inline bool is_alu(struct ir3_instruction *instr)
667 {
668 return (1 <= opc_cat(instr->opc)) && (opc_cat(instr->opc) <= 3);
669 }
670
671 static inline bool is_sfu(struct ir3_instruction *instr)
672 {
673 return (opc_cat(instr->opc) == 4);
674 }
675
676 static inline bool is_tex(struct ir3_instruction *instr)
677 {
678 return (opc_cat(instr->opc) == 5);
679 }
680
681 static inline bool is_mem(struct ir3_instruction *instr)
682 {
683 return (opc_cat(instr->opc) == 6);
684 }
685
686 static inline bool is_barrier(struct ir3_instruction *instr)
687 {
688 return (opc_cat(instr->opc) == 7);
689 }
690
691 static inline bool
692 is_store(struct ir3_instruction *instr)
693 {
694 /* these instructions, the "destination" register is
695 * actually a source, the address to store to.
696 */
697 switch (instr->opc) {
698 case OPC_STG:
699 case OPC_STGB:
700 case OPC_STIB:
701 case OPC_STP:
702 case OPC_STL:
703 case OPC_STLW:
704 case OPC_L2G:
705 case OPC_G2L:
706 return true;
707 default:
708 return false;
709 }
710 }
711
712 static inline bool is_load(struct ir3_instruction *instr)
713 {
714 switch (instr->opc) {
715 case OPC_LDG:
716 case OPC_LDGB:
717 case OPC_LDIB:
718 case OPC_LDL:
719 case OPC_LDP:
720 case OPC_L2G:
721 case OPC_LDLW:
722 case OPC_LDC:
723 case OPC_LDLV:
724 /* probably some others too.. */
725 return true;
726 default:
727 return false;
728 }
729 }
730
731 static inline bool is_input(struct ir3_instruction *instr)
732 {
733 /* in some cases, ldlv is used to fetch varying without
734 * interpolation.. fortunately inloc is the first src
735 * register in either case
736 */
737 switch (instr->opc) {
738 case OPC_LDLV:
739 case OPC_BARY_F:
740 return true;
741 default:
742 return false;
743 }
744 }
745
746 static inline bool is_bool(struct ir3_instruction *instr)
747 {
748 switch (instr->opc) {
749 case OPC_CMPS_F:
750 case OPC_CMPS_S:
751 case OPC_CMPS_U:
752 return true;
753 default:
754 return false;
755 }
756 }
757
758 static inline bool is_meta(struct ir3_instruction *instr)
759 {
760 /* TODO how should we count PHI (and maybe fan-in/out) which
761 * might actually contribute some instructions to the final
762 * result?
763 */
764 return (opc_cat(instr->opc) == -1);
765 }
766
767 static inline unsigned dest_regs(struct ir3_instruction *instr)
768 {
769 if ((instr->regs_count == 0) || is_store(instr))
770 return 0;
771
772 return util_last_bit(instr->regs[0]->wrmask);
773 }
774
775 static inline bool writes_addr(struct ir3_instruction *instr)
776 {
777 if (instr->regs_count > 0) {
778 struct ir3_register *dst = instr->regs[0];
779 return reg_num(dst) == REG_A0;
780 }
781 return false;
782 }
783
784 static inline bool writes_pred(struct ir3_instruction *instr)
785 {
786 if (instr->regs_count > 0) {
787 struct ir3_register *dst = instr->regs[0];
788 return reg_num(dst) == REG_P0;
789 }
790 return false;
791 }
792
793 /* returns defining instruction for reg */
794 /* TODO better name */
795 static inline struct ir3_instruction *ssa(struct ir3_register *reg)
796 {
797 if (reg->flags & (IR3_REG_SSA | IR3_REG_ARRAY)) {
798 return reg->instr;
799 }
800 return NULL;
801 }
802
803 static inline bool conflicts(struct ir3_instruction *a,
804 struct ir3_instruction *b)
805 {
806 return (a && b) && (a != b);
807 }
808
809 static inline bool reg_gpr(struct ir3_register *r)
810 {
811 if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED))
812 return false;
813 if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0))
814 return false;
815 return true;
816 }
817
818 static inline type_t half_type(type_t type)
819 {
820 switch (type) {
821 case TYPE_F32: return TYPE_F16;
822 case TYPE_U32: return TYPE_U16;
823 case TYPE_S32: return TYPE_S16;
824 case TYPE_F16:
825 case TYPE_U16:
826 case TYPE_S16:
827 return type;
828 default:
829 assert(0);
830 return ~0;
831 }
832 }
833
834 /* some cat2 instructions (ie. those which are not float) can embed an
835 * immediate:
836 */
837 static inline bool ir3_cat2_int(opc_t opc)
838 {
839 switch (opc) {
840 case OPC_ADD_U:
841 case OPC_ADD_S:
842 case OPC_SUB_U:
843 case OPC_SUB_S:
844 case OPC_CMPS_U:
845 case OPC_CMPS_S:
846 case OPC_MIN_U:
847 case OPC_MIN_S:
848 case OPC_MAX_U:
849 case OPC_MAX_S:
850 case OPC_CMPV_U:
851 case OPC_CMPV_S:
852 case OPC_MUL_U:
853 case OPC_MUL_S:
854 case OPC_MULL_U:
855 case OPC_CLZ_S:
856 case OPC_ABSNEG_S:
857 case OPC_AND_B:
858 case OPC_OR_B:
859 case OPC_NOT_B:
860 case OPC_XOR_B:
861 case OPC_BFREV_B:
862 case OPC_CLZ_B:
863 case OPC_SHL_B:
864 case OPC_SHR_B:
865 case OPC_ASHR_B:
866 case OPC_MGEN_B:
867 case OPC_GETBIT_B:
868 case OPC_CBITS_B:
869 case OPC_BARY_F:
870 return true;
871
872 default:
873 return false;
874 }
875 }
876
877 static inline bool ir3_cat2_float(opc_t opc)
878 {
879 switch (opc) {
880 case OPC_ADD_F:
881 case OPC_MIN_F:
882 case OPC_MAX_F:
883 case OPC_MUL_F:
884 case OPC_SIGN_F:
885 case OPC_CMPS_F:
886 case OPC_ABSNEG_F:
887 case OPC_CMPV_F:
888 case OPC_FLOOR_F:
889 case OPC_CEIL_F:
890 case OPC_RNDNE_F:
891 case OPC_RNDAZ_F:
892 case OPC_TRUNC_F:
893 return true;
894
895 default:
896 return false;
897 }
898 }
899
900 static inline bool ir3_cat3_float(opc_t opc)
901 {
902 switch (opc) {
903 case OPC_MAD_F16:
904 case OPC_MAD_F32:
905 case OPC_SEL_F16:
906 case OPC_SEL_F32:
907 return true;
908 default:
909 return false;
910 }
911 }
912
913 /* map cat2 instruction to valid abs/neg flags: */
914 static inline unsigned ir3_cat2_absneg(opc_t opc)
915 {
916 switch (opc) {
917 case OPC_ADD_F:
918 case OPC_MIN_F:
919 case OPC_MAX_F:
920 case OPC_MUL_F:
921 case OPC_SIGN_F:
922 case OPC_CMPS_F:
923 case OPC_ABSNEG_F:
924 case OPC_CMPV_F:
925 case OPC_FLOOR_F:
926 case OPC_CEIL_F:
927 case OPC_RNDNE_F:
928 case OPC_RNDAZ_F:
929 case OPC_TRUNC_F:
930 case OPC_BARY_F:
931 return IR3_REG_FABS | IR3_REG_FNEG;
932
933 case OPC_ADD_U:
934 case OPC_ADD_S:
935 case OPC_SUB_U:
936 case OPC_SUB_S:
937 case OPC_CMPS_U:
938 case OPC_CMPS_S:
939 case OPC_MIN_U:
940 case OPC_MIN_S:
941 case OPC_MAX_U:
942 case OPC_MAX_S:
943 case OPC_CMPV_U:
944 case OPC_CMPV_S:
945 case OPC_MUL_U:
946 case OPC_MUL_S:
947 case OPC_MULL_U:
948 case OPC_CLZ_S:
949 return 0;
950
951 case OPC_ABSNEG_S:
952 return IR3_REG_SABS | IR3_REG_SNEG;
953
954 case OPC_AND_B:
955 case OPC_OR_B:
956 case OPC_NOT_B:
957 case OPC_XOR_B:
958 case OPC_BFREV_B:
959 case OPC_CLZ_B:
960 case OPC_SHL_B:
961 case OPC_SHR_B:
962 case OPC_ASHR_B:
963 case OPC_MGEN_B:
964 case OPC_GETBIT_B:
965 case OPC_CBITS_B:
966 return IR3_REG_BNOT;
967
968 default:
969 return 0;
970 }
971 }
972
973 /* map cat3 instructions to valid abs/neg flags: */
974 static inline unsigned ir3_cat3_absneg(opc_t opc)
975 {
976 switch (opc) {
977 case OPC_MAD_F16:
978 case OPC_MAD_F32:
979 case OPC_SEL_F16:
980 case OPC_SEL_F32:
981 return IR3_REG_FNEG;
982
983 case OPC_MAD_U16:
984 case OPC_MADSH_U16:
985 case OPC_MAD_S16:
986 case OPC_MADSH_M16:
987 case OPC_MAD_U24:
988 case OPC_MAD_S24:
989 case OPC_SEL_S16:
990 case OPC_SEL_S32:
991 case OPC_SAD_S16:
992 case OPC_SAD_S32:
993 /* neg *may* work on 3rd src.. */
994
995 case OPC_SEL_B16:
996 case OPC_SEL_B32:
997
998 default:
999 return 0;
1000 }
1001 }
1002
1003 #define MASK(n) ((1 << (n)) - 1)
1004
1005 /* iterator for an instructions's sources (reg), also returns src #: */
1006 #define foreach_src_n(__srcreg, __n, __instr) \
1007 if ((__instr)->regs_count) \
1008 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
1009 if ((__srcreg = (__instr)->regs[__n + 1]))
1010
1011 /* iterator for an instructions's sources (reg): */
1012 #define foreach_src(__srcreg, __instr) \
1013 foreach_src_n(__srcreg, __i, __instr)
1014
1015 static inline unsigned __ssa_src_cnt(struct ir3_instruction *instr)
1016 {
1017 unsigned cnt = instr->regs_count + instr->deps_count;
1018 if (instr->address)
1019 cnt++;
1020 return cnt;
1021 }
1022
1023 static inline struct ir3_instruction * __ssa_src_n(struct ir3_instruction *instr, unsigned n)
1024 {
1025 if (n == (instr->regs_count + instr->deps_count))
1026 return instr->address;
1027 if (n >= instr->regs_count)
1028 return instr->deps[n - instr->regs_count];
1029 return ssa(instr->regs[n]);
1030 }
1031
1032 static inline bool __is_false_dep(struct ir3_instruction *instr, unsigned n)
1033 {
1034 if (n == (instr->regs_count + instr->deps_count))
1035 return false;
1036 if (n >= instr->regs_count)
1037 return true;
1038 return false;
1039 }
1040
1041 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
1042
1043 /* iterator for an instruction's SSA sources (instr), also returns src #: */
1044 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
1045 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
1046 if ((__srcinst = __ssa_src_n(__instr, __n)))
1047
1048 /* iterator for an instruction's SSA sources (instr): */
1049 #define foreach_ssa_src(__srcinst, __instr) \
1050 foreach_ssa_src_n(__srcinst, __i, __instr)
1051
1052
1053 /* dump: */
1054 void ir3_print(struct ir3 *ir);
1055 void ir3_print_instr(struct ir3_instruction *instr);
1056
1057 /* depth calculation: */
1058 int ir3_delayslots(struct ir3_instruction *assigner,
1059 struct ir3_instruction *consumer, unsigned n);
1060 void ir3_insert_by_depth(struct ir3_instruction *instr, struct list_head *list);
1061 void ir3_depth(struct ir3 *ir);
1062
1063 /* copy-propagate: */
1064 struct ir3_shader_variant;
1065 void ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so);
1066
1067 /* group neighbors and insert mov's to resolve conflicts: */
1068 void ir3_group(struct ir3 *ir);
1069
1070 /* Sethi–Ullman numbering: */
1071 void ir3_sun(struct ir3 *ir);
1072
1073 /* scheduling: */
1074 void ir3_sched_add_deps(struct ir3 *ir);
1075 int ir3_sched(struct ir3 *ir);
1076
1077 void ir3_a6xx_fixup_atomic_dests(struct ir3 *ir, struct ir3_shader_variant *so);
1078
1079 /* register assignment: */
1080 struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler);
1081 int ir3_ra(struct ir3_shader_variant *v, struct ir3_instruction **precolor, unsigned nprecolor);
1082
1083 /* legalize: */
1084 void ir3_legalize(struct ir3 *ir, bool *has_ssbo, bool *need_pixlod, int *max_bary);
1085
1086 /* ************************************************************************* */
1087 /* instruction helpers */
1088
1089 static inline struct ir3_instruction *
1090 create_immed_typed(struct ir3_block *block, uint32_t val, type_t type)
1091 {
1092 struct ir3_instruction *mov;
1093 unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0;
1094
1095 mov = ir3_instr_create(block, OPC_MOV);
1096 mov->cat1.src_type = type;
1097 mov->cat1.dst_type = type;
1098 ir3_reg_create(mov, 0, flags);
1099 ir3_reg_create(mov, 0, IR3_REG_IMMED)->uim_val = val;
1100
1101 return mov;
1102 }
1103
1104 static inline struct ir3_instruction *
1105 create_immed(struct ir3_block *block, uint32_t val)
1106 {
1107 return create_immed_typed(block, val, TYPE_U32);
1108 }
1109
1110 static inline struct ir3_instruction *
1111 create_uniform_typed(struct ir3_block *block, unsigned n, type_t type)
1112 {
1113 struct ir3_instruction *mov;
1114 unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0;
1115
1116 mov = ir3_instr_create(block, OPC_MOV);
1117 mov->cat1.src_type = type;
1118 mov->cat1.dst_type = type;
1119 ir3_reg_create(mov, 0, flags);
1120 ir3_reg_create(mov, n, IR3_REG_CONST | flags);
1121
1122 return mov;
1123 }
1124
1125 static inline struct ir3_instruction *
1126 create_uniform(struct ir3_block *block, unsigned n)
1127 {
1128 return create_uniform_typed(block, n, TYPE_F32);
1129 }
1130
1131 static inline struct ir3_instruction *
1132 create_uniform_indirect(struct ir3_block *block, int n,
1133 struct ir3_instruction *address)
1134 {
1135 struct ir3_instruction *mov;
1136
1137 mov = ir3_instr_create(block, OPC_MOV);
1138 mov->cat1.src_type = TYPE_U32;
1139 mov->cat1.dst_type = TYPE_U32;
1140 ir3_reg_create(mov, 0, 0);
1141 ir3_reg_create(mov, 0, IR3_REG_CONST | IR3_REG_RELATIV)->array.offset = n;
1142
1143 ir3_instr_set_address(mov, address);
1144
1145 return mov;
1146 }
1147
1148 /* creates SSA src of correct type (ie. half vs full precision) */
1149 static inline struct ir3_register * __ssa_src(struct ir3_instruction *instr,
1150 struct ir3_instruction *src, unsigned flags)
1151 {
1152 struct ir3_register *reg;
1153 if (src->regs[0]->flags & IR3_REG_HALF)
1154 flags |= IR3_REG_HALF;
1155 reg = ir3_reg_create(instr, 0, IR3_REG_SSA | flags);
1156 reg->instr = src;
1157 reg->wrmask = src->regs[0]->wrmask;
1158 return reg;
1159 }
1160
1161 static inline struct ir3_instruction *
1162 ir3_MOV(struct ir3_block *block, struct ir3_instruction *src, type_t type)
1163 {
1164 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1165 ir3_reg_create(instr, 0, 0); /* dst */
1166 if (src->regs[0]->flags & IR3_REG_ARRAY) {
1167 struct ir3_register *src_reg = __ssa_src(instr, src, IR3_REG_ARRAY);
1168 src_reg->array = src->regs[0]->array;
1169 } else {
1170 __ssa_src(instr, src, src->regs[0]->flags & IR3_REG_HIGH);
1171 }
1172 debug_assert(!(src->regs[0]->flags & IR3_REG_RELATIV));
1173 instr->cat1.src_type = type;
1174 instr->cat1.dst_type = type;
1175 return instr;
1176 }
1177
1178 static inline struct ir3_instruction *
1179 ir3_COV(struct ir3_block *block, struct ir3_instruction *src,
1180 type_t src_type, type_t dst_type)
1181 {
1182 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1183 unsigned dst_flags = (type_size(dst_type) < 32) ? IR3_REG_HALF : 0;
1184 unsigned src_flags = (type_size(src_type) < 32) ? IR3_REG_HALF : 0;
1185
1186 debug_assert((src->regs[0]->flags & IR3_REG_HALF) == src_flags);
1187
1188 ir3_reg_create(instr, 0, dst_flags); /* dst */
1189 __ssa_src(instr, src, 0);
1190 instr->cat1.src_type = src_type;
1191 instr->cat1.dst_type = dst_type;
1192 debug_assert(!(src->regs[0]->flags & IR3_REG_ARRAY));
1193 return instr;
1194 }
1195
1196 static inline struct ir3_instruction *
1197 ir3_NOP(struct ir3_block *block)
1198 {
1199 return ir3_instr_create(block, OPC_NOP);
1200 }
1201
1202 #define IR3_INSTR_0 0
1203
1204 #define __INSTR0(flag, name, opc) \
1205 static inline struct ir3_instruction * \
1206 ir3_##name(struct ir3_block *block) \
1207 { \
1208 struct ir3_instruction *instr = \
1209 ir3_instr_create(block, opc); \
1210 instr->flags |= flag; \
1211 return instr; \
1212 }
1213 #define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name)
1214 #define INSTR0(name) __INSTR0(0, name, OPC_##name)
1215
1216 #define __INSTR1(flag, name, opc) \
1217 static inline struct ir3_instruction * \
1218 ir3_##name(struct ir3_block *block, \
1219 struct ir3_instruction *a, unsigned aflags) \
1220 { \
1221 struct ir3_instruction *instr = \
1222 ir3_instr_create(block, opc); \
1223 ir3_reg_create(instr, 0, 0); /* dst */ \
1224 __ssa_src(instr, a, aflags); \
1225 instr->flags |= flag; \
1226 return instr; \
1227 }
1228 #define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name)
1229 #define INSTR1(name) __INSTR1(0, name, OPC_##name)
1230
1231 #define __INSTR2(flag, name, opc) \
1232 static inline struct ir3_instruction * \
1233 ir3_##name(struct ir3_block *block, \
1234 struct ir3_instruction *a, unsigned aflags, \
1235 struct ir3_instruction *b, unsigned bflags) \
1236 { \
1237 struct ir3_instruction *instr = \
1238 ir3_instr_create(block, opc); \
1239 ir3_reg_create(instr, 0, 0); /* dst */ \
1240 __ssa_src(instr, a, aflags); \
1241 __ssa_src(instr, b, bflags); \
1242 instr->flags |= flag; \
1243 return instr; \
1244 }
1245 #define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name)
1246 #define INSTR2(name) __INSTR2(0, name, OPC_##name)
1247
1248 #define __INSTR3(flag, name, opc) \
1249 static inline struct ir3_instruction * \
1250 ir3_##name(struct ir3_block *block, \
1251 struct ir3_instruction *a, unsigned aflags, \
1252 struct ir3_instruction *b, unsigned bflags, \
1253 struct ir3_instruction *c, unsigned cflags) \
1254 { \
1255 struct ir3_instruction *instr = \
1256 ir3_instr_create2(block, opc, 4); \
1257 ir3_reg_create(instr, 0, 0); /* dst */ \
1258 __ssa_src(instr, a, aflags); \
1259 __ssa_src(instr, b, bflags); \
1260 __ssa_src(instr, c, cflags); \
1261 instr->flags |= flag; \
1262 return instr; \
1263 }
1264 #define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name)
1265 #define INSTR3(name) __INSTR3(0, name, OPC_##name)
1266
1267 #define __INSTR4(flag, name, opc) \
1268 static inline struct ir3_instruction * \
1269 ir3_##name(struct ir3_block *block, \
1270 struct ir3_instruction *a, unsigned aflags, \
1271 struct ir3_instruction *b, unsigned bflags, \
1272 struct ir3_instruction *c, unsigned cflags, \
1273 struct ir3_instruction *d, unsigned dflags) \
1274 { \
1275 struct ir3_instruction *instr = \
1276 ir3_instr_create2(block, opc, 5); \
1277 ir3_reg_create(instr, 0, 0); /* dst */ \
1278 __ssa_src(instr, a, aflags); \
1279 __ssa_src(instr, b, bflags); \
1280 __ssa_src(instr, c, cflags); \
1281 __ssa_src(instr, d, dflags); \
1282 instr->flags |= flag; \
1283 return instr; \
1284 }
1285 #define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name)
1286 #define INSTR4(name) __INSTR4(0, name, OPC_##name)
1287
1288 /* cat0 instructions: */
1289 INSTR0(BR)
1290 INSTR0(JUMP)
1291 INSTR1(KILL)
1292 INSTR0(END)
1293 INSTR0(CHSH)
1294 INSTR0(CHMASK)
1295
1296 /* cat2 instructions, most 2 src but some 1 src: */
1297 INSTR2(ADD_F)
1298 INSTR2(MIN_F)
1299 INSTR2(MAX_F)
1300 INSTR2(MUL_F)
1301 INSTR1(SIGN_F)
1302 INSTR2(CMPS_F)
1303 INSTR1(ABSNEG_F)
1304 INSTR2(CMPV_F)
1305 INSTR1(FLOOR_F)
1306 INSTR1(CEIL_F)
1307 INSTR1(RNDNE_F)
1308 INSTR1(RNDAZ_F)
1309 INSTR1(TRUNC_F)
1310 INSTR2(ADD_U)
1311 INSTR2(ADD_S)
1312 INSTR2(SUB_U)
1313 INSTR2(SUB_S)
1314 INSTR2(CMPS_U)
1315 INSTR2(CMPS_S)
1316 INSTR2(MIN_U)
1317 INSTR2(MIN_S)
1318 INSTR2(MAX_U)
1319 INSTR2(MAX_S)
1320 INSTR1(ABSNEG_S)
1321 INSTR2(AND_B)
1322 INSTR2(OR_B)
1323 INSTR1(NOT_B)
1324 INSTR2(XOR_B)
1325 INSTR2(CMPV_U)
1326 INSTR2(CMPV_S)
1327 INSTR2(MUL_U)
1328 INSTR2(MUL_S)
1329 INSTR2(MULL_U)
1330 INSTR1(BFREV_B)
1331 INSTR1(CLZ_S)
1332 INSTR1(CLZ_B)
1333 INSTR2(SHL_B)
1334 INSTR2(SHR_B)
1335 INSTR2(ASHR_B)
1336 INSTR2(BARY_F)
1337 INSTR2(MGEN_B)
1338 INSTR2(GETBIT_B)
1339 INSTR1(SETRM)
1340 INSTR1(CBITS_B)
1341 INSTR2(SHB)
1342 INSTR2(MSAD)
1343
1344 /* cat3 instructions: */
1345 INSTR3(MAD_U16)
1346 INSTR3(MADSH_U16)
1347 INSTR3(MAD_S16)
1348 INSTR3(MADSH_M16)
1349 INSTR3(MAD_U24)
1350 INSTR3(MAD_S24)
1351 INSTR3(MAD_F16)
1352 INSTR3(MAD_F32)
1353 INSTR3(SEL_B16)
1354 INSTR3(SEL_B32)
1355 INSTR3(SEL_S16)
1356 INSTR3(SEL_S32)
1357 INSTR3(SEL_F16)
1358 INSTR3(SEL_F32)
1359 INSTR3(SAD_S16)
1360 INSTR3(SAD_S32)
1361
1362 /* cat4 instructions: */
1363 INSTR1(RCP)
1364 INSTR1(RSQ)
1365 INSTR1(LOG2)
1366 INSTR1(EXP2)
1367 INSTR1(SIN)
1368 INSTR1(COS)
1369 INSTR1(SQRT)
1370
1371 /* cat5 instructions: */
1372 INSTR1(DSX)
1373 INSTR1(DSY)
1374 INSTR1F(3D, DSX)
1375 INSTR1F(3D, DSY)
1376 INSTR1(RGETPOS)
1377
1378 static inline struct ir3_instruction *
1379 ir3_SAM(struct ir3_block *block, opc_t opc, type_t type,
1380 unsigned wrmask, unsigned flags, struct ir3_instruction *samp_tex,
1381 struct ir3_instruction *src0, struct ir3_instruction *src1)
1382 {
1383 struct ir3_instruction *sam;
1384 struct ir3_register *reg;
1385
1386 sam = ir3_instr_create(block, opc);
1387 sam->flags |= flags | IR3_INSTR_S2EN;
1388 ir3_reg_create(sam, 0, 0)->wrmask = wrmask;
1389 __ssa_src(sam, samp_tex, IR3_REG_HALF);
1390 if (src0) {
1391 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
1392 reg->wrmask = (1 << (src0->regs_count - 1)) - 1;
1393 reg->instr = src0;
1394 }
1395 if (src1) {
1396 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
1397 reg->instr = src1;
1398 reg->wrmask = (1 << (src1->regs_count - 1)) - 1;
1399 }
1400 sam->cat5.type = type;
1401
1402 return sam;
1403 }
1404
1405 /* cat6 instructions: */
1406 INSTR2(LDLV)
1407 INSTR3(LDG)
1408 INSTR3(LDL)
1409 INSTR3(LDLW)
1410 INSTR3(STG)
1411 INSTR3(STL)
1412 INSTR3(STLW)
1413 INSTR1(RESINFO)
1414 INSTR1(RESFMT)
1415 INSTR2(ATOMIC_ADD)
1416 INSTR2(ATOMIC_SUB)
1417 INSTR2(ATOMIC_XCHG)
1418 INSTR2(ATOMIC_INC)
1419 INSTR2(ATOMIC_DEC)
1420 INSTR2(ATOMIC_CMPXCHG)
1421 INSTR2(ATOMIC_MIN)
1422 INSTR2(ATOMIC_MAX)
1423 INSTR2(ATOMIC_AND)
1424 INSTR2(ATOMIC_OR)
1425 INSTR2(ATOMIC_XOR)
1426 #if GPU >= 600
1427 INSTR3(STIB);
1428 INSTR2(LDIB);
1429 INSTR3F(G, ATOMIC_ADD)
1430 INSTR3F(G, ATOMIC_SUB)
1431 INSTR3F(G, ATOMIC_XCHG)
1432 INSTR3F(G, ATOMIC_INC)
1433 INSTR3F(G, ATOMIC_DEC)
1434 INSTR3F(G, ATOMIC_CMPXCHG)
1435 INSTR3F(G, ATOMIC_MIN)
1436 INSTR3F(G, ATOMIC_MAX)
1437 INSTR3F(G, ATOMIC_AND)
1438 INSTR3F(G, ATOMIC_OR)
1439 INSTR3F(G, ATOMIC_XOR)
1440 #elif GPU >= 400
1441 INSTR3(LDGB)
1442 INSTR4(STGB)
1443 INSTR4(STIB)
1444 INSTR4F(G, ATOMIC_ADD)
1445 INSTR4F(G, ATOMIC_SUB)
1446 INSTR4F(G, ATOMIC_XCHG)
1447 INSTR4F(G, ATOMIC_INC)
1448 INSTR4F(G, ATOMIC_DEC)
1449 INSTR4F(G, ATOMIC_CMPXCHG)
1450 INSTR4F(G, ATOMIC_MIN)
1451 INSTR4F(G, ATOMIC_MAX)
1452 INSTR4F(G, ATOMIC_AND)
1453 INSTR4F(G, ATOMIC_OR)
1454 INSTR4F(G, ATOMIC_XOR)
1455 #endif
1456
1457 /* cat7 instructions: */
1458 INSTR0(BAR)
1459 INSTR0(FENCE)
1460
1461 /* ************************************************************************* */
1462 /* split this out or find some helper to use.. like main/bitset.h.. */
1463
1464 #include <string.h>
1465
1466 #define MAX_REG 256
1467
1468 typedef uint8_t regmask_t[2 * MAX_REG / 8];
1469
1470 static inline unsigned regmask_idx(struct ir3_register *reg)
1471 {
1472 unsigned num = (reg->flags & IR3_REG_RELATIV) ? reg->array.offset : reg->num;
1473 debug_assert(num < MAX_REG);
1474 if (reg->flags & IR3_REG_HALF) {
1475 if (reg->merged) {
1476 num /= 2;
1477 } else {
1478 num += MAX_REG;
1479 }
1480 }
1481 return num;
1482 }
1483
1484 static inline void regmask_init(regmask_t *regmask)
1485 {
1486 memset(regmask, 0, sizeof(*regmask));
1487 }
1488
1489 static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg)
1490 {
1491 unsigned idx = regmask_idx(reg);
1492 if (reg->flags & IR3_REG_RELATIV) {
1493 unsigned i;
1494 for (i = 0; i < reg->size; i++, idx++)
1495 (*regmask)[idx / 8] |= 1 << (idx % 8);
1496 } else {
1497 unsigned mask;
1498 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1499 if (mask & 1)
1500 (*regmask)[idx / 8] |= 1 << (idx % 8);
1501 }
1502 }
1503
1504 static inline void regmask_or(regmask_t *dst, regmask_t *a, regmask_t *b)
1505 {
1506 unsigned i;
1507 for (i = 0; i < ARRAY_SIZE(*dst); i++)
1508 (*dst)[i] = (*a)[i] | (*b)[i];
1509 }
1510
1511 /* set bits in a if not set in b, conceptually:
1512 * a |= (reg & ~b)
1513 */
1514 static inline void regmask_set_if_not(regmask_t *a,
1515 struct ir3_register *reg, regmask_t *b)
1516 {
1517 unsigned idx = regmask_idx(reg);
1518 if (reg->flags & IR3_REG_RELATIV) {
1519 unsigned i;
1520 for (i = 0; i < reg->size; i++, idx++)
1521 if (!((*b)[idx / 8] & (1 << (idx % 8))))
1522 (*a)[idx / 8] |= 1 << (idx % 8);
1523 } else {
1524 unsigned mask;
1525 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1526 if (mask & 1)
1527 if (!((*b)[idx / 8] & (1 << (idx % 8))))
1528 (*a)[idx / 8] |= 1 << (idx % 8);
1529 }
1530 }
1531
1532 static inline bool regmask_get(regmask_t *regmask,
1533 struct ir3_register *reg)
1534 {
1535 unsigned idx = regmask_idx(reg);
1536 if (reg->flags & IR3_REG_RELATIV) {
1537 unsigned i;
1538 for (i = 0; i < reg->size; i++, idx++)
1539 if ((*regmask)[idx / 8] & (1 << (idx % 8)))
1540 return true;
1541 } else {
1542 unsigned mask;
1543 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1544 if (mask & 1)
1545 if ((*regmask)[idx / 8] & (1 << (idx % 8)))
1546 return true;
1547 }
1548 return false;
1549 }
1550
1551 /* ************************************************************************* */
1552
1553 #endif /* IR3_H_ */