2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "compiler/shader_enums.h"
32 #include "util/bitscan.h"
33 #include "util/list.h"
35 #include "util/u_debug.h"
37 #include "instr-a3xx.h"
39 /* low level intermediate representation of an adreno shader program */
43 struct ir3_instruction
;
49 uint16_t instrs_count
; /* expanded to account for rpt's */
50 /* NOTE: max_reg, etc, does not include registers not touched
51 * by the shader (ie. vertex fetched via VFD_DECODE but not
54 int8_t max_reg
; /* highest GPR # used by shader */
58 /* number of sync bits: */
64 IR3_REG_CONST
= 0x001,
65 IR3_REG_IMMED
= 0x002,
67 /* high registers are used for some things in compute shaders,
68 * for example. Seems to be for things that are global to all
69 * threads in a wave, so possibly these are global/shared by
70 * all the threads in the wave?
73 IR3_REG_RELATIV
= 0x010,
75 /* Most instructions, it seems, can do float abs/neg but not
76 * integer. The CP pass needs to know what is intended (int or
77 * float) in order to do the right thing. For this reason the
78 * abs/neg flags are split out into float and int variants. In
79 * addition, .b (bitwise) operations, the negate is actually a
80 * bitwise not, so split that out into a new flag to make it
89 IR3_REG_POS_INF
= 0x1000,
90 /* (ei) flag, end-input? Set on last bary, presumably to signal
91 * that the shader needs no more input:
94 /* meta-flags, for intermediate stages of IR, ie.
95 * before register assignment is done:
97 IR3_REG_SSA
= 0x4000, /* 'instr' is ptr to assigning instr */
98 IR3_REG_ARRAY
= 0x8000,
102 bool merged
: 1; /* half-regs conflict with full regs (ie >= a6xx) */
105 * the component is in the low two bits of the reg #, so
106 * rN.x becomes: (N << 2) | x
121 /* For IR3_REG_SSA, src registers contain ptr back to assigning
124 * For IR3_REG_ARRAY, the pointer is back to the last dependent
125 * array access (although the net effect is the same, it points
126 * back to a previous instruction that we depend on).
128 struct ir3_instruction
*instr
;
131 /* used for cat5 instructions, but also for internal/IR level
132 * tracking of what registers are read/written by an instruction.
133 * wrmask may be a bad name since it is used to represent both
134 * src and dst that touch multiple adjacent registers.
137 /* for relative addressing, 32bits for array size is too small,
138 * but otoh we don't need to deal with disjoint sets, so instead
139 * use a simple size field (number of scalar components).
146 * Stupid/simple growable array implementation:
148 #define DECLARE_ARRAY(type, name) \
149 unsigned name ## _count, name ## _sz; \
152 #define array_insert(ctx, arr, val) do { \
153 if (arr ## _count == arr ## _sz) { \
154 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
155 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
157 arr[arr ##_count++] = val; \
160 struct ir3_instruction
{
161 struct ir3_block
*block
;
164 /* (sy) flag is set on first instruction, and after sample
165 * instructions (probably just on RAW hazard).
167 IR3_INSTR_SY
= 0x001,
168 /* (ss) flag is set on first instruction, and first instruction
169 * to depend on the result of "long" instructions (RAW hazard):
171 * rcp, rsq, log2, exp2, sin, cos, sqrt
173 * It seems to synchronize until all in-flight instructions are
174 * completed, for example:
177 * add.f hr2.z, (neg)hr2.z, hc0.y
178 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
181 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
183 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
184 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
185 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
187 * The last mul.f does not have (ss) set, presumably because the
188 * (ss) on the previous instruction does the job.
190 * The blob driver also seems to set it on WAR hazards, although
191 * not really clear if this is needed or just blob compiler being
192 * sloppy. So far I haven't found a case where removing the (ss)
193 * causes problems for WAR hazard, but I could just be getting
197 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
200 IR3_INSTR_SS
= 0x002,
201 /* (jp) flag is set on jump targets:
203 IR3_INSTR_JP
= 0x004,
204 IR3_INSTR_UL
= 0x008,
205 IR3_INSTR_3D
= 0x010,
210 IR3_INSTR_S2EN
= 0x200,
212 IR3_INSTR_SAT
= 0x800,
213 /* meta-flags, for intermediate stages of IR, ie.
214 * before register assignment is done:
216 IR3_INSTR_MARK
= 0x1000,
217 IR3_INSTR_UNUSED
= 0x2000,
225 struct ir3_register
**regs
;
231 struct ir3_block
*target
;
234 type_t src_type
, dst_type
;
254 int iim_val
: 3; /* for ldgb/stgb, # of components */
259 unsigned w
: 1; /* write */
260 unsigned r
: 1; /* read */
261 unsigned l
: 1; /* local */
262 unsigned g
: 1; /* global */
264 /* for meta-instructions, just used to hold extra data
265 * before instruction scheduling, etc
268 int off
; /* component/offset */
272 unsigned input_offset
;
275 /* for sysvals, identifies the sysval type. Mostly so we can
276 * identify the special cases where a sysval should not be DCE'd
277 * (currently, just pre-fs texture fetch)
279 gl_system_value sysval
;
283 /* transient values used during various algorithms: */
285 /* The instruction depth is the max dependency distance to output.
287 * You can also think of it as the "cost", if we did any sort of
288 * optimization for register footprint. Ie. a value that is just
289 * result of moving a const to a reg would have a low cost, so to
290 * it could make sense to duplicate the instruction at various
291 * points where the result is needed to reduce register footprint.
294 /* When we get to the RA stage, we no longer need depth, but
295 * we do need instruction's position/name:
303 /* used for per-pass extra instruction data.
305 * TODO we should remove the per-pass data like this and 'use_count'
306 * and do something similar to what RA does w/ ir3_ra_instr_data..
307 * ie. use the ir3_count_instructions pass, and then use instr->ip
308 * to index into a table of pass-private data.
312 int sun
; /* Sethi–Ullman number, used by sched */
313 int use_count
; /* currently just updated/used by cp */
315 /* Used during CP and RA stages. For fanin and shader inputs/
316 * outputs where we need a sequence of consecutive registers,
317 * keep track of each src instructions left (ie 'n-1') and right
318 * (ie 'n+1') neighbor. The front-end must insert enough mov's
319 * to ensure that each instruction has at most one left and at
320 * most one right neighbor. During the copy-propagation pass,
321 * we only remove mov's when we can preserve this constraint.
322 * And during the RA stage, we use the neighbor information to
323 * allocate a block of registers in one shot.
325 * TODO: maybe just add something like:
326 * struct ir3_instruction_ref {
327 * struct ir3_instruction *instr;
331 * Or can we get away without the refcnt stuff? It seems like
332 * it should be overkill.. the problem is if, potentially after
333 * already eliminating some mov's, if you have a single mov that
334 * needs to be grouped with it's neighbors in two different
335 * places (ex. shader output and a fanin).
338 struct ir3_instruction
*left
, *right
;
339 uint16_t left_cnt
, right_cnt
;
342 /* an instruction can reference at most one address register amongst
343 * it's src/dst registers. Beyond that, you need to insert mov's.
345 * NOTE: do not write this directly, use ir3_instr_set_address()
347 struct ir3_instruction
*address
;
349 /* Tracking for additional dependent instructions. Used to handle
350 * barriers, WAR hazards for arrays/SSBOs/etc.
352 DECLARE_ARRAY(struct ir3_instruction
*, deps
);
355 * From PoV of instruction scheduling, not execution (ie. ignores global/
356 * local distinction):
357 * shared image atomic SSBO everything
358 * barrier()/ - R/W R/W R/W R/W X
359 * groupMemoryBarrier()
360 * memoryBarrier() - R/W R/W
361 * (but only images declared coherent?)
362 * memoryBarrierAtomic() - R/W
363 * memoryBarrierBuffer() - R/W
364 * memoryBarrierImage() - R/W
365 * memoryBarrierShared() - R/W
367 * TODO I think for SSBO/image/shared, in cases where we can determine
368 * which variable is accessed, we don't need to care about accesses to
369 * different variables (unless declared coherent??)
372 IR3_BARRIER_EVERYTHING
= 1 << 0,
373 IR3_BARRIER_SHARED_R
= 1 << 1,
374 IR3_BARRIER_SHARED_W
= 1 << 2,
375 IR3_BARRIER_IMAGE_R
= 1 << 3,
376 IR3_BARRIER_IMAGE_W
= 1 << 4,
377 IR3_BARRIER_BUFFER_R
= 1 << 5,
378 IR3_BARRIER_BUFFER_W
= 1 << 6,
379 IR3_BARRIER_ARRAY_R
= 1 << 7,
380 IR3_BARRIER_ARRAY_W
= 1 << 8,
381 } barrier_class
, barrier_conflict
;
383 /* Entry in ir3_block's instruction list: */
384 struct list_head node
;
391 static inline struct ir3_instruction
*
392 ir3_neighbor_first(struct ir3_instruction
*instr
)
395 while (instr
->cp
.left
) {
396 instr
= instr
->cp
.left
;
397 if (++cnt
> 0xffff) {
405 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
409 debug_assert(!instr
->cp
.left
);
411 while (instr
->cp
.right
) {
413 instr
= instr
->cp
.right
;
424 struct ir3_compiler
*compiler
;
425 gl_shader_stage type
;
427 unsigned ninputs
, noutputs
;
428 struct ir3_instruction
**inputs
;
429 struct ir3_instruction
**outputs
;
431 /* Track bary.f (and ldlv) instructions.. this is needed in
432 * scheduling to ensure that all varying fetches happen before
433 * any potential kill instructions. The hw gets grumpy if all
434 * threads in a group are killed before the last bary.f gets
435 * a chance to signal end of input (ei).
437 DECLARE_ARRAY(struct ir3_instruction
*, baryfs
);
439 /* Track all indirect instructions (read and write). To avoid
440 * deadlock scenario where an address register gets scheduled,
441 * but other dependent src instructions cannot be scheduled due
442 * to dependency on a *different* address register value, the
443 * scheduler needs to ensure that all dependencies other than
444 * the instruction other than the address register are scheduled
445 * before the one that writes the address register. Having a
446 * convenient list of instructions that reference some address
447 * register simplifies this.
449 DECLARE_ARRAY(struct ir3_instruction
*, indirects
);
451 /* and same for instructions that consume predicate register: */
452 DECLARE_ARRAY(struct ir3_instruction
*, predicates
);
454 /* Track texture sample instructions which need texture state
455 * patched in (for astc-srgb workaround):
457 DECLARE_ARRAY(struct ir3_instruction
*, astc_srgb
);
459 /* List of blocks: */
460 struct list_head block_list
;
462 /* List of ir3_array's: */
463 struct list_head array_list
;
465 unsigned max_sun
; /* max Sethi–Ullman number */
468 unsigned block_count
, instr_count
;
473 struct list_head node
;
477 struct nir_register
*r
;
479 /* To avoid array write's from getting DCE'd, keep track of the
480 * most recent write. Any array access depends on the most
481 * recent write. This way, nothing depends on writes after the
482 * last read. But all the writes that happen before that have
483 * something depending on them
485 struct ir3_instruction
*last_write
;
487 /* extra stuff used in RA pass: */
488 unsigned base
; /* base vreg name */
489 unsigned reg
; /* base physical reg */
490 uint16_t start_ip
, end_ip
;
493 struct ir3_array
* ir3_lookup_array(struct ir3
*ir
, unsigned id
);
496 struct list_head node
;
499 const struct nir_block
*nblock
;
501 struct list_head instr_list
; /* list of ir3_instruction */
503 /* each block has either one or two successors.. in case of
504 * two successors, 'condition' decides which one to follow.
505 * A block preceding an if/else has two successors.
507 struct ir3_instruction
*condition
;
508 struct ir3_block
*successors
[2];
510 struct set
*predecessors
; /* set of ir3_block */
512 uint16_t start_ip
, end_ip
;
514 /* Track instructions which do not write a register but other-
515 * wise must not be discarded (such as kill, stg, etc)
517 DECLARE_ARRAY(struct ir3_instruction
*, keeps
);
519 /* used for per-pass extra block data. Mainly used right
520 * now in RA step to track livein/liveout.
529 static inline uint32_t
530 block_id(struct ir3_block
*block
)
533 return block
->serialno
;
535 return (uint32_t)(unsigned long)block
;
539 struct ir3
* ir3_create(struct ir3_compiler
*compiler
,
540 gl_shader_stage type
, unsigned nin
, unsigned nout
);
541 void ir3_destroy(struct ir3
*shader
);
542 void * ir3_assemble(struct ir3
*shader
,
543 struct ir3_info
*info
, uint32_t gpu_id
);
544 void * ir3_alloc(struct ir3
*shader
, int sz
);
546 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
548 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
);
549 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
550 opc_t opc
, int nreg
);
551 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
552 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
);
553 const char *ir3_instr_name(struct ir3_instruction
*instr
);
555 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
557 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
558 struct ir3_register
*reg
);
560 void ir3_instr_set_address(struct ir3_instruction
*instr
,
561 struct ir3_instruction
*addr
);
563 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
565 if (instr
->flags
& IR3_INSTR_MARK
)
566 return true; /* already visited */
567 instr
->flags
|= IR3_INSTR_MARK
;
571 void ir3_block_clear_mark(struct ir3_block
*block
);
572 void ir3_clear_mark(struct ir3
*shader
);
574 unsigned ir3_count_instructions(struct ir3
*ir
);
576 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
577 struct ir3_register
*reg
)
580 for (i
= 0; i
< instr
->regs_count
; i
++)
581 if (reg
== instr
->regs
[i
])
587 #define MAX_ARRAYS 16
595 static inline uint32_t regid(int num
, int comp
)
597 return (num
<< 2) | (comp
& 0x3);
600 static inline uint32_t reg_num(struct ir3_register
*reg
)
602 return reg
->num
>> 2;
605 static inline uint32_t reg_comp(struct ir3_register
*reg
)
607 return reg
->num
& 0x3;
610 static inline bool is_flow(struct ir3_instruction
*instr
)
612 return (opc_cat(instr
->opc
) == 0);
615 static inline bool is_kill(struct ir3_instruction
*instr
)
617 return instr
->opc
== OPC_KILL
;
620 static inline bool is_nop(struct ir3_instruction
*instr
)
622 return instr
->opc
== OPC_NOP
;
625 static inline bool is_same_type_reg(struct ir3_register
*reg1
,
626 struct ir3_register
*reg2
)
628 unsigned type_reg1
= (reg1
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
629 unsigned type_reg2
= (reg2
->flags
& (IR3_REG_HIGH
| IR3_REG_HALF
));
631 if (type_reg1
^ type_reg2
)
637 /* Is it a non-transformative (ie. not type changing) mov? This can
638 * also include absneg.s/absneg.f, which for the most part can be
639 * treated as a mov (single src argument).
641 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
643 struct ir3_register
*dst
;
645 switch (instr
->opc
) {
647 if (instr
->cat1
.src_type
!= instr
->cat1
.dst_type
)
652 if (instr
->flags
& IR3_INSTR_SAT
)
654 /* If the type of dest reg and src reg are different,
655 * it shouldn't be considered as same type mov */
656 if (!is_same_type_reg(instr
->regs
[0], instr
->regs
[1]))
663 dst
= instr
->regs
[0];
665 /* mov's that write to a0.x or p0.x are special: */
666 if (dst
->num
== regid(REG_P0
, 0))
668 if (dst
->num
== regid(REG_A0
, 0))
671 if (dst
->flags
& (IR3_REG_RELATIV
| IR3_REG_ARRAY
))
677 static inline bool is_alu(struct ir3_instruction
*instr
)
679 return (1 <= opc_cat(instr
->opc
)) && (opc_cat(instr
->opc
) <= 3);
682 static inline bool is_sfu(struct ir3_instruction
*instr
)
684 return (opc_cat(instr
->opc
) == 4);
687 static inline bool is_tex(struct ir3_instruction
*instr
)
689 return (opc_cat(instr
->opc
) == 5);
692 static inline bool is_mem(struct ir3_instruction
*instr
)
694 return (opc_cat(instr
->opc
) == 6);
697 static inline bool is_barrier(struct ir3_instruction
*instr
)
699 return (opc_cat(instr
->opc
) == 7);
703 is_store(struct ir3_instruction
*instr
)
705 /* these instructions, the "destination" register is
706 * actually a source, the address to store to.
708 switch (instr
->opc
) {
723 static inline bool is_load(struct ir3_instruction
*instr
)
725 switch (instr
->opc
) {
735 /* probably some others too.. */
742 static inline bool is_input(struct ir3_instruction
*instr
)
744 /* in some cases, ldlv is used to fetch varying without
745 * interpolation.. fortunately inloc is the first src
746 * register in either case
748 switch (instr
->opc
) {
757 static inline bool is_bool(struct ir3_instruction
*instr
)
759 switch (instr
->opc
) {
769 static inline bool is_meta(struct ir3_instruction
*instr
)
771 /* TODO how should we count PHI (and maybe fan-in/out) which
772 * might actually contribute some instructions to the final
775 return (opc_cat(instr
->opc
) == -1);
778 static inline unsigned dest_regs(struct ir3_instruction
*instr
)
780 if ((instr
->regs_count
== 0) || is_store(instr
))
783 return util_last_bit(instr
->regs
[0]->wrmask
);
786 static inline bool writes_addr(struct ir3_instruction
*instr
)
788 if (instr
->regs_count
> 0) {
789 struct ir3_register
*dst
= instr
->regs
[0];
790 return reg_num(dst
) == REG_A0
;
795 static inline bool writes_pred(struct ir3_instruction
*instr
)
797 if (instr
->regs_count
> 0) {
798 struct ir3_register
*dst
= instr
->regs
[0];
799 return reg_num(dst
) == REG_P0
;
804 /* returns defining instruction for reg */
805 /* TODO better name */
806 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
808 if (reg
->flags
& (IR3_REG_SSA
| IR3_REG_ARRAY
)) {
814 static inline bool conflicts(struct ir3_instruction
*a
,
815 struct ir3_instruction
*b
)
817 return (a
&& b
) && (a
!= b
);
820 static inline bool reg_gpr(struct ir3_register
*r
)
822 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
824 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
829 static inline type_t
half_type(type_t type
)
832 case TYPE_F32
: return TYPE_F16
;
833 case TYPE_U32
: return TYPE_U16
;
834 case TYPE_S32
: return TYPE_S16
;
845 /* some cat2 instructions (ie. those which are not float) can embed an
848 static inline bool ir3_cat2_int(opc_t opc
)
888 static inline bool ir3_cat2_float(opc_t opc
)
911 static inline bool ir3_cat3_float(opc_t opc
)
924 /* map cat2 instruction to valid abs/neg flags: */
925 static inline unsigned ir3_cat2_absneg(opc_t opc
)
942 return IR3_REG_FABS
| IR3_REG_FNEG
;
963 return IR3_REG_SABS
| IR3_REG_SNEG
;
984 /* map cat3 instructions to valid abs/neg flags: */
985 static inline unsigned ir3_cat3_absneg(opc_t opc
)
1004 /* neg *may* work on 3rd src.. */
1014 #define MASK(n) ((1 << (n)) - 1)
1016 /* iterator for an instructions's sources (reg), also returns src #: */
1017 #define foreach_src_n(__srcreg, __n, __instr) \
1018 if ((__instr)->regs_count) \
1019 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
1020 if ((__srcreg = (__instr)->regs[__n + 1]))
1022 /* iterator for an instructions's sources (reg): */
1023 #define foreach_src(__srcreg, __instr) \
1024 foreach_src_n(__srcreg, __i, __instr)
1026 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
1028 unsigned cnt
= instr
->regs_count
+ instr
->deps_count
;
1034 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
1036 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1037 return instr
->address
;
1038 if (n
>= instr
->regs_count
)
1039 return instr
->deps
[n
- instr
->regs_count
];
1040 return ssa(instr
->regs
[n
]);
1043 static inline bool __is_false_dep(struct ir3_instruction
*instr
, unsigned n
)
1045 if (n
== (instr
->regs_count
+ instr
->deps_count
))
1047 if (n
>= instr
->regs_count
)
1052 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
1054 /* iterator for an instruction's SSA sources (instr), also returns src #: */
1055 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
1056 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
1057 if ((__srcinst = __ssa_src_n(__instr, __n)))
1059 /* iterator for an instruction's SSA sources (instr): */
1060 #define foreach_ssa_src(__srcinst, __instr) \
1061 foreach_ssa_src_n(__srcinst, __i, __instr)
1065 void ir3_print(struct ir3
*ir
);
1066 void ir3_print_instr(struct ir3_instruction
*instr
);
1068 /* depth calculation: */
1069 struct ir3_shader_variant
;
1070 int ir3_delayslots(struct ir3_instruction
*assigner
,
1071 struct ir3_instruction
*consumer
, unsigned n
);
1072 void ir3_insert_by_depth(struct ir3_instruction
*instr
, struct list_head
*list
);
1073 void ir3_depth(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1075 /* copy-propagate: */
1076 void ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1078 /* group neighbors and insert mov's to resolve conflicts: */
1079 void ir3_group(struct ir3
*ir
);
1081 /* Sethi–Ullman numbering: */
1082 void ir3_sun(struct ir3
*ir
);
1085 void ir3_sched_add_deps(struct ir3
*ir
);
1086 int ir3_sched(struct ir3
*ir
);
1088 void ir3_a6xx_fixup_atomic_dests(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1090 /* register assignment: */
1091 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(struct ir3_compiler
*compiler
);
1092 int ir3_ra(struct ir3_shader_variant
*v
, struct ir3_instruction
**precolor
, unsigned nprecolor
);
1095 void ir3_legalize(struct ir3
*ir
, bool *has_ssbo
, bool *need_pixlod
, int *max_bary
);
1097 /* ************************************************************************* */
1098 /* instruction helpers */
1100 static inline struct ir3_instruction
*
1101 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
1103 struct ir3_instruction
*mov
;
1104 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1106 mov
= ir3_instr_create(block
, OPC_MOV
);
1107 mov
->cat1
.src_type
= type
;
1108 mov
->cat1
.dst_type
= type
;
1109 ir3_reg_create(mov
, 0, flags
);
1110 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
1115 static inline struct ir3_instruction
*
1116 create_immed(struct ir3_block
*block
, uint32_t val
)
1118 return create_immed_typed(block
, val
, TYPE_U32
);
1121 static inline struct ir3_instruction
*
1122 create_uniform_typed(struct ir3_block
*block
, unsigned n
, type_t type
)
1124 struct ir3_instruction
*mov
;
1125 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1127 mov
= ir3_instr_create(block
, OPC_MOV
);
1128 mov
->cat1
.src_type
= type
;
1129 mov
->cat1
.dst_type
= type
;
1130 ir3_reg_create(mov
, 0, flags
);
1131 ir3_reg_create(mov
, n
, IR3_REG_CONST
| flags
);
1136 static inline struct ir3_instruction
*
1137 create_uniform(struct ir3_block
*block
, unsigned n
)
1139 return create_uniform_typed(block
, n
, TYPE_F32
);
1142 static inline struct ir3_instruction
*
1143 create_uniform_indirect(struct ir3_block
*block
, int n
,
1144 struct ir3_instruction
*address
)
1146 struct ir3_instruction
*mov
;
1148 mov
= ir3_instr_create(block
, OPC_MOV
);
1149 mov
->cat1
.src_type
= TYPE_U32
;
1150 mov
->cat1
.dst_type
= TYPE_U32
;
1151 ir3_reg_create(mov
, 0, 0);
1152 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
1154 ir3_instr_set_address(mov
, address
);
1159 /* creates SSA src of correct type (ie. half vs full precision) */
1160 static inline struct ir3_register
* __ssa_src(struct ir3_instruction
*instr
,
1161 struct ir3_instruction
*src
, unsigned flags
)
1163 struct ir3_register
*reg
;
1164 if (src
->regs
[0]->flags
& IR3_REG_HALF
)
1165 flags
|= IR3_REG_HALF
;
1166 reg
= ir3_reg_create(instr
, 0, IR3_REG_SSA
| flags
);
1168 reg
->wrmask
= src
->regs
[0]->wrmask
;
1172 static inline struct ir3_instruction
*
1173 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
1175 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1176 ir3_reg_create(instr
, 0, 0); /* dst */
1177 if (src
->regs
[0]->flags
& IR3_REG_ARRAY
) {
1178 struct ir3_register
*src_reg
= __ssa_src(instr
, src
, IR3_REG_ARRAY
);
1179 src_reg
->array
= src
->regs
[0]->array
;
1181 __ssa_src(instr
, src
, src
->regs
[0]->flags
& IR3_REG_HIGH
);
1183 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_RELATIV
));
1184 instr
->cat1
.src_type
= type
;
1185 instr
->cat1
.dst_type
= type
;
1189 static inline struct ir3_instruction
*
1190 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
1191 type_t src_type
, type_t dst_type
)
1193 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1194 unsigned dst_flags
= (type_size(dst_type
) < 32) ? IR3_REG_HALF
: 0;
1195 unsigned src_flags
= (type_size(src_type
) < 32) ? IR3_REG_HALF
: 0;
1197 debug_assert((src
->regs
[0]->flags
& IR3_REG_HALF
) == src_flags
);
1199 ir3_reg_create(instr
, 0, dst_flags
); /* dst */
1200 __ssa_src(instr
, src
, 0);
1201 instr
->cat1
.src_type
= src_type
;
1202 instr
->cat1
.dst_type
= dst_type
;
1203 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_ARRAY
));
1207 static inline struct ir3_instruction
*
1208 ir3_NOP(struct ir3_block
*block
)
1210 return ir3_instr_create(block
, OPC_NOP
);
1213 #define IR3_INSTR_0 0
1215 #define __INSTR0(flag, name, opc) \
1216 static inline struct ir3_instruction * \
1217 ir3_##name(struct ir3_block *block) \
1219 struct ir3_instruction *instr = \
1220 ir3_instr_create(block, opc); \
1221 instr->flags |= flag; \
1224 #define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name)
1225 #define INSTR0(name) __INSTR0(0, name, OPC_##name)
1227 #define __INSTR1(flag, name, opc) \
1228 static inline struct ir3_instruction * \
1229 ir3_##name(struct ir3_block *block, \
1230 struct ir3_instruction *a, unsigned aflags) \
1232 struct ir3_instruction *instr = \
1233 ir3_instr_create(block, opc); \
1234 ir3_reg_create(instr, 0, 0); /* dst */ \
1235 __ssa_src(instr, a, aflags); \
1236 instr->flags |= flag; \
1239 #define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name)
1240 #define INSTR1(name) __INSTR1(0, name, OPC_##name)
1242 #define __INSTR2(flag, name, opc) \
1243 static inline struct ir3_instruction * \
1244 ir3_##name(struct ir3_block *block, \
1245 struct ir3_instruction *a, unsigned aflags, \
1246 struct ir3_instruction *b, unsigned bflags) \
1248 struct ir3_instruction *instr = \
1249 ir3_instr_create(block, opc); \
1250 ir3_reg_create(instr, 0, 0); /* dst */ \
1251 __ssa_src(instr, a, aflags); \
1252 __ssa_src(instr, b, bflags); \
1253 instr->flags |= flag; \
1256 #define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name)
1257 #define INSTR2(name) __INSTR2(0, name, OPC_##name)
1259 #define __INSTR3(flag, name, opc) \
1260 static inline struct ir3_instruction * \
1261 ir3_##name(struct ir3_block *block, \
1262 struct ir3_instruction *a, unsigned aflags, \
1263 struct ir3_instruction *b, unsigned bflags, \
1264 struct ir3_instruction *c, unsigned cflags) \
1266 struct ir3_instruction *instr = \
1267 ir3_instr_create2(block, opc, 4); \
1268 ir3_reg_create(instr, 0, 0); /* dst */ \
1269 __ssa_src(instr, a, aflags); \
1270 __ssa_src(instr, b, bflags); \
1271 __ssa_src(instr, c, cflags); \
1272 instr->flags |= flag; \
1275 #define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name)
1276 #define INSTR3(name) __INSTR3(0, name, OPC_##name)
1278 #define __INSTR4(flag, name, opc) \
1279 static inline struct ir3_instruction * \
1280 ir3_##name(struct ir3_block *block, \
1281 struct ir3_instruction *a, unsigned aflags, \
1282 struct ir3_instruction *b, unsigned bflags, \
1283 struct ir3_instruction *c, unsigned cflags, \
1284 struct ir3_instruction *d, unsigned dflags) \
1286 struct ir3_instruction *instr = \
1287 ir3_instr_create2(block, opc, 5); \
1288 ir3_reg_create(instr, 0, 0); /* dst */ \
1289 __ssa_src(instr, a, aflags); \
1290 __ssa_src(instr, b, bflags); \
1291 __ssa_src(instr, c, cflags); \
1292 __ssa_src(instr, d, dflags); \
1293 instr->flags |= flag; \
1296 #define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name)
1297 #define INSTR4(name) __INSTR4(0, name, OPC_##name)
1299 /* cat0 instructions: */
1307 /* cat2 instructions, most 2 src but some 1 src: */
1355 /* cat3 instructions: */
1373 /* cat4 instructions: */
1382 /* cat5 instructions: */
1389 static inline struct ir3_instruction
*
1390 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1391 unsigned wrmask
, unsigned flags
, struct ir3_instruction
*samp_tex
,
1392 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1394 struct ir3_instruction
*sam
;
1395 struct ir3_register
*reg
;
1397 sam
= ir3_instr_create(block
, opc
);
1398 sam
->flags
|= flags
| IR3_INSTR_S2EN
;
1399 ir3_reg_create(sam
, 0, 0)->wrmask
= wrmask
;
1400 __ssa_src(sam
, samp_tex
, IR3_REG_HALF
);
1402 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
1403 reg
->wrmask
= (1 << (src0
->regs_count
- 1)) - 1;
1407 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
1409 reg
->wrmask
= (1 << (src1
->regs_count
- 1)) - 1;
1411 sam
->cat5
.type
= type
;
1416 /* cat6 instructions: */
1431 INSTR2(ATOMIC_CMPXCHG
)
1440 INSTR3F(G
, ATOMIC_ADD
)
1441 INSTR3F(G
, ATOMIC_SUB
)
1442 INSTR3F(G
, ATOMIC_XCHG
)
1443 INSTR3F(G
, ATOMIC_INC
)
1444 INSTR3F(G
, ATOMIC_DEC
)
1445 INSTR3F(G
, ATOMIC_CMPXCHG
)
1446 INSTR3F(G
, ATOMIC_MIN
)
1447 INSTR3F(G
, ATOMIC_MAX
)
1448 INSTR3F(G
, ATOMIC_AND
)
1449 INSTR3F(G
, ATOMIC_OR
)
1450 INSTR3F(G
, ATOMIC_XOR
)
1455 INSTR4F(G
, ATOMIC_ADD
)
1456 INSTR4F(G
, ATOMIC_SUB
)
1457 INSTR4F(G
, ATOMIC_XCHG
)
1458 INSTR4F(G
, ATOMIC_INC
)
1459 INSTR4F(G
, ATOMIC_DEC
)
1460 INSTR4F(G
, ATOMIC_CMPXCHG
)
1461 INSTR4F(G
, ATOMIC_MIN
)
1462 INSTR4F(G
, ATOMIC_MAX
)
1463 INSTR4F(G
, ATOMIC_AND
)
1464 INSTR4F(G
, ATOMIC_OR
)
1465 INSTR4F(G
, ATOMIC_XOR
)
1468 /* cat7 instructions: */
1472 /* meta instructions: */
1473 INSTR0(META_TEX_PREFETCH
);
1475 /* ************************************************************************* */
1476 /* split this out or find some helper to use.. like main/bitset.h.. */
1482 typedef uint8_t regmask_t
[2 * MAX_REG
/ 8];
1484 static inline unsigned regmask_idx(struct ir3_register
*reg
)
1486 unsigned num
= (reg
->flags
& IR3_REG_RELATIV
) ? reg
->array
.offset
: reg
->num
;
1487 debug_assert(num
< MAX_REG
);
1488 if (reg
->flags
& IR3_REG_HALF
) {
1498 static inline void regmask_init(regmask_t
*regmask
)
1500 memset(regmask
, 0, sizeof(*regmask
));
1503 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1505 unsigned idx
= regmask_idx(reg
);
1506 if (reg
->flags
& IR3_REG_RELATIV
) {
1508 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1509 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1512 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1514 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1518 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1521 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1522 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1525 /* set bits in a if not set in b, conceptually:
1528 static inline void regmask_set_if_not(regmask_t
*a
,
1529 struct ir3_register
*reg
, regmask_t
*b
)
1531 unsigned idx
= regmask_idx(reg
);
1532 if (reg
->flags
& IR3_REG_RELATIV
) {
1534 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1535 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1536 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1539 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1541 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1542 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1546 static inline bool regmask_get(regmask_t
*regmask
,
1547 struct ir3_register
*reg
)
1549 unsigned idx
= regmask_idx(reg
);
1550 if (reg
->flags
& IR3_REG_RELATIV
) {
1552 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1553 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1557 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1559 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1565 /* ************************************************************************* */