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freedreno: move ir3 to common location
[mesa.git] / src / freedreno / ir3 / ir3.h
1 /*
2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #ifndef IR3_H_
25 #define IR3_H_
26
27 #include <stdint.h>
28 #include <stdbool.h>
29
30 #include "compiler/shader_enums.h"
31
32 #include "util/u_debug.h"
33 #include "util/list.h"
34
35 #include "instr-a3xx.h"
36
37 /* low level intermediate representation of an adreno shader program */
38
39 struct ir3_compiler;
40 struct ir3;
41 struct ir3_instruction;
42 struct ir3_block;
43
44 struct ir3_info {
45 uint32_t gpu_id;
46 uint16_t sizedwords;
47 uint16_t instrs_count; /* expanded to account for rpt's */
48 /* NOTE: max_reg, etc, does not include registers not touched
49 * by the shader (ie. vertex fetched via VFD_DECODE but not
50 * touched by shader)
51 */
52 int8_t max_reg; /* highest GPR # used by shader */
53 int8_t max_half_reg;
54 int16_t max_const;
55
56 /* number of sync bits: */
57 uint16_t ss, sy;
58 };
59
60 struct ir3_register {
61 enum {
62 IR3_REG_CONST = 0x001,
63 IR3_REG_IMMED = 0x002,
64 IR3_REG_HALF = 0x004,
65 /* high registers are used for some things in compute shaders,
66 * for example. Seems to be for things that are global to all
67 * threads in a wave, so possibly these are global/shared by
68 * all the threads in the wave?
69 */
70 IR3_REG_HIGH = 0x008,
71 IR3_REG_RELATIV= 0x010,
72 IR3_REG_R = 0x020,
73 /* Most instructions, it seems, can do float abs/neg but not
74 * integer. The CP pass needs to know what is intended (int or
75 * float) in order to do the right thing. For this reason the
76 * abs/neg flags are split out into float and int variants. In
77 * addition, .b (bitwise) operations, the negate is actually a
78 * bitwise not, so split that out into a new flag to make it
79 * more clear.
80 */
81 IR3_REG_FNEG = 0x040,
82 IR3_REG_FABS = 0x080,
83 IR3_REG_SNEG = 0x100,
84 IR3_REG_SABS = 0x200,
85 IR3_REG_BNOT = 0x400,
86 IR3_REG_EVEN = 0x800,
87 IR3_REG_POS_INF= 0x1000,
88 /* (ei) flag, end-input? Set on last bary, presumably to signal
89 * that the shader needs no more input:
90 */
91 IR3_REG_EI = 0x2000,
92 /* meta-flags, for intermediate stages of IR, ie.
93 * before register assignment is done:
94 */
95 IR3_REG_SSA = 0x4000, /* 'instr' is ptr to assigning instr */
96 IR3_REG_ARRAY = 0x8000,
97
98 } flags;
99
100 /* normal registers:
101 * the component is in the low two bits of the reg #, so
102 * rN.x becomes: (N << 2) | x
103 */
104 int num;
105 union {
106 /* immediate: */
107 int32_t iim_val;
108 uint32_t uim_val;
109 float fim_val;
110 /* relative: */
111 struct {
112 uint16_t id;
113 int16_t offset;
114 } array;
115 };
116
117 /* For IR3_REG_SSA, src registers contain ptr back to assigning
118 * instruction.
119 *
120 * For IR3_REG_ARRAY, the pointer is back to the last dependent
121 * array access (although the net effect is the same, it points
122 * back to a previous instruction that we depend on).
123 */
124 struct ir3_instruction *instr;
125
126 union {
127 /* used for cat5 instructions, but also for internal/IR level
128 * tracking of what registers are read/written by an instruction.
129 * wrmask may be a bad name since it is used to represent both
130 * src and dst that touch multiple adjacent registers.
131 */
132 unsigned wrmask;
133 /* for relative addressing, 32bits for array size is too small,
134 * but otoh we don't need to deal with disjoint sets, so instead
135 * use a simple size field (number of scalar components).
136 */
137 unsigned size;
138 };
139 };
140
141 /*
142 * Stupid/simple growable array implementation:
143 */
144 #define DECLARE_ARRAY(type, name) \
145 unsigned name ## _count, name ## _sz; \
146 type * name;
147
148 #define array_insert(ctx, arr, val) do { \
149 if (arr ## _count == arr ## _sz) { \
150 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
151 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
152 } \
153 arr[arr ##_count++] = val; \
154 } while (0)
155
156 struct ir3_instruction {
157 struct ir3_block *block;
158 opc_t opc;
159 enum {
160 /* (sy) flag is set on first instruction, and after sample
161 * instructions (probably just on RAW hazard).
162 */
163 IR3_INSTR_SY = 0x001,
164 /* (ss) flag is set on first instruction, and first instruction
165 * to depend on the result of "long" instructions (RAW hazard):
166 *
167 * rcp, rsq, log2, exp2, sin, cos, sqrt
168 *
169 * It seems to synchronize until all in-flight instructions are
170 * completed, for example:
171 *
172 * rsq hr1.w, hr1.w
173 * add.f hr2.z, (neg)hr2.z, hc0.y
174 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
175 * rsq hr2.x, hr2.x
176 * (rpt1)nop
177 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
178 * nop
179 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
180 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
181 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
182 *
183 * The last mul.f does not have (ss) set, presumably because the
184 * (ss) on the previous instruction does the job.
185 *
186 * The blob driver also seems to set it on WAR hazards, although
187 * not really clear if this is needed or just blob compiler being
188 * sloppy. So far I haven't found a case where removing the (ss)
189 * causes problems for WAR hazard, but I could just be getting
190 * lucky:
191 *
192 * rcp r1.y, r3.y
193 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
194 *
195 */
196 IR3_INSTR_SS = 0x002,
197 /* (jp) flag is set on jump targets:
198 */
199 IR3_INSTR_JP = 0x004,
200 IR3_INSTR_UL = 0x008,
201 IR3_INSTR_3D = 0x010,
202 IR3_INSTR_A = 0x020,
203 IR3_INSTR_O = 0x040,
204 IR3_INSTR_P = 0x080,
205 IR3_INSTR_S = 0x100,
206 IR3_INSTR_S2EN = 0x200,
207 IR3_INSTR_G = 0x400,
208 IR3_INSTR_SAT = 0x800,
209 /* meta-flags, for intermediate stages of IR, ie.
210 * before register assignment is done:
211 */
212 IR3_INSTR_MARK = 0x1000,
213 IR3_INSTR_UNUSED= 0x2000,
214 } flags;
215 int repeat;
216 #ifdef DEBUG
217 unsigned regs_max;
218 #endif
219 unsigned regs_count;
220 struct ir3_register **regs;
221 union {
222 struct {
223 char inv;
224 char comp;
225 int immed;
226 struct ir3_block *target;
227 } cat0;
228 struct {
229 type_t src_type, dst_type;
230 } cat1;
231 struct {
232 enum {
233 IR3_COND_LT = 0,
234 IR3_COND_LE = 1,
235 IR3_COND_GT = 2,
236 IR3_COND_GE = 3,
237 IR3_COND_EQ = 4,
238 IR3_COND_NE = 5,
239 } condition;
240 } cat2;
241 struct {
242 unsigned samp, tex;
243 type_t type;
244 } cat5;
245 struct {
246 type_t type;
247 int src_offset;
248 int dst_offset;
249 int iim_val : 3; /* for ldgb/stgb, # of components */
250 int d : 3;
251 bool typed : 1;
252 } cat6;
253 struct {
254 unsigned w : 1; /* write */
255 unsigned r : 1; /* read */
256 unsigned l : 1; /* local */
257 unsigned g : 1; /* global */
258 } cat7;
259 /* for meta-instructions, just used to hold extra data
260 * before instruction scheduling, etc
261 */
262 struct {
263 int off; /* component/offset */
264 } fo;
265 struct {
266 struct ir3_block *block;
267 } inout;
268 };
269
270 /* transient values used during various algorithms: */
271 union {
272 /* The instruction depth is the max dependency distance to output.
273 *
274 * You can also think of it as the "cost", if we did any sort of
275 * optimization for register footprint. Ie. a value that is just
276 * result of moving a const to a reg would have a low cost, so to
277 * it could make sense to duplicate the instruction at various
278 * points where the result is needed to reduce register footprint.
279 */
280 unsigned depth;
281 /* When we get to the RA stage, we no longer need depth, but
282 * we do need instruction's position/name:
283 */
284 struct {
285 uint16_t ip;
286 uint16_t name;
287 };
288 };
289
290 /* used for per-pass extra instruction data.
291 */
292 void *data;
293
294 /* Used during CP and RA stages. For fanin and shader inputs/
295 * outputs where we need a sequence of consecutive registers,
296 * keep track of each src instructions left (ie 'n-1') and right
297 * (ie 'n+1') neighbor. The front-end must insert enough mov's
298 * to ensure that each instruction has at most one left and at
299 * most one right neighbor. During the copy-propagation pass,
300 * we only remove mov's when we can preserve this constraint.
301 * And during the RA stage, we use the neighbor information to
302 * allocate a block of registers in one shot.
303 *
304 * TODO: maybe just add something like:
305 * struct ir3_instruction_ref {
306 * struct ir3_instruction *instr;
307 * unsigned cnt;
308 * }
309 *
310 * Or can we get away without the refcnt stuff? It seems like
311 * it should be overkill.. the problem is if, potentially after
312 * already eliminating some mov's, if you have a single mov that
313 * needs to be grouped with it's neighbors in two different
314 * places (ex. shader output and a fanin).
315 */
316 struct {
317 struct ir3_instruction *left, *right;
318 uint16_t left_cnt, right_cnt;
319 } cp;
320
321 /* an instruction can reference at most one address register amongst
322 * it's src/dst registers. Beyond that, you need to insert mov's.
323 *
324 * NOTE: do not write this directly, use ir3_instr_set_address()
325 */
326 struct ir3_instruction *address;
327
328 /* Tracking for additional dependent instructions. Used to handle
329 * barriers, WAR hazards for arrays/SSBOs/etc.
330 */
331 DECLARE_ARRAY(struct ir3_instruction *, deps);
332
333 /*
334 * From PoV of instruction scheduling, not execution (ie. ignores global/
335 * local distinction):
336 * shared image atomic SSBO everything
337 * barrier()/ - R/W R/W R/W R/W X
338 * groupMemoryBarrier()
339 * memoryBarrier() - R/W R/W
340 * (but only images declared coherent?)
341 * memoryBarrierAtomic() - R/W
342 * memoryBarrierBuffer() - R/W
343 * memoryBarrierImage() - R/W
344 * memoryBarrierShared() - R/W
345 *
346 * TODO I think for SSBO/image/shared, in cases where we can determine
347 * which variable is accessed, we don't need to care about accesses to
348 * different variables (unless declared coherent??)
349 */
350 enum {
351 IR3_BARRIER_EVERYTHING = 1 << 0,
352 IR3_BARRIER_SHARED_R = 1 << 1,
353 IR3_BARRIER_SHARED_W = 1 << 2,
354 IR3_BARRIER_IMAGE_R = 1 << 3,
355 IR3_BARRIER_IMAGE_W = 1 << 4,
356 IR3_BARRIER_BUFFER_R = 1 << 5,
357 IR3_BARRIER_BUFFER_W = 1 << 6,
358 IR3_BARRIER_ARRAY_R = 1 << 7,
359 IR3_BARRIER_ARRAY_W = 1 << 8,
360 } barrier_class, barrier_conflict;
361
362 /* Entry in ir3_block's instruction list: */
363 struct list_head node;
364
365 int use_count; /* currently just updated/used by cp */
366
367 #ifdef DEBUG
368 uint32_t serialno;
369 #endif
370 };
371
372 static inline struct ir3_instruction *
373 ir3_neighbor_first(struct ir3_instruction *instr)
374 {
375 int cnt = 0;
376 while (instr->cp.left) {
377 instr = instr->cp.left;
378 if (++cnt > 0xffff) {
379 debug_assert(0);
380 break;
381 }
382 }
383 return instr;
384 }
385
386 static inline int ir3_neighbor_count(struct ir3_instruction *instr)
387 {
388 int num = 1;
389
390 debug_assert(!instr->cp.left);
391
392 while (instr->cp.right) {
393 num++;
394 instr = instr->cp.right;
395 if (num > 0xffff) {
396 debug_assert(0);
397 break;
398 }
399 }
400
401 return num;
402 }
403
404 struct ir3 {
405 struct ir3_compiler *compiler;
406
407 unsigned ninputs, noutputs;
408 struct ir3_instruction **inputs;
409 struct ir3_instruction **outputs;
410
411 /* Track bary.f (and ldlv) instructions.. this is needed in
412 * scheduling to ensure that all varying fetches happen before
413 * any potential kill instructions. The hw gets grumpy if all
414 * threads in a group are killed before the last bary.f gets
415 * a chance to signal end of input (ei).
416 */
417 DECLARE_ARRAY(struct ir3_instruction *, baryfs);
418
419 /* Track all indirect instructions (read and write). To avoid
420 * deadlock scenario where an address register gets scheduled,
421 * but other dependent src instructions cannot be scheduled due
422 * to dependency on a *different* address register value, the
423 * scheduler needs to ensure that all dependencies other than
424 * the instruction other than the address register are scheduled
425 * before the one that writes the address register. Having a
426 * convenient list of instructions that reference some address
427 * register simplifies this.
428 */
429 DECLARE_ARRAY(struct ir3_instruction *, indirects);
430
431 /* and same for instructions that consume predicate register: */
432 DECLARE_ARRAY(struct ir3_instruction *, predicates);
433
434 /* Track texture sample instructions which need texture state
435 * patched in (for astc-srgb workaround):
436 */
437 DECLARE_ARRAY(struct ir3_instruction *, astc_srgb);
438
439 /* List of blocks: */
440 struct list_head block_list;
441
442 /* List of ir3_array's: */
443 struct list_head array_list;
444
445 #ifdef DEBUG
446 unsigned block_count, instr_count;
447 #endif
448 };
449
450 struct ir3_array {
451 struct list_head node;
452 unsigned length;
453 unsigned id;
454
455 struct nir_register *r;
456
457 /* To avoid array write's from getting DCE'd, keep track of the
458 * most recent write. Any array access depends on the most
459 * recent write. This way, nothing depends on writes after the
460 * last read. But all the writes that happen before that have
461 * something depending on them
462 */
463 struct ir3_instruction *last_write;
464
465 /* extra stuff used in RA pass: */
466 unsigned base; /* base vreg name */
467 unsigned reg; /* base physical reg */
468 uint16_t start_ip, end_ip;
469 };
470
471 struct ir3_array * ir3_lookup_array(struct ir3 *ir, unsigned id);
472
473 struct ir3_block {
474 struct list_head node;
475 struct ir3 *shader;
476
477 const struct nir_block *nblock;
478
479 struct list_head instr_list; /* list of ir3_instruction */
480
481 /* each block has either one or two successors.. in case of
482 * two successors, 'condition' decides which one to follow.
483 * A block preceding an if/else has two successors.
484 */
485 struct ir3_instruction *condition;
486 struct ir3_block *successors[2];
487
488 unsigned predecessors_count;
489 struct ir3_block **predecessors;
490
491 uint16_t start_ip, end_ip;
492
493 /* Track instructions which do not write a register but other-
494 * wise must not be discarded (such as kill, stg, etc)
495 */
496 DECLARE_ARRAY(struct ir3_instruction *, keeps);
497
498 /* used for per-pass extra block data. Mainly used right
499 * now in RA step to track livein/liveout.
500 */
501 void *data;
502
503 #ifdef DEBUG
504 uint32_t serialno;
505 #endif
506 };
507
508 static inline uint32_t
509 block_id(struct ir3_block *block)
510 {
511 #ifdef DEBUG
512 return block->serialno;
513 #else
514 return (uint32_t)(unsigned long)block;
515 #endif
516 }
517
518 struct ir3 * ir3_create(struct ir3_compiler *compiler,
519 unsigned nin, unsigned nout);
520 void ir3_destroy(struct ir3 *shader);
521 void * ir3_assemble(struct ir3 *shader,
522 struct ir3_info *info, uint32_t gpu_id);
523 void * ir3_alloc(struct ir3 *shader, int sz);
524
525 struct ir3_block * ir3_block_create(struct ir3 *shader);
526
527 struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc);
528 struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
529 opc_t opc, int nreg);
530 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
531 void ir3_instr_add_dep(struct ir3_instruction *instr, struct ir3_instruction *dep);
532 const char *ir3_instr_name(struct ir3_instruction *instr);
533
534 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
535 int num, int flags);
536 struct ir3_register * ir3_reg_clone(struct ir3 *shader,
537 struct ir3_register *reg);
538
539 void ir3_instr_set_address(struct ir3_instruction *instr,
540 struct ir3_instruction *addr);
541
542 static inline bool ir3_instr_check_mark(struct ir3_instruction *instr)
543 {
544 if (instr->flags & IR3_INSTR_MARK)
545 return true; /* already visited */
546 instr->flags |= IR3_INSTR_MARK;
547 return false;
548 }
549
550 void ir3_block_clear_mark(struct ir3_block *block);
551 void ir3_clear_mark(struct ir3 *shader);
552
553 unsigned ir3_count_instructions(struct ir3 *ir);
554
555 static inline int ir3_instr_regno(struct ir3_instruction *instr,
556 struct ir3_register *reg)
557 {
558 unsigned i;
559 for (i = 0; i < instr->regs_count; i++)
560 if (reg == instr->regs[i])
561 return i;
562 return -1;
563 }
564
565
566 #define MAX_ARRAYS 16
567
568 /* comp:
569 * 0 - x
570 * 1 - y
571 * 2 - z
572 * 3 - w
573 */
574 static inline uint32_t regid(int num, int comp)
575 {
576 return (num << 2) | (comp & 0x3);
577 }
578
579 static inline uint32_t reg_num(struct ir3_register *reg)
580 {
581 return reg->num >> 2;
582 }
583
584 static inline uint32_t reg_comp(struct ir3_register *reg)
585 {
586 return reg->num & 0x3;
587 }
588
589 static inline bool is_flow(struct ir3_instruction *instr)
590 {
591 return (opc_cat(instr->opc) == 0);
592 }
593
594 static inline bool is_kill(struct ir3_instruction *instr)
595 {
596 return instr->opc == OPC_KILL;
597 }
598
599 static inline bool is_nop(struct ir3_instruction *instr)
600 {
601 return instr->opc == OPC_NOP;
602 }
603
604 /* Is it a non-transformative (ie. not type changing) mov? This can
605 * also include absneg.s/absneg.f, which for the most part can be
606 * treated as a mov (single src argument).
607 */
608 static inline bool is_same_type_mov(struct ir3_instruction *instr)
609 {
610 struct ir3_register *dst;
611
612 switch (instr->opc) {
613 case OPC_MOV:
614 if (instr->cat1.src_type != instr->cat1.dst_type)
615 return false;
616 break;
617 case OPC_ABSNEG_F:
618 case OPC_ABSNEG_S:
619 if (instr->flags & IR3_INSTR_SAT)
620 return false;
621 break;
622 default:
623 return false;
624 }
625
626 dst = instr->regs[0];
627
628 /* mov's that write to a0.x or p0.x are special: */
629 if (dst->num == regid(REG_P0, 0))
630 return false;
631 if (dst->num == regid(REG_A0, 0))
632 return false;
633
634 if (dst->flags & (IR3_REG_RELATIV | IR3_REG_ARRAY))
635 return false;
636
637 return true;
638 }
639
640 static inline bool is_alu(struct ir3_instruction *instr)
641 {
642 return (1 <= opc_cat(instr->opc)) && (opc_cat(instr->opc) <= 3);
643 }
644
645 static inline bool is_sfu(struct ir3_instruction *instr)
646 {
647 return (opc_cat(instr->opc) == 4);
648 }
649
650 static inline bool is_tex(struct ir3_instruction *instr)
651 {
652 return (opc_cat(instr->opc) == 5);
653 }
654
655 static inline bool is_mem(struct ir3_instruction *instr)
656 {
657 return (opc_cat(instr->opc) == 6);
658 }
659
660 static inline bool is_barrier(struct ir3_instruction *instr)
661 {
662 return (opc_cat(instr->opc) == 7);
663 }
664
665 static inline bool
666 is_store(struct ir3_instruction *instr)
667 {
668 /* these instructions, the "destination" register is
669 * actually a source, the address to store to.
670 */
671 switch (instr->opc) {
672 case OPC_STG:
673 case OPC_STGB:
674 case OPC_STIB:
675 case OPC_STP:
676 case OPC_STL:
677 case OPC_STLW:
678 case OPC_L2G:
679 case OPC_G2L:
680 return true;
681 default:
682 return false;
683 }
684 }
685
686 static inline bool is_load(struct ir3_instruction *instr)
687 {
688 switch (instr->opc) {
689 case OPC_LDG:
690 case OPC_LDGB:
691 case OPC_LDL:
692 case OPC_LDP:
693 case OPC_L2G:
694 case OPC_LDLW:
695 case OPC_LDC:
696 case OPC_LDLV:
697 /* probably some others too.. */
698 return true;
699 default:
700 return false;
701 }
702 }
703
704 static inline bool is_input(struct ir3_instruction *instr)
705 {
706 /* in some cases, ldlv is used to fetch varying without
707 * interpolation.. fortunately inloc is the first src
708 * register in either case
709 */
710 switch (instr->opc) {
711 case OPC_LDLV:
712 case OPC_BARY_F:
713 return true;
714 default:
715 return false;
716 }
717 }
718
719 static inline bool is_bool(struct ir3_instruction *instr)
720 {
721 switch (instr->opc) {
722 case OPC_CMPS_F:
723 case OPC_CMPS_S:
724 case OPC_CMPS_U:
725 return true;
726 default:
727 return false;
728 }
729 }
730
731 static inline bool is_meta(struct ir3_instruction *instr)
732 {
733 /* TODO how should we count PHI (and maybe fan-in/out) which
734 * might actually contribute some instructions to the final
735 * result?
736 */
737 return (opc_cat(instr->opc) == -1);
738 }
739
740 static inline bool writes_addr(struct ir3_instruction *instr)
741 {
742 if (instr->regs_count > 0) {
743 struct ir3_register *dst = instr->regs[0];
744 return reg_num(dst) == REG_A0;
745 }
746 return false;
747 }
748
749 static inline bool writes_pred(struct ir3_instruction *instr)
750 {
751 if (instr->regs_count > 0) {
752 struct ir3_register *dst = instr->regs[0];
753 return reg_num(dst) == REG_P0;
754 }
755 return false;
756 }
757
758 /* returns defining instruction for reg */
759 /* TODO better name */
760 static inline struct ir3_instruction *ssa(struct ir3_register *reg)
761 {
762 if (reg->flags & (IR3_REG_SSA | IR3_REG_ARRAY)) {
763 return reg->instr;
764 }
765 return NULL;
766 }
767
768 static inline bool conflicts(struct ir3_instruction *a,
769 struct ir3_instruction *b)
770 {
771 return (a && b) && (a != b);
772 }
773
774 static inline bool reg_gpr(struct ir3_register *r)
775 {
776 if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED))
777 return false;
778 if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0))
779 return false;
780 return true;
781 }
782
783 static inline type_t half_type(type_t type)
784 {
785 switch (type) {
786 case TYPE_F32: return TYPE_F16;
787 case TYPE_U32: return TYPE_U16;
788 case TYPE_S32: return TYPE_S16;
789 case TYPE_F16:
790 case TYPE_U16:
791 case TYPE_S16:
792 return type;
793 default:
794 assert(0);
795 return ~0;
796 }
797 }
798
799 /* some cat2 instructions (ie. those which are not float) can embed an
800 * immediate:
801 */
802 static inline bool ir3_cat2_int(opc_t opc)
803 {
804 switch (opc) {
805 case OPC_ADD_U:
806 case OPC_ADD_S:
807 case OPC_SUB_U:
808 case OPC_SUB_S:
809 case OPC_CMPS_U:
810 case OPC_CMPS_S:
811 case OPC_MIN_U:
812 case OPC_MIN_S:
813 case OPC_MAX_U:
814 case OPC_MAX_S:
815 case OPC_CMPV_U:
816 case OPC_CMPV_S:
817 case OPC_MUL_U:
818 case OPC_MUL_S:
819 case OPC_MULL_U:
820 case OPC_CLZ_S:
821 case OPC_ABSNEG_S:
822 case OPC_AND_B:
823 case OPC_OR_B:
824 case OPC_NOT_B:
825 case OPC_XOR_B:
826 case OPC_BFREV_B:
827 case OPC_CLZ_B:
828 case OPC_SHL_B:
829 case OPC_SHR_B:
830 case OPC_ASHR_B:
831 case OPC_MGEN_B:
832 case OPC_GETBIT_B:
833 case OPC_CBITS_B:
834 case OPC_BARY_F:
835 return true;
836
837 default:
838 return false;
839 }
840 }
841
842
843 /* map cat2 instruction to valid abs/neg flags: */
844 static inline unsigned ir3_cat2_absneg(opc_t opc)
845 {
846 switch (opc) {
847 case OPC_ADD_F:
848 case OPC_MIN_F:
849 case OPC_MAX_F:
850 case OPC_MUL_F:
851 case OPC_SIGN_F:
852 case OPC_CMPS_F:
853 case OPC_ABSNEG_F:
854 case OPC_CMPV_F:
855 case OPC_FLOOR_F:
856 case OPC_CEIL_F:
857 case OPC_RNDNE_F:
858 case OPC_RNDAZ_F:
859 case OPC_TRUNC_F:
860 case OPC_BARY_F:
861 return IR3_REG_FABS | IR3_REG_FNEG;
862
863 case OPC_ADD_U:
864 case OPC_ADD_S:
865 case OPC_SUB_U:
866 case OPC_SUB_S:
867 case OPC_CMPS_U:
868 case OPC_CMPS_S:
869 case OPC_MIN_U:
870 case OPC_MIN_S:
871 case OPC_MAX_U:
872 case OPC_MAX_S:
873 case OPC_CMPV_U:
874 case OPC_CMPV_S:
875 case OPC_MUL_U:
876 case OPC_MUL_S:
877 case OPC_MULL_U:
878 case OPC_CLZ_S:
879 return 0;
880
881 case OPC_ABSNEG_S:
882 return IR3_REG_SABS | IR3_REG_SNEG;
883
884 case OPC_AND_B:
885 case OPC_OR_B:
886 case OPC_NOT_B:
887 case OPC_XOR_B:
888 case OPC_BFREV_B:
889 case OPC_CLZ_B:
890 case OPC_SHL_B:
891 case OPC_SHR_B:
892 case OPC_ASHR_B:
893 case OPC_MGEN_B:
894 case OPC_GETBIT_B:
895 case OPC_CBITS_B:
896 return IR3_REG_BNOT;
897
898 default:
899 return 0;
900 }
901 }
902
903 /* map cat3 instructions to valid abs/neg flags: */
904 static inline unsigned ir3_cat3_absneg(opc_t opc)
905 {
906 switch (opc) {
907 case OPC_MAD_F16:
908 case OPC_MAD_F32:
909 case OPC_SEL_F16:
910 case OPC_SEL_F32:
911 return IR3_REG_FNEG;
912
913 case OPC_MAD_U16:
914 case OPC_MADSH_U16:
915 case OPC_MAD_S16:
916 case OPC_MADSH_M16:
917 case OPC_MAD_U24:
918 case OPC_MAD_S24:
919 case OPC_SEL_S16:
920 case OPC_SEL_S32:
921 case OPC_SAD_S16:
922 case OPC_SAD_S32:
923 /* neg *may* work on 3rd src.. */
924
925 case OPC_SEL_B16:
926 case OPC_SEL_B32:
927
928 default:
929 return 0;
930 }
931 }
932
933 #define MASK(n) ((1 << (n)) - 1)
934
935 /* iterator for an instructions's sources (reg), also returns src #: */
936 #define foreach_src_n(__srcreg, __n, __instr) \
937 if ((__instr)->regs_count) \
938 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
939 if ((__srcreg = (__instr)->regs[__n + 1]))
940
941 /* iterator for an instructions's sources (reg): */
942 #define foreach_src(__srcreg, __instr) \
943 foreach_src_n(__srcreg, __i, __instr)
944
945 static inline unsigned __ssa_src_cnt(struct ir3_instruction *instr)
946 {
947 unsigned cnt = instr->regs_count + instr->deps_count;
948 if (instr->address)
949 cnt++;
950 return cnt;
951 }
952
953 static inline struct ir3_instruction * __ssa_src_n(struct ir3_instruction *instr, unsigned n)
954 {
955 if (n == (instr->regs_count + instr->deps_count))
956 return instr->address;
957 if (n >= instr->regs_count)
958 return instr->deps[n - instr->regs_count];
959 return ssa(instr->regs[n]);
960 }
961
962 static inline bool __is_false_dep(struct ir3_instruction *instr, unsigned n)
963 {
964 if (n == (instr->regs_count + instr->deps_count))
965 return false;
966 if (n >= instr->regs_count)
967 return true;
968 return false;
969 }
970
971 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
972
973 /* iterator for an instruction's SSA sources (instr), also returns src #: */
974 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
975 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
976 if ((__srcinst = __ssa_src_n(__instr, __n)))
977
978 /* iterator for an instruction's SSA sources (instr): */
979 #define foreach_ssa_src(__srcinst, __instr) \
980 foreach_ssa_src_n(__srcinst, __i, __instr)
981
982
983 /* dump: */
984 void ir3_print(struct ir3 *ir);
985 void ir3_print_instr(struct ir3_instruction *instr);
986
987 /* depth calculation: */
988 int ir3_delayslots(struct ir3_instruction *assigner,
989 struct ir3_instruction *consumer, unsigned n);
990 void ir3_insert_by_depth(struct ir3_instruction *instr, struct list_head *list);
991 void ir3_depth(struct ir3 *ir);
992
993 /* copy-propagate: */
994 struct ir3_shader_variant;
995 void ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so);
996
997 /* group neighbors and insert mov's to resolve conflicts: */
998 void ir3_group(struct ir3 *ir);
999
1000 /* scheduling: */
1001 void ir3_sched_add_deps(struct ir3 *ir);
1002 int ir3_sched(struct ir3 *ir);
1003
1004 /* register assignment: */
1005 struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler);
1006 int ir3_ra(struct ir3 *ir3, gl_shader_stage type,
1007 bool frag_coord, bool frag_face);
1008
1009 /* legalize: */
1010 void ir3_legalize(struct ir3 *ir, int *num_samp, bool *has_ssbo, int *max_bary);
1011
1012 /* ************************************************************************* */
1013 /* instruction helpers */
1014
1015 /* creates SSA src of correct type (ie. half vs full precision) */
1016 static inline struct ir3_register * __ssa_src(struct ir3_instruction *instr,
1017 struct ir3_instruction *src, unsigned flags)
1018 {
1019 struct ir3_register *reg;
1020 if (src->regs[0]->flags & IR3_REG_HALF)
1021 flags |= IR3_REG_HALF;
1022 reg = ir3_reg_create(instr, 0, IR3_REG_SSA | flags);
1023 reg->instr = src;
1024 return reg;
1025 }
1026
1027 static inline struct ir3_instruction *
1028 ir3_MOV(struct ir3_block *block, struct ir3_instruction *src, type_t type)
1029 {
1030 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1031 ir3_reg_create(instr, 0, 0); /* dst */
1032 if (src->regs[0]->flags & IR3_REG_ARRAY) {
1033 struct ir3_register *src_reg = __ssa_src(instr, src, IR3_REG_ARRAY);
1034 src_reg->array = src->regs[0]->array;
1035 } else {
1036 __ssa_src(instr, src, 0);
1037 }
1038 debug_assert(!(src->regs[0]->flags & IR3_REG_RELATIV));
1039 instr->cat1.src_type = type;
1040 instr->cat1.dst_type = type;
1041 return instr;
1042 }
1043
1044 static inline struct ir3_instruction *
1045 ir3_COV(struct ir3_block *block, struct ir3_instruction *src,
1046 type_t src_type, type_t dst_type)
1047 {
1048 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1049 unsigned dst_flags = (type_size(dst_type) < 32) ? IR3_REG_HALF : 0;
1050 unsigned src_flags = (type_size(src_type) < 32) ? IR3_REG_HALF : 0;
1051
1052 debug_assert((src->regs[0]->flags & IR3_REG_HALF) == src_flags);
1053
1054 ir3_reg_create(instr, 0, dst_flags); /* dst */
1055 __ssa_src(instr, src, 0);
1056 instr->cat1.src_type = src_type;
1057 instr->cat1.dst_type = dst_type;
1058 debug_assert(!(src->regs[0]->flags & IR3_REG_ARRAY));
1059 return instr;
1060 }
1061
1062 static inline struct ir3_instruction *
1063 ir3_NOP(struct ir3_block *block)
1064 {
1065 return ir3_instr_create(block, OPC_NOP);
1066 }
1067
1068 #define INSTR0(name) \
1069 static inline struct ir3_instruction * \
1070 ir3_##name(struct ir3_block *block) \
1071 { \
1072 struct ir3_instruction *instr = \
1073 ir3_instr_create(block, OPC_##name); \
1074 return instr; \
1075 }
1076
1077 #define INSTR1(name) \
1078 static inline struct ir3_instruction * \
1079 ir3_##name(struct ir3_block *block, \
1080 struct ir3_instruction *a, unsigned aflags) \
1081 { \
1082 struct ir3_instruction *instr = \
1083 ir3_instr_create(block, OPC_##name); \
1084 ir3_reg_create(instr, 0, 0); /* dst */ \
1085 __ssa_src(instr, a, aflags); \
1086 return instr; \
1087 }
1088
1089 #define INSTR2(name) \
1090 static inline struct ir3_instruction * \
1091 ir3_##name(struct ir3_block *block, \
1092 struct ir3_instruction *a, unsigned aflags, \
1093 struct ir3_instruction *b, unsigned bflags) \
1094 { \
1095 struct ir3_instruction *instr = \
1096 ir3_instr_create(block, OPC_##name); \
1097 ir3_reg_create(instr, 0, 0); /* dst */ \
1098 __ssa_src(instr, a, aflags); \
1099 __ssa_src(instr, b, bflags); \
1100 return instr; \
1101 }
1102
1103 #define INSTR3(name) \
1104 static inline struct ir3_instruction * \
1105 ir3_##name(struct ir3_block *block, \
1106 struct ir3_instruction *a, unsigned aflags, \
1107 struct ir3_instruction *b, unsigned bflags, \
1108 struct ir3_instruction *c, unsigned cflags) \
1109 { \
1110 struct ir3_instruction *instr = \
1111 ir3_instr_create(block, OPC_##name); \
1112 ir3_reg_create(instr, 0, 0); /* dst */ \
1113 __ssa_src(instr, a, aflags); \
1114 __ssa_src(instr, b, bflags); \
1115 __ssa_src(instr, c, cflags); \
1116 return instr; \
1117 }
1118
1119 #define INSTR4(name) \
1120 static inline struct ir3_instruction * \
1121 ir3_##name(struct ir3_block *block, \
1122 struct ir3_instruction *a, unsigned aflags, \
1123 struct ir3_instruction *b, unsigned bflags, \
1124 struct ir3_instruction *c, unsigned cflags, \
1125 struct ir3_instruction *d, unsigned dflags) \
1126 { \
1127 struct ir3_instruction *instr = \
1128 ir3_instr_create2(block, OPC_##name, 5); \
1129 ir3_reg_create(instr, 0, 0); /* dst */ \
1130 __ssa_src(instr, a, aflags); \
1131 __ssa_src(instr, b, bflags); \
1132 __ssa_src(instr, c, cflags); \
1133 __ssa_src(instr, d, dflags); \
1134 return instr; \
1135 }
1136
1137 #define INSTR4F(f, name) \
1138 static inline struct ir3_instruction * \
1139 ir3_##name##_##f(struct ir3_block *block, \
1140 struct ir3_instruction *a, unsigned aflags, \
1141 struct ir3_instruction *b, unsigned bflags, \
1142 struct ir3_instruction *c, unsigned cflags, \
1143 struct ir3_instruction *d, unsigned dflags) \
1144 { \
1145 struct ir3_instruction *instr = \
1146 ir3_instr_create2(block, OPC_##name, 5); \
1147 ir3_reg_create(instr, 0, 0); /* dst */ \
1148 __ssa_src(instr, a, aflags); \
1149 __ssa_src(instr, b, bflags); \
1150 __ssa_src(instr, c, cflags); \
1151 __ssa_src(instr, d, dflags); \
1152 instr->flags |= IR3_INSTR_##f; \
1153 return instr; \
1154 }
1155
1156 /* cat0 instructions: */
1157 INSTR0(BR)
1158 INSTR0(JUMP)
1159 INSTR1(KILL)
1160 INSTR0(END)
1161
1162 /* cat2 instructions, most 2 src but some 1 src: */
1163 INSTR2(ADD_F)
1164 INSTR2(MIN_F)
1165 INSTR2(MAX_F)
1166 INSTR2(MUL_F)
1167 INSTR1(SIGN_F)
1168 INSTR2(CMPS_F)
1169 INSTR1(ABSNEG_F)
1170 INSTR2(CMPV_F)
1171 INSTR1(FLOOR_F)
1172 INSTR1(CEIL_F)
1173 INSTR1(RNDNE_F)
1174 INSTR1(RNDAZ_F)
1175 INSTR1(TRUNC_F)
1176 INSTR2(ADD_U)
1177 INSTR2(ADD_S)
1178 INSTR2(SUB_U)
1179 INSTR2(SUB_S)
1180 INSTR2(CMPS_U)
1181 INSTR2(CMPS_S)
1182 INSTR2(MIN_U)
1183 INSTR2(MIN_S)
1184 INSTR2(MAX_U)
1185 INSTR2(MAX_S)
1186 INSTR1(ABSNEG_S)
1187 INSTR2(AND_B)
1188 INSTR2(OR_B)
1189 INSTR1(NOT_B)
1190 INSTR2(XOR_B)
1191 INSTR2(CMPV_U)
1192 INSTR2(CMPV_S)
1193 INSTR2(MUL_U)
1194 INSTR2(MUL_S)
1195 INSTR2(MULL_U)
1196 INSTR1(BFREV_B)
1197 INSTR1(CLZ_S)
1198 INSTR1(CLZ_B)
1199 INSTR2(SHL_B)
1200 INSTR2(SHR_B)
1201 INSTR2(ASHR_B)
1202 INSTR2(BARY_F)
1203 INSTR2(MGEN_B)
1204 INSTR2(GETBIT_B)
1205 INSTR1(SETRM)
1206 INSTR1(CBITS_B)
1207 INSTR2(SHB)
1208 INSTR2(MSAD)
1209
1210 /* cat3 instructions: */
1211 INSTR3(MAD_U16)
1212 INSTR3(MADSH_U16)
1213 INSTR3(MAD_S16)
1214 INSTR3(MADSH_M16)
1215 INSTR3(MAD_U24)
1216 INSTR3(MAD_S24)
1217 INSTR3(MAD_F16)
1218 INSTR3(MAD_F32)
1219 INSTR3(SEL_B16)
1220 INSTR3(SEL_B32)
1221 INSTR3(SEL_S16)
1222 INSTR3(SEL_S32)
1223 INSTR3(SEL_F16)
1224 INSTR3(SEL_F32)
1225 INSTR3(SAD_S16)
1226 INSTR3(SAD_S32)
1227
1228 /* cat4 instructions: */
1229 INSTR1(RCP)
1230 INSTR1(RSQ)
1231 INSTR1(LOG2)
1232 INSTR1(EXP2)
1233 INSTR1(SIN)
1234 INSTR1(COS)
1235 INSTR1(SQRT)
1236
1237 /* cat5 instructions: */
1238 INSTR1(DSX)
1239 INSTR1(DSY)
1240
1241 static inline struct ir3_instruction *
1242 ir3_SAM(struct ir3_block *block, opc_t opc, type_t type,
1243 unsigned wrmask, unsigned flags, unsigned samp, unsigned tex,
1244 struct ir3_instruction *src0, struct ir3_instruction *src1)
1245 {
1246 struct ir3_instruction *sam;
1247 struct ir3_register *reg;
1248
1249 sam = ir3_instr_create(block, opc);
1250 sam->flags |= flags;
1251 ir3_reg_create(sam, 0, 0)->wrmask = wrmask;
1252 if (src0) {
1253 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
1254 reg->wrmask = (1 << (src0->regs_count - 1)) - 1;
1255 reg->instr = src0;
1256 }
1257 if (src1) {
1258 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
1259 reg->instr = src1;
1260 reg->wrmask = (1 << (src1->regs_count - 1)) - 1;
1261 }
1262 sam->cat5.samp = samp;
1263 sam->cat5.tex = tex;
1264 sam->cat5.type = type;
1265
1266 return sam;
1267 }
1268
1269 /* cat6 instructions: */
1270 INSTR2(LDLV)
1271 INSTR2(LDG)
1272 INSTR2(LDL)
1273 INSTR3(STG)
1274 INSTR3(STL)
1275 INSTR3(LDGB)
1276 INSTR4(STGB)
1277 INSTR4(STIB)
1278 INSTR1(RESINFO)
1279 INSTR1(RESFMT)
1280 INSTR2(ATOMIC_ADD)
1281 INSTR2(ATOMIC_SUB)
1282 INSTR2(ATOMIC_XCHG)
1283 INSTR2(ATOMIC_INC)
1284 INSTR2(ATOMIC_DEC)
1285 INSTR2(ATOMIC_CMPXCHG)
1286 INSTR2(ATOMIC_MIN)
1287 INSTR2(ATOMIC_MAX)
1288 INSTR2(ATOMIC_AND)
1289 INSTR2(ATOMIC_OR)
1290 INSTR2(ATOMIC_XOR)
1291 INSTR4F(G, ATOMIC_ADD)
1292 INSTR4F(G, ATOMIC_SUB)
1293 INSTR4F(G, ATOMIC_XCHG)
1294 INSTR4F(G, ATOMIC_INC)
1295 INSTR4F(G, ATOMIC_DEC)
1296 INSTR4F(G, ATOMIC_CMPXCHG)
1297 INSTR4F(G, ATOMIC_MIN)
1298 INSTR4F(G, ATOMIC_MAX)
1299 INSTR4F(G, ATOMIC_AND)
1300 INSTR4F(G, ATOMIC_OR)
1301 INSTR4F(G, ATOMIC_XOR)
1302
1303 /* cat7 instructions: */
1304 INSTR0(BAR)
1305 INSTR0(FENCE)
1306
1307 /* ************************************************************************* */
1308 /* split this out or find some helper to use.. like main/bitset.h.. */
1309
1310 #include <string.h>
1311
1312 #define MAX_REG 256
1313
1314 typedef uint8_t regmask_t[2 * MAX_REG / 8];
1315
1316 static inline unsigned regmask_idx(struct ir3_register *reg)
1317 {
1318 unsigned num = (reg->flags & IR3_REG_RELATIV) ? reg->array.offset : reg->num;
1319 debug_assert(num < MAX_REG);
1320 if (reg->flags & IR3_REG_HALF)
1321 num += MAX_REG;
1322 return num;
1323 }
1324
1325 static inline void regmask_init(regmask_t *regmask)
1326 {
1327 memset(regmask, 0, sizeof(*regmask));
1328 }
1329
1330 static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg)
1331 {
1332 unsigned idx = regmask_idx(reg);
1333 if (reg->flags & IR3_REG_RELATIV) {
1334 unsigned i;
1335 for (i = 0; i < reg->size; i++, idx++)
1336 (*regmask)[idx / 8] |= 1 << (idx % 8);
1337 } else {
1338 unsigned mask;
1339 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1340 if (mask & 1)
1341 (*regmask)[idx / 8] |= 1 << (idx % 8);
1342 }
1343 }
1344
1345 static inline void regmask_or(regmask_t *dst, regmask_t *a, regmask_t *b)
1346 {
1347 unsigned i;
1348 for (i = 0; i < ARRAY_SIZE(*dst); i++)
1349 (*dst)[i] = (*a)[i] | (*b)[i];
1350 }
1351
1352 /* set bits in a if not set in b, conceptually:
1353 * a |= (reg & ~b)
1354 */
1355 static inline void regmask_set_if_not(regmask_t *a,
1356 struct ir3_register *reg, regmask_t *b)
1357 {
1358 unsigned idx = regmask_idx(reg);
1359 if (reg->flags & IR3_REG_RELATIV) {
1360 unsigned i;
1361 for (i = 0; i < reg->size; i++, idx++)
1362 if (!((*b)[idx / 8] & (1 << (idx % 8))))
1363 (*a)[idx / 8] |= 1 << (idx % 8);
1364 } else {
1365 unsigned mask;
1366 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1367 if (mask & 1)
1368 if (!((*b)[idx / 8] & (1 << (idx % 8))))
1369 (*a)[idx / 8] |= 1 << (idx % 8);
1370 }
1371 }
1372
1373 static inline bool regmask_get(regmask_t *regmask,
1374 struct ir3_register *reg)
1375 {
1376 unsigned idx = regmask_idx(reg);
1377 if (reg->flags & IR3_REG_RELATIV) {
1378 unsigned i;
1379 for (i = 0; i < reg->size; i++, idx++)
1380 if ((*regmask)[idx / 8] & (1 << (idx % 8)))
1381 return true;
1382 } else {
1383 unsigned mask;
1384 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1385 if (mask & 1)
1386 if ((*regmask)[idx / 8] & (1 << (idx % 8)))
1387 return true;
1388 }
1389 return false;
1390 }
1391
1392 /* ************************************************************************* */
1393
1394 #endif /* IR3_H_ */