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freedreno/ir3: use nopN encoding when possible
[mesa.git] / src / freedreno / ir3 / ir3.h
1 /*
2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #ifndef IR3_H_
25 #define IR3_H_
26
27 #include <stdint.h>
28 #include <stdbool.h>
29
30 #include "compiler/shader_enums.h"
31
32 #include "util/u_debug.h"
33 #include "util/list.h"
34
35 #include "instr-a3xx.h"
36
37 /* low level intermediate representation of an adreno shader program */
38
39 struct ir3_compiler;
40 struct ir3;
41 struct ir3_instruction;
42 struct ir3_block;
43
44 struct ir3_info {
45 uint32_t gpu_id;
46 uint16_t sizedwords;
47 uint16_t instrs_count; /* expanded to account for rpt's */
48 /* NOTE: max_reg, etc, does not include registers not touched
49 * by the shader (ie. vertex fetched via VFD_DECODE but not
50 * touched by shader)
51 */
52 int8_t max_reg; /* highest GPR # used by shader */
53 int8_t max_half_reg;
54 int16_t max_const;
55
56 /* number of sync bits: */
57 uint16_t ss, sy;
58 };
59
60 struct ir3_register {
61 enum {
62 IR3_REG_CONST = 0x001,
63 IR3_REG_IMMED = 0x002,
64 IR3_REG_HALF = 0x004,
65 /* high registers are used for some things in compute shaders,
66 * for example. Seems to be for things that are global to all
67 * threads in a wave, so possibly these are global/shared by
68 * all the threads in the wave?
69 */
70 IR3_REG_HIGH = 0x008,
71 IR3_REG_RELATIV= 0x010,
72 IR3_REG_R = 0x020,
73 /* Most instructions, it seems, can do float abs/neg but not
74 * integer. The CP pass needs to know what is intended (int or
75 * float) in order to do the right thing. For this reason the
76 * abs/neg flags are split out into float and int variants. In
77 * addition, .b (bitwise) operations, the negate is actually a
78 * bitwise not, so split that out into a new flag to make it
79 * more clear.
80 */
81 IR3_REG_FNEG = 0x040,
82 IR3_REG_FABS = 0x080,
83 IR3_REG_SNEG = 0x100,
84 IR3_REG_SABS = 0x200,
85 IR3_REG_BNOT = 0x400,
86 IR3_REG_EVEN = 0x800,
87 IR3_REG_POS_INF= 0x1000,
88 /* (ei) flag, end-input? Set on last bary, presumably to signal
89 * that the shader needs no more input:
90 */
91 IR3_REG_EI = 0x2000,
92 /* meta-flags, for intermediate stages of IR, ie.
93 * before register assignment is done:
94 */
95 IR3_REG_SSA = 0x4000, /* 'instr' is ptr to assigning instr */
96 IR3_REG_ARRAY = 0x8000,
97
98 } flags;
99
100 /* normal registers:
101 * the component is in the low two bits of the reg #, so
102 * rN.x becomes: (N << 2) | x
103 */
104 int num;
105 union {
106 /* immediate: */
107 int32_t iim_val;
108 uint32_t uim_val;
109 float fim_val;
110 /* relative: */
111 struct {
112 uint16_t id;
113 int16_t offset;
114 } array;
115 };
116
117 /* For IR3_REG_SSA, src registers contain ptr back to assigning
118 * instruction.
119 *
120 * For IR3_REG_ARRAY, the pointer is back to the last dependent
121 * array access (although the net effect is the same, it points
122 * back to a previous instruction that we depend on).
123 */
124 struct ir3_instruction *instr;
125
126 union {
127 /* used for cat5 instructions, but also for internal/IR level
128 * tracking of what registers are read/written by an instruction.
129 * wrmask may be a bad name since it is used to represent both
130 * src and dst that touch multiple adjacent registers.
131 */
132 unsigned wrmask;
133 /* for relative addressing, 32bits for array size is too small,
134 * but otoh we don't need to deal with disjoint sets, so instead
135 * use a simple size field (number of scalar components).
136 */
137 unsigned size;
138 };
139 };
140
141 /*
142 * Stupid/simple growable array implementation:
143 */
144 #define DECLARE_ARRAY(type, name) \
145 unsigned name ## _count, name ## _sz; \
146 type * name;
147
148 #define array_insert(ctx, arr, val) do { \
149 if (arr ## _count == arr ## _sz) { \
150 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
151 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
152 } \
153 arr[arr ##_count++] = val; \
154 } while (0)
155
156 struct ir3_instruction {
157 struct ir3_block *block;
158 opc_t opc;
159 enum {
160 /* (sy) flag is set on first instruction, and after sample
161 * instructions (probably just on RAW hazard).
162 */
163 IR3_INSTR_SY = 0x001,
164 /* (ss) flag is set on first instruction, and first instruction
165 * to depend on the result of "long" instructions (RAW hazard):
166 *
167 * rcp, rsq, log2, exp2, sin, cos, sqrt
168 *
169 * It seems to synchronize until all in-flight instructions are
170 * completed, for example:
171 *
172 * rsq hr1.w, hr1.w
173 * add.f hr2.z, (neg)hr2.z, hc0.y
174 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
175 * rsq hr2.x, hr2.x
176 * (rpt1)nop
177 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
178 * nop
179 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
180 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
181 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
182 *
183 * The last mul.f does not have (ss) set, presumably because the
184 * (ss) on the previous instruction does the job.
185 *
186 * The blob driver also seems to set it on WAR hazards, although
187 * not really clear if this is needed or just blob compiler being
188 * sloppy. So far I haven't found a case where removing the (ss)
189 * causes problems for WAR hazard, but I could just be getting
190 * lucky:
191 *
192 * rcp r1.y, r3.y
193 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
194 *
195 */
196 IR3_INSTR_SS = 0x002,
197 /* (jp) flag is set on jump targets:
198 */
199 IR3_INSTR_JP = 0x004,
200 IR3_INSTR_UL = 0x008,
201 IR3_INSTR_3D = 0x010,
202 IR3_INSTR_A = 0x020,
203 IR3_INSTR_O = 0x040,
204 IR3_INSTR_P = 0x080,
205 IR3_INSTR_S = 0x100,
206 IR3_INSTR_S2EN = 0x200,
207 IR3_INSTR_G = 0x400,
208 IR3_INSTR_SAT = 0x800,
209 /* meta-flags, for intermediate stages of IR, ie.
210 * before register assignment is done:
211 */
212 IR3_INSTR_MARK = 0x1000,
213 IR3_INSTR_UNUSED= 0x2000,
214 } flags;
215 uint8_t repeat;
216 uint8_t nop;
217 #ifdef DEBUG
218 unsigned regs_max;
219 #endif
220 unsigned regs_count;
221 struct ir3_register **regs;
222 union {
223 struct {
224 char inv;
225 char comp;
226 int immed;
227 struct ir3_block *target;
228 } cat0;
229 struct {
230 type_t src_type, dst_type;
231 } cat1;
232 struct {
233 enum {
234 IR3_COND_LT = 0,
235 IR3_COND_LE = 1,
236 IR3_COND_GT = 2,
237 IR3_COND_GE = 3,
238 IR3_COND_EQ = 4,
239 IR3_COND_NE = 5,
240 } condition;
241 } cat2;
242 struct {
243 unsigned samp, tex;
244 type_t type;
245 } cat5;
246 struct {
247 type_t type;
248 int src_offset;
249 int dst_offset;
250 int iim_val : 3; /* for ldgb/stgb, # of components */
251 int d : 3;
252 bool typed : 1;
253 } cat6;
254 struct {
255 unsigned w : 1; /* write */
256 unsigned r : 1; /* read */
257 unsigned l : 1; /* local */
258 unsigned g : 1; /* global */
259 } cat7;
260 /* for meta-instructions, just used to hold extra data
261 * before instruction scheduling, etc
262 */
263 struct {
264 int off; /* component/offset */
265 } fo;
266 struct {
267 struct ir3_block *block;
268 } inout;
269 };
270
271 /* transient values used during various algorithms: */
272 union {
273 /* The instruction depth is the max dependency distance to output.
274 *
275 * You can also think of it as the "cost", if we did any sort of
276 * optimization for register footprint. Ie. a value that is just
277 * result of moving a const to a reg would have a low cost, so to
278 * it could make sense to duplicate the instruction at various
279 * points where the result is needed to reduce register footprint.
280 */
281 unsigned depth;
282 /* When we get to the RA stage, we no longer need depth, but
283 * we do need instruction's position/name:
284 */
285 struct {
286 uint16_t ip;
287 uint16_t name;
288 };
289 };
290
291 /* used for per-pass extra instruction data.
292 */
293 void *data;
294
295 /* Used during CP and RA stages. For fanin and shader inputs/
296 * outputs where we need a sequence of consecutive registers,
297 * keep track of each src instructions left (ie 'n-1') and right
298 * (ie 'n+1') neighbor. The front-end must insert enough mov's
299 * to ensure that each instruction has at most one left and at
300 * most one right neighbor. During the copy-propagation pass,
301 * we only remove mov's when we can preserve this constraint.
302 * And during the RA stage, we use the neighbor information to
303 * allocate a block of registers in one shot.
304 *
305 * TODO: maybe just add something like:
306 * struct ir3_instruction_ref {
307 * struct ir3_instruction *instr;
308 * unsigned cnt;
309 * }
310 *
311 * Or can we get away without the refcnt stuff? It seems like
312 * it should be overkill.. the problem is if, potentially after
313 * already eliminating some mov's, if you have a single mov that
314 * needs to be grouped with it's neighbors in two different
315 * places (ex. shader output and a fanin).
316 */
317 struct {
318 struct ir3_instruction *left, *right;
319 uint16_t left_cnt, right_cnt;
320 } cp;
321
322 /* an instruction can reference at most one address register amongst
323 * it's src/dst registers. Beyond that, you need to insert mov's.
324 *
325 * NOTE: do not write this directly, use ir3_instr_set_address()
326 */
327 struct ir3_instruction *address;
328
329 /* Tracking for additional dependent instructions. Used to handle
330 * barriers, WAR hazards for arrays/SSBOs/etc.
331 */
332 DECLARE_ARRAY(struct ir3_instruction *, deps);
333
334 /*
335 * From PoV of instruction scheduling, not execution (ie. ignores global/
336 * local distinction):
337 * shared image atomic SSBO everything
338 * barrier()/ - R/W R/W R/W R/W X
339 * groupMemoryBarrier()
340 * memoryBarrier() - R/W R/W
341 * (but only images declared coherent?)
342 * memoryBarrierAtomic() - R/W
343 * memoryBarrierBuffer() - R/W
344 * memoryBarrierImage() - R/W
345 * memoryBarrierShared() - R/W
346 *
347 * TODO I think for SSBO/image/shared, in cases where we can determine
348 * which variable is accessed, we don't need to care about accesses to
349 * different variables (unless declared coherent??)
350 */
351 enum {
352 IR3_BARRIER_EVERYTHING = 1 << 0,
353 IR3_BARRIER_SHARED_R = 1 << 1,
354 IR3_BARRIER_SHARED_W = 1 << 2,
355 IR3_BARRIER_IMAGE_R = 1 << 3,
356 IR3_BARRIER_IMAGE_W = 1 << 4,
357 IR3_BARRIER_BUFFER_R = 1 << 5,
358 IR3_BARRIER_BUFFER_W = 1 << 6,
359 IR3_BARRIER_ARRAY_R = 1 << 7,
360 IR3_BARRIER_ARRAY_W = 1 << 8,
361 } barrier_class, barrier_conflict;
362
363 /* Entry in ir3_block's instruction list: */
364 struct list_head node;
365
366 int use_count; /* currently just updated/used by cp */
367
368 #ifdef DEBUG
369 uint32_t serialno;
370 #endif
371 };
372
373 static inline struct ir3_instruction *
374 ir3_neighbor_first(struct ir3_instruction *instr)
375 {
376 int cnt = 0;
377 while (instr->cp.left) {
378 instr = instr->cp.left;
379 if (++cnt > 0xffff) {
380 debug_assert(0);
381 break;
382 }
383 }
384 return instr;
385 }
386
387 static inline int ir3_neighbor_count(struct ir3_instruction *instr)
388 {
389 int num = 1;
390
391 debug_assert(!instr->cp.left);
392
393 while (instr->cp.right) {
394 num++;
395 instr = instr->cp.right;
396 if (num > 0xffff) {
397 debug_assert(0);
398 break;
399 }
400 }
401
402 return num;
403 }
404
405 struct ir3 {
406 struct ir3_compiler *compiler;
407
408 unsigned ninputs, noutputs;
409 struct ir3_instruction **inputs;
410 struct ir3_instruction **outputs;
411
412 /* Track bary.f (and ldlv) instructions.. this is needed in
413 * scheduling to ensure that all varying fetches happen before
414 * any potential kill instructions. The hw gets grumpy if all
415 * threads in a group are killed before the last bary.f gets
416 * a chance to signal end of input (ei).
417 */
418 DECLARE_ARRAY(struct ir3_instruction *, baryfs);
419
420 /* Track all indirect instructions (read and write). To avoid
421 * deadlock scenario where an address register gets scheduled,
422 * but other dependent src instructions cannot be scheduled due
423 * to dependency on a *different* address register value, the
424 * scheduler needs to ensure that all dependencies other than
425 * the instruction other than the address register are scheduled
426 * before the one that writes the address register. Having a
427 * convenient list of instructions that reference some address
428 * register simplifies this.
429 */
430 DECLARE_ARRAY(struct ir3_instruction *, indirects);
431
432 /* and same for instructions that consume predicate register: */
433 DECLARE_ARRAY(struct ir3_instruction *, predicates);
434
435 /* Track texture sample instructions which need texture state
436 * patched in (for astc-srgb workaround):
437 */
438 DECLARE_ARRAY(struct ir3_instruction *, astc_srgb);
439
440 /* List of blocks: */
441 struct list_head block_list;
442
443 /* List of ir3_array's: */
444 struct list_head array_list;
445
446 #ifdef DEBUG
447 unsigned block_count, instr_count;
448 #endif
449 };
450
451 struct ir3_array {
452 struct list_head node;
453 unsigned length;
454 unsigned id;
455
456 struct nir_register *r;
457
458 /* To avoid array write's from getting DCE'd, keep track of the
459 * most recent write. Any array access depends on the most
460 * recent write. This way, nothing depends on writes after the
461 * last read. But all the writes that happen before that have
462 * something depending on them
463 */
464 struct ir3_instruction *last_write;
465
466 /* extra stuff used in RA pass: */
467 unsigned base; /* base vreg name */
468 unsigned reg; /* base physical reg */
469 uint16_t start_ip, end_ip;
470 };
471
472 struct ir3_array * ir3_lookup_array(struct ir3 *ir, unsigned id);
473
474 struct ir3_block {
475 struct list_head node;
476 struct ir3 *shader;
477
478 const struct nir_block *nblock;
479
480 struct list_head instr_list; /* list of ir3_instruction */
481
482 /* each block has either one or two successors.. in case of
483 * two successors, 'condition' decides which one to follow.
484 * A block preceding an if/else has two successors.
485 */
486 struct ir3_instruction *condition;
487 struct ir3_block *successors[2];
488
489 unsigned predecessors_count;
490 struct ir3_block **predecessors;
491
492 uint16_t start_ip, end_ip;
493
494 /* Track instructions which do not write a register but other-
495 * wise must not be discarded (such as kill, stg, etc)
496 */
497 DECLARE_ARRAY(struct ir3_instruction *, keeps);
498
499 /* used for per-pass extra block data. Mainly used right
500 * now in RA step to track livein/liveout.
501 */
502 void *data;
503
504 #ifdef DEBUG
505 uint32_t serialno;
506 #endif
507 };
508
509 static inline uint32_t
510 block_id(struct ir3_block *block)
511 {
512 #ifdef DEBUG
513 return block->serialno;
514 #else
515 return (uint32_t)(unsigned long)block;
516 #endif
517 }
518
519 struct ir3 * ir3_create(struct ir3_compiler *compiler,
520 unsigned nin, unsigned nout);
521 void ir3_destroy(struct ir3 *shader);
522 void * ir3_assemble(struct ir3 *shader,
523 struct ir3_info *info, uint32_t gpu_id);
524 void * ir3_alloc(struct ir3 *shader, int sz);
525
526 struct ir3_block * ir3_block_create(struct ir3 *shader);
527
528 struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc);
529 struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
530 opc_t opc, int nreg);
531 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
532 void ir3_instr_add_dep(struct ir3_instruction *instr, struct ir3_instruction *dep);
533 const char *ir3_instr_name(struct ir3_instruction *instr);
534
535 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
536 int num, int flags);
537 struct ir3_register * ir3_reg_clone(struct ir3 *shader,
538 struct ir3_register *reg);
539
540 void ir3_instr_set_address(struct ir3_instruction *instr,
541 struct ir3_instruction *addr);
542
543 static inline bool ir3_instr_check_mark(struct ir3_instruction *instr)
544 {
545 if (instr->flags & IR3_INSTR_MARK)
546 return true; /* already visited */
547 instr->flags |= IR3_INSTR_MARK;
548 return false;
549 }
550
551 void ir3_block_clear_mark(struct ir3_block *block);
552 void ir3_clear_mark(struct ir3 *shader);
553
554 unsigned ir3_count_instructions(struct ir3 *ir);
555
556 static inline int ir3_instr_regno(struct ir3_instruction *instr,
557 struct ir3_register *reg)
558 {
559 unsigned i;
560 for (i = 0; i < instr->regs_count; i++)
561 if (reg == instr->regs[i])
562 return i;
563 return -1;
564 }
565
566
567 #define MAX_ARRAYS 16
568
569 /* comp:
570 * 0 - x
571 * 1 - y
572 * 2 - z
573 * 3 - w
574 */
575 static inline uint32_t regid(int num, int comp)
576 {
577 return (num << 2) | (comp & 0x3);
578 }
579
580 static inline uint32_t reg_num(struct ir3_register *reg)
581 {
582 return reg->num >> 2;
583 }
584
585 static inline uint32_t reg_comp(struct ir3_register *reg)
586 {
587 return reg->num & 0x3;
588 }
589
590 static inline bool is_flow(struct ir3_instruction *instr)
591 {
592 return (opc_cat(instr->opc) == 0);
593 }
594
595 static inline bool is_kill(struct ir3_instruction *instr)
596 {
597 return instr->opc == OPC_KILL;
598 }
599
600 static inline bool is_nop(struct ir3_instruction *instr)
601 {
602 return instr->opc == OPC_NOP;
603 }
604
605 /* Is it a non-transformative (ie. not type changing) mov? This can
606 * also include absneg.s/absneg.f, which for the most part can be
607 * treated as a mov (single src argument).
608 */
609 static inline bool is_same_type_mov(struct ir3_instruction *instr)
610 {
611 struct ir3_register *dst;
612
613 switch (instr->opc) {
614 case OPC_MOV:
615 if (instr->cat1.src_type != instr->cat1.dst_type)
616 return false;
617 break;
618 case OPC_ABSNEG_F:
619 case OPC_ABSNEG_S:
620 if (instr->flags & IR3_INSTR_SAT)
621 return false;
622 break;
623 default:
624 return false;
625 }
626
627 dst = instr->regs[0];
628
629 /* mov's that write to a0.x or p0.x are special: */
630 if (dst->num == regid(REG_P0, 0))
631 return false;
632 if (dst->num == regid(REG_A0, 0))
633 return false;
634
635 if (dst->flags & (IR3_REG_RELATIV | IR3_REG_ARRAY))
636 return false;
637
638 return true;
639 }
640
641 static inline bool is_alu(struct ir3_instruction *instr)
642 {
643 return (1 <= opc_cat(instr->opc)) && (opc_cat(instr->opc) <= 3);
644 }
645
646 static inline bool is_sfu(struct ir3_instruction *instr)
647 {
648 return (opc_cat(instr->opc) == 4);
649 }
650
651 static inline bool is_tex(struct ir3_instruction *instr)
652 {
653 return (opc_cat(instr->opc) == 5);
654 }
655
656 static inline bool is_mem(struct ir3_instruction *instr)
657 {
658 return (opc_cat(instr->opc) == 6);
659 }
660
661 static inline bool is_barrier(struct ir3_instruction *instr)
662 {
663 return (opc_cat(instr->opc) == 7);
664 }
665
666 static inline bool
667 is_store(struct ir3_instruction *instr)
668 {
669 /* these instructions, the "destination" register is
670 * actually a source, the address to store to.
671 */
672 switch (instr->opc) {
673 case OPC_STG:
674 case OPC_STGB:
675 case OPC_STIB:
676 case OPC_STP:
677 case OPC_STL:
678 case OPC_STLW:
679 case OPC_L2G:
680 case OPC_G2L:
681 return true;
682 default:
683 return false;
684 }
685 }
686
687 static inline bool is_load(struct ir3_instruction *instr)
688 {
689 switch (instr->opc) {
690 case OPC_LDG:
691 case OPC_LDGB:
692 case OPC_LDIB:
693 case OPC_LDL:
694 case OPC_LDP:
695 case OPC_L2G:
696 case OPC_LDLW:
697 case OPC_LDC:
698 case OPC_LDLV:
699 /* probably some others too.. */
700 return true;
701 default:
702 return false;
703 }
704 }
705
706 static inline bool is_input(struct ir3_instruction *instr)
707 {
708 /* in some cases, ldlv is used to fetch varying without
709 * interpolation.. fortunately inloc is the first src
710 * register in either case
711 */
712 switch (instr->opc) {
713 case OPC_LDLV:
714 case OPC_BARY_F:
715 return true;
716 default:
717 return false;
718 }
719 }
720
721 static inline bool is_bool(struct ir3_instruction *instr)
722 {
723 switch (instr->opc) {
724 case OPC_CMPS_F:
725 case OPC_CMPS_S:
726 case OPC_CMPS_U:
727 return true;
728 default:
729 return false;
730 }
731 }
732
733 static inline bool is_meta(struct ir3_instruction *instr)
734 {
735 /* TODO how should we count PHI (and maybe fan-in/out) which
736 * might actually contribute some instructions to the final
737 * result?
738 */
739 return (opc_cat(instr->opc) == -1);
740 }
741
742 static inline bool writes_addr(struct ir3_instruction *instr)
743 {
744 if (instr->regs_count > 0) {
745 struct ir3_register *dst = instr->regs[0];
746 return reg_num(dst) == REG_A0;
747 }
748 return false;
749 }
750
751 static inline bool writes_pred(struct ir3_instruction *instr)
752 {
753 if (instr->regs_count > 0) {
754 struct ir3_register *dst = instr->regs[0];
755 return reg_num(dst) == REG_P0;
756 }
757 return false;
758 }
759
760 /* returns defining instruction for reg */
761 /* TODO better name */
762 static inline struct ir3_instruction *ssa(struct ir3_register *reg)
763 {
764 if (reg->flags & (IR3_REG_SSA | IR3_REG_ARRAY)) {
765 return reg->instr;
766 }
767 return NULL;
768 }
769
770 static inline bool conflicts(struct ir3_instruction *a,
771 struct ir3_instruction *b)
772 {
773 return (a && b) && (a != b);
774 }
775
776 static inline bool reg_gpr(struct ir3_register *r)
777 {
778 if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED))
779 return false;
780 if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0))
781 return false;
782 return true;
783 }
784
785 static inline type_t half_type(type_t type)
786 {
787 switch (type) {
788 case TYPE_F32: return TYPE_F16;
789 case TYPE_U32: return TYPE_U16;
790 case TYPE_S32: return TYPE_S16;
791 case TYPE_F16:
792 case TYPE_U16:
793 case TYPE_S16:
794 return type;
795 default:
796 assert(0);
797 return ~0;
798 }
799 }
800
801 /* some cat2 instructions (ie. those which are not float) can embed an
802 * immediate:
803 */
804 static inline bool ir3_cat2_int(opc_t opc)
805 {
806 switch (opc) {
807 case OPC_ADD_U:
808 case OPC_ADD_S:
809 case OPC_SUB_U:
810 case OPC_SUB_S:
811 case OPC_CMPS_U:
812 case OPC_CMPS_S:
813 case OPC_MIN_U:
814 case OPC_MIN_S:
815 case OPC_MAX_U:
816 case OPC_MAX_S:
817 case OPC_CMPV_U:
818 case OPC_CMPV_S:
819 case OPC_MUL_U:
820 case OPC_MUL_S:
821 case OPC_MULL_U:
822 case OPC_CLZ_S:
823 case OPC_ABSNEG_S:
824 case OPC_AND_B:
825 case OPC_OR_B:
826 case OPC_NOT_B:
827 case OPC_XOR_B:
828 case OPC_BFREV_B:
829 case OPC_CLZ_B:
830 case OPC_SHL_B:
831 case OPC_SHR_B:
832 case OPC_ASHR_B:
833 case OPC_MGEN_B:
834 case OPC_GETBIT_B:
835 case OPC_CBITS_B:
836 case OPC_BARY_F:
837 return true;
838
839 default:
840 return false;
841 }
842 }
843
844
845 /* map cat2 instruction to valid abs/neg flags: */
846 static inline unsigned ir3_cat2_absneg(opc_t opc)
847 {
848 switch (opc) {
849 case OPC_ADD_F:
850 case OPC_MIN_F:
851 case OPC_MAX_F:
852 case OPC_MUL_F:
853 case OPC_SIGN_F:
854 case OPC_CMPS_F:
855 case OPC_ABSNEG_F:
856 case OPC_CMPV_F:
857 case OPC_FLOOR_F:
858 case OPC_CEIL_F:
859 case OPC_RNDNE_F:
860 case OPC_RNDAZ_F:
861 case OPC_TRUNC_F:
862 case OPC_BARY_F:
863 return IR3_REG_FABS | IR3_REG_FNEG;
864
865 case OPC_ADD_U:
866 case OPC_ADD_S:
867 case OPC_SUB_U:
868 case OPC_SUB_S:
869 case OPC_CMPS_U:
870 case OPC_CMPS_S:
871 case OPC_MIN_U:
872 case OPC_MIN_S:
873 case OPC_MAX_U:
874 case OPC_MAX_S:
875 case OPC_CMPV_U:
876 case OPC_CMPV_S:
877 case OPC_MUL_U:
878 case OPC_MUL_S:
879 case OPC_MULL_U:
880 case OPC_CLZ_S:
881 return 0;
882
883 case OPC_ABSNEG_S:
884 return IR3_REG_SABS | IR3_REG_SNEG;
885
886 case OPC_AND_B:
887 case OPC_OR_B:
888 case OPC_NOT_B:
889 case OPC_XOR_B:
890 case OPC_BFREV_B:
891 case OPC_CLZ_B:
892 case OPC_SHL_B:
893 case OPC_SHR_B:
894 case OPC_ASHR_B:
895 case OPC_MGEN_B:
896 case OPC_GETBIT_B:
897 case OPC_CBITS_B:
898 return IR3_REG_BNOT;
899
900 default:
901 return 0;
902 }
903 }
904
905 /* map cat3 instructions to valid abs/neg flags: */
906 static inline unsigned ir3_cat3_absneg(opc_t opc)
907 {
908 switch (opc) {
909 case OPC_MAD_F16:
910 case OPC_MAD_F32:
911 case OPC_SEL_F16:
912 case OPC_SEL_F32:
913 return IR3_REG_FNEG;
914
915 case OPC_MAD_U16:
916 case OPC_MADSH_U16:
917 case OPC_MAD_S16:
918 case OPC_MADSH_M16:
919 case OPC_MAD_U24:
920 case OPC_MAD_S24:
921 case OPC_SEL_S16:
922 case OPC_SEL_S32:
923 case OPC_SAD_S16:
924 case OPC_SAD_S32:
925 /* neg *may* work on 3rd src.. */
926
927 case OPC_SEL_B16:
928 case OPC_SEL_B32:
929
930 default:
931 return 0;
932 }
933 }
934
935 #define MASK(n) ((1 << (n)) - 1)
936
937 /* iterator for an instructions's sources (reg), also returns src #: */
938 #define foreach_src_n(__srcreg, __n, __instr) \
939 if ((__instr)->regs_count) \
940 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
941 if ((__srcreg = (__instr)->regs[__n + 1]))
942
943 /* iterator for an instructions's sources (reg): */
944 #define foreach_src(__srcreg, __instr) \
945 foreach_src_n(__srcreg, __i, __instr)
946
947 static inline unsigned __ssa_src_cnt(struct ir3_instruction *instr)
948 {
949 unsigned cnt = instr->regs_count + instr->deps_count;
950 if (instr->address)
951 cnt++;
952 return cnt;
953 }
954
955 static inline struct ir3_instruction * __ssa_src_n(struct ir3_instruction *instr, unsigned n)
956 {
957 if (n == (instr->regs_count + instr->deps_count))
958 return instr->address;
959 if (n >= instr->regs_count)
960 return instr->deps[n - instr->regs_count];
961 return ssa(instr->regs[n]);
962 }
963
964 static inline bool __is_false_dep(struct ir3_instruction *instr, unsigned n)
965 {
966 if (n == (instr->regs_count + instr->deps_count))
967 return false;
968 if (n >= instr->regs_count)
969 return true;
970 return false;
971 }
972
973 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
974
975 /* iterator for an instruction's SSA sources (instr), also returns src #: */
976 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
977 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
978 if ((__srcinst = __ssa_src_n(__instr, __n)))
979
980 /* iterator for an instruction's SSA sources (instr): */
981 #define foreach_ssa_src(__srcinst, __instr) \
982 foreach_ssa_src_n(__srcinst, __i, __instr)
983
984
985 /* dump: */
986 void ir3_print(struct ir3 *ir);
987 void ir3_print_instr(struct ir3_instruction *instr);
988
989 /* depth calculation: */
990 int ir3_delayslots(struct ir3_instruction *assigner,
991 struct ir3_instruction *consumer, unsigned n);
992 void ir3_insert_by_depth(struct ir3_instruction *instr, struct list_head *list);
993 void ir3_depth(struct ir3 *ir);
994
995 /* copy-propagate: */
996 struct ir3_shader_variant;
997 void ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so);
998
999 /* group neighbors and insert mov's to resolve conflicts: */
1000 void ir3_group(struct ir3 *ir);
1001
1002 /* scheduling: */
1003 void ir3_sched_add_deps(struct ir3 *ir);
1004 int ir3_sched(struct ir3 *ir);
1005
1006 void ir3_a6xx_fixup_atomic_dests(struct ir3 *ir, struct ir3_shader_variant *so);
1007
1008 /* register assignment: */
1009 struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler);
1010 int ir3_ra(struct ir3 *ir3, gl_shader_stage type,
1011 bool frag_coord, bool frag_face);
1012
1013 /* legalize: */
1014 void ir3_legalize(struct ir3 *ir, int *num_samp, bool *has_ssbo, int *max_bary);
1015
1016 /* ************************************************************************* */
1017 /* instruction helpers */
1018
1019 static inline struct ir3_instruction *
1020 create_immed_typed(struct ir3_block *block, uint32_t val, type_t type)
1021 {
1022 struct ir3_instruction *mov;
1023 unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0;
1024
1025 mov = ir3_instr_create(block, OPC_MOV);
1026 mov->cat1.src_type = type;
1027 mov->cat1.dst_type = type;
1028 ir3_reg_create(mov, 0, flags);
1029 ir3_reg_create(mov, 0, IR3_REG_IMMED)->uim_val = val;
1030
1031 return mov;
1032 }
1033
1034 static inline struct ir3_instruction *
1035 create_immed(struct ir3_block *block, uint32_t val)
1036 {
1037 return create_immed_typed(block, val, TYPE_U32);
1038 }
1039
1040 static inline struct ir3_instruction *
1041 create_uniform(struct ir3_block *block, unsigned n)
1042 {
1043 struct ir3_instruction *mov;
1044
1045 mov = ir3_instr_create(block, OPC_MOV);
1046 /* TODO get types right? */
1047 mov->cat1.src_type = TYPE_F32;
1048 mov->cat1.dst_type = TYPE_F32;
1049 ir3_reg_create(mov, 0, 0);
1050 ir3_reg_create(mov, n, IR3_REG_CONST);
1051
1052 return mov;
1053 }
1054
1055 static inline struct ir3_instruction *
1056 create_uniform_indirect(struct ir3_block *block, int n,
1057 struct ir3_instruction *address)
1058 {
1059 struct ir3_instruction *mov;
1060
1061 mov = ir3_instr_create(block, OPC_MOV);
1062 mov->cat1.src_type = TYPE_U32;
1063 mov->cat1.dst_type = TYPE_U32;
1064 ir3_reg_create(mov, 0, 0);
1065 ir3_reg_create(mov, 0, IR3_REG_CONST | IR3_REG_RELATIV)->array.offset = n;
1066
1067 ir3_instr_set_address(mov, address);
1068
1069 return mov;
1070 }
1071
1072 /* creates SSA src of correct type (ie. half vs full precision) */
1073 static inline struct ir3_register * __ssa_src(struct ir3_instruction *instr,
1074 struct ir3_instruction *src, unsigned flags)
1075 {
1076 struct ir3_register *reg;
1077 if (src->regs[0]->flags & IR3_REG_HALF)
1078 flags |= IR3_REG_HALF;
1079 reg = ir3_reg_create(instr, 0, IR3_REG_SSA | flags);
1080 reg->instr = src;
1081 reg->wrmask = src->regs[0]->wrmask;
1082 return reg;
1083 }
1084
1085 static inline struct ir3_instruction *
1086 ir3_MOV(struct ir3_block *block, struct ir3_instruction *src, type_t type)
1087 {
1088 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1089 ir3_reg_create(instr, 0, 0); /* dst */
1090 if (src->regs[0]->flags & IR3_REG_ARRAY) {
1091 struct ir3_register *src_reg = __ssa_src(instr, src, IR3_REG_ARRAY);
1092 src_reg->array = src->regs[0]->array;
1093 } else {
1094 __ssa_src(instr, src, src->regs[0]->flags & IR3_REG_HIGH);
1095 }
1096 debug_assert(!(src->regs[0]->flags & IR3_REG_RELATIV));
1097 instr->cat1.src_type = type;
1098 instr->cat1.dst_type = type;
1099 return instr;
1100 }
1101
1102 static inline struct ir3_instruction *
1103 ir3_COV(struct ir3_block *block, struct ir3_instruction *src,
1104 type_t src_type, type_t dst_type)
1105 {
1106 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1107 unsigned dst_flags = (type_size(dst_type) < 32) ? IR3_REG_HALF : 0;
1108 unsigned src_flags = (type_size(src_type) < 32) ? IR3_REG_HALF : 0;
1109
1110 debug_assert((src->regs[0]->flags & IR3_REG_HALF) == src_flags);
1111
1112 ir3_reg_create(instr, 0, dst_flags); /* dst */
1113 __ssa_src(instr, src, 0);
1114 instr->cat1.src_type = src_type;
1115 instr->cat1.dst_type = dst_type;
1116 debug_assert(!(src->regs[0]->flags & IR3_REG_ARRAY));
1117 return instr;
1118 }
1119
1120 static inline struct ir3_instruction *
1121 ir3_NOP(struct ir3_block *block)
1122 {
1123 return ir3_instr_create(block, OPC_NOP);
1124 }
1125
1126 #define INSTR0(name) \
1127 static inline struct ir3_instruction * \
1128 ir3_##name(struct ir3_block *block) \
1129 { \
1130 struct ir3_instruction *instr = \
1131 ir3_instr_create(block, OPC_##name); \
1132 return instr; \
1133 }
1134
1135 #define INSTR1(name) \
1136 static inline struct ir3_instruction * \
1137 ir3_##name(struct ir3_block *block, \
1138 struct ir3_instruction *a, unsigned aflags) \
1139 { \
1140 struct ir3_instruction *instr = \
1141 ir3_instr_create(block, OPC_##name); \
1142 ir3_reg_create(instr, 0, 0); /* dst */ \
1143 __ssa_src(instr, a, aflags); \
1144 return instr; \
1145 }
1146
1147 #define INSTR2(name) \
1148 static inline struct ir3_instruction * \
1149 ir3_##name(struct ir3_block *block, \
1150 struct ir3_instruction *a, unsigned aflags, \
1151 struct ir3_instruction *b, unsigned bflags) \
1152 { \
1153 struct ir3_instruction *instr = \
1154 ir3_instr_create(block, OPC_##name); \
1155 ir3_reg_create(instr, 0, 0); /* dst */ \
1156 __ssa_src(instr, a, aflags); \
1157 __ssa_src(instr, b, bflags); \
1158 return instr; \
1159 }
1160
1161 #define INSTR3(name) \
1162 static inline struct ir3_instruction * \
1163 ir3_##name(struct ir3_block *block, \
1164 struct ir3_instruction *a, unsigned aflags, \
1165 struct ir3_instruction *b, unsigned bflags, \
1166 struct ir3_instruction *c, unsigned cflags) \
1167 { \
1168 struct ir3_instruction *instr = \
1169 ir3_instr_create(block, OPC_##name); \
1170 ir3_reg_create(instr, 0, 0); /* dst */ \
1171 __ssa_src(instr, a, aflags); \
1172 __ssa_src(instr, b, bflags); \
1173 __ssa_src(instr, c, cflags); \
1174 return instr; \
1175 }
1176
1177 #define INSTR3F(f, name) \
1178 static inline struct ir3_instruction * \
1179 ir3_##name##_##f(struct ir3_block *block, \
1180 struct ir3_instruction *a, unsigned aflags, \
1181 struct ir3_instruction *b, unsigned bflags, \
1182 struct ir3_instruction *c, unsigned cflags) \
1183 { \
1184 struct ir3_instruction *instr = \
1185 ir3_instr_create2(block, OPC_##name, 5); \
1186 ir3_reg_create(instr, 0, 0); /* dst */ \
1187 __ssa_src(instr, a, aflags); \
1188 __ssa_src(instr, b, bflags); \
1189 __ssa_src(instr, c, cflags); \
1190 instr->flags |= IR3_INSTR_##f; \
1191 return instr; \
1192 }
1193
1194 #define INSTR4(name) \
1195 static inline struct ir3_instruction * \
1196 ir3_##name(struct ir3_block *block, \
1197 struct ir3_instruction *a, unsigned aflags, \
1198 struct ir3_instruction *b, unsigned bflags, \
1199 struct ir3_instruction *c, unsigned cflags, \
1200 struct ir3_instruction *d, unsigned dflags) \
1201 { \
1202 struct ir3_instruction *instr = \
1203 ir3_instr_create2(block, OPC_##name, 5); \
1204 ir3_reg_create(instr, 0, 0); /* dst */ \
1205 __ssa_src(instr, a, aflags); \
1206 __ssa_src(instr, b, bflags); \
1207 __ssa_src(instr, c, cflags); \
1208 __ssa_src(instr, d, dflags); \
1209 return instr; \
1210 }
1211
1212 #define INSTR4F(f, name) \
1213 static inline struct ir3_instruction * \
1214 ir3_##name##_##f(struct ir3_block *block, \
1215 struct ir3_instruction *a, unsigned aflags, \
1216 struct ir3_instruction *b, unsigned bflags, \
1217 struct ir3_instruction *c, unsigned cflags, \
1218 struct ir3_instruction *d, unsigned dflags) \
1219 { \
1220 struct ir3_instruction *instr = \
1221 ir3_instr_create2(block, OPC_##name, 5); \
1222 ir3_reg_create(instr, 0, 0); /* dst */ \
1223 __ssa_src(instr, a, aflags); \
1224 __ssa_src(instr, b, bflags); \
1225 __ssa_src(instr, c, cflags); \
1226 __ssa_src(instr, d, dflags); \
1227 instr->flags |= IR3_INSTR_##f; \
1228 return instr; \
1229 }
1230
1231 /* cat0 instructions: */
1232 INSTR0(BR)
1233 INSTR0(JUMP)
1234 INSTR1(KILL)
1235 INSTR0(END)
1236
1237 /* cat2 instructions, most 2 src but some 1 src: */
1238 INSTR2(ADD_F)
1239 INSTR2(MIN_F)
1240 INSTR2(MAX_F)
1241 INSTR2(MUL_F)
1242 INSTR1(SIGN_F)
1243 INSTR2(CMPS_F)
1244 INSTR1(ABSNEG_F)
1245 INSTR2(CMPV_F)
1246 INSTR1(FLOOR_F)
1247 INSTR1(CEIL_F)
1248 INSTR1(RNDNE_F)
1249 INSTR1(RNDAZ_F)
1250 INSTR1(TRUNC_F)
1251 INSTR2(ADD_U)
1252 INSTR2(ADD_S)
1253 INSTR2(SUB_U)
1254 INSTR2(SUB_S)
1255 INSTR2(CMPS_U)
1256 INSTR2(CMPS_S)
1257 INSTR2(MIN_U)
1258 INSTR2(MIN_S)
1259 INSTR2(MAX_U)
1260 INSTR2(MAX_S)
1261 INSTR1(ABSNEG_S)
1262 INSTR2(AND_B)
1263 INSTR2(OR_B)
1264 INSTR1(NOT_B)
1265 INSTR2(XOR_B)
1266 INSTR2(CMPV_U)
1267 INSTR2(CMPV_S)
1268 INSTR2(MUL_U)
1269 INSTR2(MUL_S)
1270 INSTR2(MULL_U)
1271 INSTR1(BFREV_B)
1272 INSTR1(CLZ_S)
1273 INSTR1(CLZ_B)
1274 INSTR2(SHL_B)
1275 INSTR2(SHR_B)
1276 INSTR2(ASHR_B)
1277 INSTR2(BARY_F)
1278 INSTR2(MGEN_B)
1279 INSTR2(GETBIT_B)
1280 INSTR1(SETRM)
1281 INSTR1(CBITS_B)
1282 INSTR2(SHB)
1283 INSTR2(MSAD)
1284
1285 /* cat3 instructions: */
1286 INSTR3(MAD_U16)
1287 INSTR3(MADSH_U16)
1288 INSTR3(MAD_S16)
1289 INSTR3(MADSH_M16)
1290 INSTR3(MAD_U24)
1291 INSTR3(MAD_S24)
1292 INSTR3(MAD_F16)
1293 INSTR3(MAD_F32)
1294 INSTR3(SEL_B16)
1295 INSTR3(SEL_B32)
1296 INSTR3(SEL_S16)
1297 INSTR3(SEL_S32)
1298 INSTR3(SEL_F16)
1299 INSTR3(SEL_F32)
1300 INSTR3(SAD_S16)
1301 INSTR3(SAD_S32)
1302
1303 /* cat4 instructions: */
1304 INSTR1(RCP)
1305 INSTR1(RSQ)
1306 INSTR1(LOG2)
1307 INSTR1(EXP2)
1308 INSTR1(SIN)
1309 INSTR1(COS)
1310 INSTR1(SQRT)
1311
1312 /* cat5 instructions: */
1313 INSTR1(DSX)
1314 INSTR1(DSY)
1315
1316 static inline struct ir3_instruction *
1317 ir3_SAM(struct ir3_block *block, opc_t opc, type_t type,
1318 unsigned wrmask, unsigned flags, unsigned samp, unsigned tex,
1319 struct ir3_instruction *src0, struct ir3_instruction *src1)
1320 {
1321 struct ir3_instruction *sam;
1322 struct ir3_register *reg;
1323
1324 sam = ir3_instr_create(block, opc);
1325 sam->flags |= flags;
1326 ir3_reg_create(sam, 0, 0)->wrmask = wrmask;
1327 if (src0) {
1328 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
1329 reg->wrmask = (1 << (src0->regs_count - 1)) - 1;
1330 reg->instr = src0;
1331 }
1332 if (src1) {
1333 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
1334 reg->instr = src1;
1335 reg->wrmask = (1 << (src1->regs_count - 1)) - 1;
1336 }
1337 sam->cat5.samp = samp;
1338 sam->cat5.tex = tex;
1339 sam->cat5.type = type;
1340
1341 return sam;
1342 }
1343
1344 /* cat6 instructions: */
1345 INSTR2(LDLV)
1346 INSTR2(LDG)
1347 INSTR2(LDL)
1348 INSTR3(STG)
1349 INSTR3(STL)
1350 INSTR1(RESINFO)
1351 INSTR1(RESFMT)
1352 INSTR2(ATOMIC_ADD)
1353 INSTR2(ATOMIC_SUB)
1354 INSTR2(ATOMIC_XCHG)
1355 INSTR2(ATOMIC_INC)
1356 INSTR2(ATOMIC_DEC)
1357 INSTR2(ATOMIC_CMPXCHG)
1358 INSTR2(ATOMIC_MIN)
1359 INSTR2(ATOMIC_MAX)
1360 INSTR2(ATOMIC_AND)
1361 INSTR2(ATOMIC_OR)
1362 INSTR2(ATOMIC_XOR)
1363 #if GPU >= 600
1364 INSTR3(STIB);
1365 INSTR2(LDIB);
1366 INSTR3F(G, ATOMIC_ADD)
1367 INSTR3F(G, ATOMIC_SUB)
1368 INSTR3F(G, ATOMIC_XCHG)
1369 INSTR3F(G, ATOMIC_INC)
1370 INSTR3F(G, ATOMIC_DEC)
1371 INSTR3F(G, ATOMIC_CMPXCHG)
1372 INSTR3F(G, ATOMIC_MIN)
1373 INSTR3F(G, ATOMIC_MAX)
1374 INSTR3F(G, ATOMIC_AND)
1375 INSTR3F(G, ATOMIC_OR)
1376 INSTR3F(G, ATOMIC_XOR)
1377 #elif GPU >= 400
1378 INSTR3(LDGB)
1379 INSTR4(STGB)
1380 INSTR4(STIB)
1381 INSTR4F(G, ATOMIC_ADD)
1382 INSTR4F(G, ATOMIC_SUB)
1383 INSTR4F(G, ATOMIC_XCHG)
1384 INSTR4F(G, ATOMIC_INC)
1385 INSTR4F(G, ATOMIC_DEC)
1386 INSTR4F(G, ATOMIC_CMPXCHG)
1387 INSTR4F(G, ATOMIC_MIN)
1388 INSTR4F(G, ATOMIC_MAX)
1389 INSTR4F(G, ATOMIC_AND)
1390 INSTR4F(G, ATOMIC_OR)
1391 INSTR4F(G, ATOMIC_XOR)
1392 #endif
1393
1394 /* cat7 instructions: */
1395 INSTR0(BAR)
1396 INSTR0(FENCE)
1397
1398 /* ************************************************************************* */
1399 /* split this out or find some helper to use.. like main/bitset.h.. */
1400
1401 #include <string.h>
1402
1403 #define MAX_REG 256
1404
1405 typedef uint8_t regmask_t[2 * MAX_REG / 8];
1406
1407 static inline unsigned regmask_idx(struct ir3_register *reg)
1408 {
1409 unsigned num = (reg->flags & IR3_REG_RELATIV) ? reg->array.offset : reg->num;
1410 debug_assert(num < MAX_REG);
1411 if (reg->flags & IR3_REG_HALF)
1412 num += MAX_REG;
1413 return num;
1414 }
1415
1416 static inline void regmask_init(regmask_t *regmask)
1417 {
1418 memset(regmask, 0, sizeof(*regmask));
1419 }
1420
1421 static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg)
1422 {
1423 unsigned idx = regmask_idx(reg);
1424 if (reg->flags & IR3_REG_RELATIV) {
1425 unsigned i;
1426 for (i = 0; i < reg->size; i++, idx++)
1427 (*regmask)[idx / 8] |= 1 << (idx % 8);
1428 } else {
1429 unsigned mask;
1430 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1431 if (mask & 1)
1432 (*regmask)[idx / 8] |= 1 << (idx % 8);
1433 }
1434 }
1435
1436 static inline void regmask_or(regmask_t *dst, regmask_t *a, regmask_t *b)
1437 {
1438 unsigned i;
1439 for (i = 0; i < ARRAY_SIZE(*dst); i++)
1440 (*dst)[i] = (*a)[i] | (*b)[i];
1441 }
1442
1443 /* set bits in a if not set in b, conceptually:
1444 * a |= (reg & ~b)
1445 */
1446 static inline void regmask_set_if_not(regmask_t *a,
1447 struct ir3_register *reg, regmask_t *b)
1448 {
1449 unsigned idx = regmask_idx(reg);
1450 if (reg->flags & IR3_REG_RELATIV) {
1451 unsigned i;
1452 for (i = 0; i < reg->size; i++, idx++)
1453 if (!((*b)[idx / 8] & (1 << (idx % 8))))
1454 (*a)[idx / 8] |= 1 << (idx % 8);
1455 } else {
1456 unsigned mask;
1457 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1458 if (mask & 1)
1459 if (!((*b)[idx / 8] & (1 << (idx % 8))))
1460 (*a)[idx / 8] |= 1 << (idx % 8);
1461 }
1462 }
1463
1464 static inline bool regmask_get(regmask_t *regmask,
1465 struct ir3_register *reg)
1466 {
1467 unsigned idx = regmask_idx(reg);
1468 if (reg->flags & IR3_REG_RELATIV) {
1469 unsigned i;
1470 for (i = 0; i < reg->size; i++, idx++)
1471 if ((*regmask)[idx / 8] & (1 << (idx % 8)))
1472 return true;
1473 } else {
1474 unsigned mask;
1475 for (mask = reg->wrmask; mask; mask >>= 1, idx++)
1476 if (mask & 1)
1477 if ((*regmask)[idx / 8] & (1 << (idx % 8)))
1478 return true;
1479 }
1480 return false;
1481 }
1482
1483 /* ************************************************************************* */
1484
1485 #endif /* IR3_H_ */