2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "compiler/shader_enums.h"
32 #include "util/u_debug.h"
33 #include "util/list.h"
35 #include "instr-a3xx.h"
37 /* low level intermediate representation of an adreno shader program */
41 struct ir3_instruction
;
47 uint16_t instrs_count
; /* expanded to account for rpt's */
48 /* NOTE: max_reg, etc, does not include registers not touched
49 * by the shader (ie. vertex fetched via VFD_DECODE but not
52 int8_t max_reg
; /* highest GPR # used by shader */
56 /* number of sync bits: */
62 IR3_REG_CONST
= 0x001,
63 IR3_REG_IMMED
= 0x002,
65 /* high registers are used for some things in compute shaders,
66 * for example. Seems to be for things that are global to all
67 * threads in a wave, so possibly these are global/shared by
68 * all the threads in the wave?
71 IR3_REG_RELATIV
= 0x010,
73 /* Most instructions, it seems, can do float abs/neg but not
74 * integer. The CP pass needs to know what is intended (int or
75 * float) in order to do the right thing. For this reason the
76 * abs/neg flags are split out into float and int variants. In
77 * addition, .b (bitwise) operations, the negate is actually a
78 * bitwise not, so split that out into a new flag to make it
87 IR3_REG_POS_INF
= 0x1000,
88 /* (ei) flag, end-input? Set on last bary, presumably to signal
89 * that the shader needs no more input:
92 /* meta-flags, for intermediate stages of IR, ie.
93 * before register assignment is done:
95 IR3_REG_SSA
= 0x4000, /* 'instr' is ptr to assigning instr */
96 IR3_REG_ARRAY
= 0x8000,
101 * the component is in the low two bits of the reg #, so
102 * rN.x becomes: (N << 2) | x
117 /* For IR3_REG_SSA, src registers contain ptr back to assigning
120 * For IR3_REG_ARRAY, the pointer is back to the last dependent
121 * array access (although the net effect is the same, it points
122 * back to a previous instruction that we depend on).
124 struct ir3_instruction
*instr
;
127 /* used for cat5 instructions, but also for internal/IR level
128 * tracking of what registers are read/written by an instruction.
129 * wrmask may be a bad name since it is used to represent both
130 * src and dst that touch multiple adjacent registers.
133 /* for relative addressing, 32bits for array size is too small,
134 * but otoh we don't need to deal with disjoint sets, so instead
135 * use a simple size field (number of scalar components).
142 * Stupid/simple growable array implementation:
144 #define DECLARE_ARRAY(type, name) \
145 unsigned name ## _count, name ## _sz; \
148 #define array_insert(ctx, arr, val) do { \
149 if (arr ## _count == arr ## _sz) { \
150 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
151 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
153 arr[arr ##_count++] = val; \
156 struct ir3_instruction
{
157 struct ir3_block
*block
;
160 /* (sy) flag is set on first instruction, and after sample
161 * instructions (probably just on RAW hazard).
163 IR3_INSTR_SY
= 0x001,
164 /* (ss) flag is set on first instruction, and first instruction
165 * to depend on the result of "long" instructions (RAW hazard):
167 * rcp, rsq, log2, exp2, sin, cos, sqrt
169 * It seems to synchronize until all in-flight instructions are
170 * completed, for example:
173 * add.f hr2.z, (neg)hr2.z, hc0.y
174 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
177 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
179 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
180 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
181 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
183 * The last mul.f does not have (ss) set, presumably because the
184 * (ss) on the previous instruction does the job.
186 * The blob driver also seems to set it on WAR hazards, although
187 * not really clear if this is needed or just blob compiler being
188 * sloppy. So far I haven't found a case where removing the (ss)
189 * causes problems for WAR hazard, but I could just be getting
193 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
196 IR3_INSTR_SS
= 0x002,
197 /* (jp) flag is set on jump targets:
199 IR3_INSTR_JP
= 0x004,
200 IR3_INSTR_UL
= 0x008,
201 IR3_INSTR_3D
= 0x010,
206 IR3_INSTR_S2EN
= 0x200,
208 IR3_INSTR_SAT
= 0x800,
209 /* meta-flags, for intermediate stages of IR, ie.
210 * before register assignment is done:
212 IR3_INSTR_MARK
= 0x1000,
213 IR3_INSTR_UNUSED
= 0x2000,
220 struct ir3_register
**regs
;
226 struct ir3_block
*target
;
229 type_t src_type
, dst_type
;
249 int iim_val
: 3; /* for ldgb/stgb, # of components */
254 unsigned w
: 1; /* write */
255 unsigned r
: 1; /* read */
256 unsigned l
: 1; /* local */
257 unsigned g
: 1; /* global */
259 /* for meta-instructions, just used to hold extra data
260 * before instruction scheduling, etc
263 int off
; /* component/offset */
266 struct ir3_block
*block
;
270 /* transient values used during various algorithms: */
272 /* The instruction depth is the max dependency distance to output.
274 * You can also think of it as the "cost", if we did any sort of
275 * optimization for register footprint. Ie. a value that is just
276 * result of moving a const to a reg would have a low cost, so to
277 * it could make sense to duplicate the instruction at various
278 * points where the result is needed to reduce register footprint.
281 /* When we get to the RA stage, we no longer need depth, but
282 * we do need instruction's position/name:
290 /* used for per-pass extra instruction data.
294 /* Used during CP and RA stages. For fanin and shader inputs/
295 * outputs where we need a sequence of consecutive registers,
296 * keep track of each src instructions left (ie 'n-1') and right
297 * (ie 'n+1') neighbor. The front-end must insert enough mov's
298 * to ensure that each instruction has at most one left and at
299 * most one right neighbor. During the copy-propagation pass,
300 * we only remove mov's when we can preserve this constraint.
301 * And during the RA stage, we use the neighbor information to
302 * allocate a block of registers in one shot.
304 * TODO: maybe just add something like:
305 * struct ir3_instruction_ref {
306 * struct ir3_instruction *instr;
310 * Or can we get away without the refcnt stuff? It seems like
311 * it should be overkill.. the problem is if, potentially after
312 * already eliminating some mov's, if you have a single mov that
313 * needs to be grouped with it's neighbors in two different
314 * places (ex. shader output and a fanin).
317 struct ir3_instruction
*left
, *right
;
318 uint16_t left_cnt
, right_cnt
;
321 /* an instruction can reference at most one address register amongst
322 * it's src/dst registers. Beyond that, you need to insert mov's.
324 * NOTE: do not write this directly, use ir3_instr_set_address()
326 struct ir3_instruction
*address
;
328 /* Tracking for additional dependent instructions. Used to handle
329 * barriers, WAR hazards for arrays/SSBOs/etc.
331 DECLARE_ARRAY(struct ir3_instruction
*, deps
);
334 * From PoV of instruction scheduling, not execution (ie. ignores global/
335 * local distinction):
336 * shared image atomic SSBO everything
337 * barrier()/ - R/W R/W R/W R/W X
338 * groupMemoryBarrier()
339 * memoryBarrier() - R/W R/W
340 * (but only images declared coherent?)
341 * memoryBarrierAtomic() - R/W
342 * memoryBarrierBuffer() - R/W
343 * memoryBarrierImage() - R/W
344 * memoryBarrierShared() - R/W
346 * TODO I think for SSBO/image/shared, in cases where we can determine
347 * which variable is accessed, we don't need to care about accesses to
348 * different variables (unless declared coherent??)
351 IR3_BARRIER_EVERYTHING
= 1 << 0,
352 IR3_BARRIER_SHARED_R
= 1 << 1,
353 IR3_BARRIER_SHARED_W
= 1 << 2,
354 IR3_BARRIER_IMAGE_R
= 1 << 3,
355 IR3_BARRIER_IMAGE_W
= 1 << 4,
356 IR3_BARRIER_BUFFER_R
= 1 << 5,
357 IR3_BARRIER_BUFFER_W
= 1 << 6,
358 IR3_BARRIER_ARRAY_R
= 1 << 7,
359 IR3_BARRIER_ARRAY_W
= 1 << 8,
360 } barrier_class
, barrier_conflict
;
362 /* Entry in ir3_block's instruction list: */
363 struct list_head node
;
365 int use_count
; /* currently just updated/used by cp */
372 static inline struct ir3_instruction
*
373 ir3_neighbor_first(struct ir3_instruction
*instr
)
376 while (instr
->cp
.left
) {
377 instr
= instr
->cp
.left
;
378 if (++cnt
> 0xffff) {
386 static inline int ir3_neighbor_count(struct ir3_instruction
*instr
)
390 debug_assert(!instr
->cp
.left
);
392 while (instr
->cp
.right
) {
394 instr
= instr
->cp
.right
;
405 struct ir3_compiler
*compiler
;
407 unsigned ninputs
, noutputs
;
408 struct ir3_instruction
**inputs
;
409 struct ir3_instruction
**outputs
;
411 /* Track bary.f (and ldlv) instructions.. this is needed in
412 * scheduling to ensure that all varying fetches happen before
413 * any potential kill instructions. The hw gets grumpy if all
414 * threads in a group are killed before the last bary.f gets
415 * a chance to signal end of input (ei).
417 DECLARE_ARRAY(struct ir3_instruction
*, baryfs
);
419 /* Track all indirect instructions (read and write). To avoid
420 * deadlock scenario where an address register gets scheduled,
421 * but other dependent src instructions cannot be scheduled due
422 * to dependency on a *different* address register value, the
423 * scheduler needs to ensure that all dependencies other than
424 * the instruction other than the address register are scheduled
425 * before the one that writes the address register. Having a
426 * convenient list of instructions that reference some address
427 * register simplifies this.
429 DECLARE_ARRAY(struct ir3_instruction
*, indirects
);
431 /* and same for instructions that consume predicate register: */
432 DECLARE_ARRAY(struct ir3_instruction
*, predicates
);
434 /* Track texture sample instructions which need texture state
435 * patched in (for astc-srgb workaround):
437 DECLARE_ARRAY(struct ir3_instruction
*, astc_srgb
);
439 /* List of blocks: */
440 struct list_head block_list
;
442 /* List of ir3_array's: */
443 struct list_head array_list
;
446 unsigned block_count
, instr_count
;
451 struct list_head node
;
455 struct nir_register
*r
;
457 /* To avoid array write's from getting DCE'd, keep track of the
458 * most recent write. Any array access depends on the most
459 * recent write. This way, nothing depends on writes after the
460 * last read. But all the writes that happen before that have
461 * something depending on them
463 struct ir3_instruction
*last_write
;
465 /* extra stuff used in RA pass: */
466 unsigned base
; /* base vreg name */
467 unsigned reg
; /* base physical reg */
468 uint16_t start_ip
, end_ip
;
471 struct ir3_array
* ir3_lookup_array(struct ir3
*ir
, unsigned id
);
474 struct list_head node
;
477 const struct nir_block
*nblock
;
479 struct list_head instr_list
; /* list of ir3_instruction */
481 /* each block has either one or two successors.. in case of
482 * two successors, 'condition' decides which one to follow.
483 * A block preceding an if/else has two successors.
485 struct ir3_instruction
*condition
;
486 struct ir3_block
*successors
[2];
488 unsigned predecessors_count
;
489 struct ir3_block
**predecessors
;
491 uint16_t start_ip
, end_ip
;
493 /* Track instructions which do not write a register but other-
494 * wise must not be discarded (such as kill, stg, etc)
496 DECLARE_ARRAY(struct ir3_instruction
*, keeps
);
498 /* used for per-pass extra block data. Mainly used right
499 * now in RA step to track livein/liveout.
508 static inline uint32_t
509 block_id(struct ir3_block
*block
)
512 return block
->serialno
;
514 return (uint32_t)(unsigned long)block
;
518 struct ir3
* ir3_create(struct ir3_compiler
*compiler
,
519 unsigned nin
, unsigned nout
);
520 void ir3_destroy(struct ir3
*shader
);
521 void * ir3_assemble(struct ir3
*shader
,
522 struct ir3_info
*info
, uint32_t gpu_id
);
523 void * ir3_alloc(struct ir3
*shader
, int sz
);
525 struct ir3_block
* ir3_block_create(struct ir3
*shader
);
527 struct ir3_instruction
* ir3_instr_create(struct ir3_block
*block
, opc_t opc
);
528 struct ir3_instruction
* ir3_instr_create2(struct ir3_block
*block
,
529 opc_t opc
, int nreg
);
530 struct ir3_instruction
* ir3_instr_clone(struct ir3_instruction
*instr
);
531 void ir3_instr_add_dep(struct ir3_instruction
*instr
, struct ir3_instruction
*dep
);
532 const char *ir3_instr_name(struct ir3_instruction
*instr
);
534 struct ir3_register
* ir3_reg_create(struct ir3_instruction
*instr
,
536 struct ir3_register
* ir3_reg_clone(struct ir3
*shader
,
537 struct ir3_register
*reg
);
539 void ir3_instr_set_address(struct ir3_instruction
*instr
,
540 struct ir3_instruction
*addr
);
542 static inline bool ir3_instr_check_mark(struct ir3_instruction
*instr
)
544 if (instr
->flags
& IR3_INSTR_MARK
)
545 return true; /* already visited */
546 instr
->flags
|= IR3_INSTR_MARK
;
550 void ir3_block_clear_mark(struct ir3_block
*block
);
551 void ir3_clear_mark(struct ir3
*shader
);
553 unsigned ir3_count_instructions(struct ir3
*ir
);
555 static inline int ir3_instr_regno(struct ir3_instruction
*instr
,
556 struct ir3_register
*reg
)
559 for (i
= 0; i
< instr
->regs_count
; i
++)
560 if (reg
== instr
->regs
[i
])
566 #define MAX_ARRAYS 16
574 static inline uint32_t regid(int num
, int comp
)
576 return (num
<< 2) | (comp
& 0x3);
579 static inline uint32_t reg_num(struct ir3_register
*reg
)
581 return reg
->num
>> 2;
584 static inline uint32_t reg_comp(struct ir3_register
*reg
)
586 return reg
->num
& 0x3;
589 static inline bool is_flow(struct ir3_instruction
*instr
)
591 return (opc_cat(instr
->opc
) == 0);
594 static inline bool is_kill(struct ir3_instruction
*instr
)
596 return instr
->opc
== OPC_KILL
;
599 static inline bool is_nop(struct ir3_instruction
*instr
)
601 return instr
->opc
== OPC_NOP
;
604 /* Is it a non-transformative (ie. not type changing) mov? This can
605 * also include absneg.s/absneg.f, which for the most part can be
606 * treated as a mov (single src argument).
608 static inline bool is_same_type_mov(struct ir3_instruction
*instr
)
610 struct ir3_register
*dst
;
612 switch (instr
->opc
) {
614 if (instr
->cat1
.src_type
!= instr
->cat1
.dst_type
)
619 if (instr
->flags
& IR3_INSTR_SAT
)
626 dst
= instr
->regs
[0];
628 /* mov's that write to a0.x or p0.x are special: */
629 if (dst
->num
== regid(REG_P0
, 0))
631 if (dst
->num
== regid(REG_A0
, 0))
634 if (dst
->flags
& (IR3_REG_RELATIV
| IR3_REG_ARRAY
))
640 static inline bool is_alu(struct ir3_instruction
*instr
)
642 return (1 <= opc_cat(instr
->opc
)) && (opc_cat(instr
->opc
) <= 3);
645 static inline bool is_sfu(struct ir3_instruction
*instr
)
647 return (opc_cat(instr
->opc
) == 4);
650 static inline bool is_tex(struct ir3_instruction
*instr
)
652 return (opc_cat(instr
->opc
) == 5);
655 static inline bool is_mem(struct ir3_instruction
*instr
)
657 return (opc_cat(instr
->opc
) == 6);
660 static inline bool is_barrier(struct ir3_instruction
*instr
)
662 return (opc_cat(instr
->opc
) == 7);
666 is_store(struct ir3_instruction
*instr
)
668 /* these instructions, the "destination" register is
669 * actually a source, the address to store to.
671 switch (instr
->opc
) {
686 static inline bool is_load(struct ir3_instruction
*instr
)
688 switch (instr
->opc
) {
697 /* probably some others too.. */
704 static inline bool is_input(struct ir3_instruction
*instr
)
706 /* in some cases, ldlv is used to fetch varying without
707 * interpolation.. fortunately inloc is the first src
708 * register in either case
710 switch (instr
->opc
) {
719 static inline bool is_bool(struct ir3_instruction
*instr
)
721 switch (instr
->opc
) {
731 static inline bool is_meta(struct ir3_instruction
*instr
)
733 /* TODO how should we count PHI (and maybe fan-in/out) which
734 * might actually contribute some instructions to the final
737 return (opc_cat(instr
->opc
) == -1);
740 static inline bool writes_addr(struct ir3_instruction
*instr
)
742 if (instr
->regs_count
> 0) {
743 struct ir3_register
*dst
= instr
->regs
[0];
744 return reg_num(dst
) == REG_A0
;
749 static inline bool writes_pred(struct ir3_instruction
*instr
)
751 if (instr
->regs_count
> 0) {
752 struct ir3_register
*dst
= instr
->regs
[0];
753 return reg_num(dst
) == REG_P0
;
758 /* returns defining instruction for reg */
759 /* TODO better name */
760 static inline struct ir3_instruction
*ssa(struct ir3_register
*reg
)
762 if (reg
->flags
& (IR3_REG_SSA
| IR3_REG_ARRAY
)) {
768 static inline bool conflicts(struct ir3_instruction
*a
,
769 struct ir3_instruction
*b
)
771 return (a
&& b
) && (a
!= b
);
774 static inline bool reg_gpr(struct ir3_register
*r
)
776 if (r
->flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
778 if ((reg_num(r
) == REG_A0
) || (reg_num(r
) == REG_P0
))
783 static inline type_t
half_type(type_t type
)
786 case TYPE_F32
: return TYPE_F16
;
787 case TYPE_U32
: return TYPE_U16
;
788 case TYPE_S32
: return TYPE_S16
;
799 /* some cat2 instructions (ie. those which are not float) can embed an
802 static inline bool ir3_cat2_int(opc_t opc
)
843 /* map cat2 instruction to valid abs/neg flags: */
844 static inline unsigned ir3_cat2_absneg(opc_t opc
)
861 return IR3_REG_FABS
| IR3_REG_FNEG
;
882 return IR3_REG_SABS
| IR3_REG_SNEG
;
903 /* map cat3 instructions to valid abs/neg flags: */
904 static inline unsigned ir3_cat3_absneg(opc_t opc
)
923 /* neg *may* work on 3rd src.. */
933 #define MASK(n) ((1 << (n)) - 1)
935 /* iterator for an instructions's sources (reg), also returns src #: */
936 #define foreach_src_n(__srcreg, __n, __instr) \
937 if ((__instr)->regs_count) \
938 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
939 if ((__srcreg = (__instr)->regs[__n + 1]))
941 /* iterator for an instructions's sources (reg): */
942 #define foreach_src(__srcreg, __instr) \
943 foreach_src_n(__srcreg, __i, __instr)
945 static inline unsigned __ssa_src_cnt(struct ir3_instruction
*instr
)
947 unsigned cnt
= instr
->regs_count
+ instr
->deps_count
;
953 static inline struct ir3_instruction
* __ssa_src_n(struct ir3_instruction
*instr
, unsigned n
)
955 if (n
== (instr
->regs_count
+ instr
->deps_count
))
956 return instr
->address
;
957 if (n
>= instr
->regs_count
)
958 return instr
->deps
[n
- instr
->regs_count
];
959 return ssa(instr
->regs
[n
]);
962 static inline bool __is_false_dep(struct ir3_instruction
*instr
, unsigned n
)
964 if (n
== (instr
->regs_count
+ instr
->deps_count
))
966 if (n
>= instr
->regs_count
)
971 #define __src_cnt(__instr) ((__instr)->address ? (__instr)->regs_count : (__instr)->regs_count - 1)
973 /* iterator for an instruction's SSA sources (instr), also returns src #: */
974 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
975 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
976 if ((__srcinst = __ssa_src_n(__instr, __n)))
978 /* iterator for an instruction's SSA sources (instr): */
979 #define foreach_ssa_src(__srcinst, __instr) \
980 foreach_ssa_src_n(__srcinst, __i, __instr)
984 void ir3_print(struct ir3
*ir
);
985 void ir3_print_instr(struct ir3_instruction
*instr
);
987 /* depth calculation: */
988 int ir3_delayslots(struct ir3_instruction
*assigner
,
989 struct ir3_instruction
*consumer
, unsigned n
);
990 void ir3_insert_by_depth(struct ir3_instruction
*instr
, struct list_head
*list
);
991 void ir3_depth(struct ir3
*ir
);
993 /* copy-propagate: */
994 struct ir3_shader_variant
;
995 void ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
);
997 /* group neighbors and insert mov's to resolve conflicts: */
998 void ir3_group(struct ir3
*ir
);
1001 void ir3_sched_add_deps(struct ir3
*ir
);
1002 int ir3_sched(struct ir3
*ir
);
1004 void ir3_a6xx_fixup_atomic_dests(struct ir3
*ir
, struct ir3_shader_variant
*so
);
1006 /* register assignment: */
1007 struct ir3_ra_reg_set
* ir3_ra_alloc_reg_set(struct ir3_compiler
*compiler
);
1008 int ir3_ra(struct ir3
*ir3
, gl_shader_stage type
,
1009 bool frag_coord
, bool frag_face
);
1012 void ir3_legalize(struct ir3
*ir
, int *num_samp
, bool *has_ssbo
, int *max_bary
);
1014 /* ************************************************************************* */
1015 /* instruction helpers */
1017 static inline struct ir3_instruction
*
1018 create_immed_typed(struct ir3_block
*block
, uint32_t val
, type_t type
)
1020 struct ir3_instruction
*mov
;
1021 unsigned flags
= (type_size(type
) < 32) ? IR3_REG_HALF
: 0;
1023 mov
= ir3_instr_create(block
, OPC_MOV
);
1024 mov
->cat1
.src_type
= type
;
1025 mov
->cat1
.dst_type
= type
;
1026 ir3_reg_create(mov
, 0, flags
);
1027 ir3_reg_create(mov
, 0, IR3_REG_IMMED
)->uim_val
= val
;
1032 static inline struct ir3_instruction
*
1033 create_immed(struct ir3_block
*block
, uint32_t val
)
1035 return create_immed_typed(block
, val
, TYPE_U32
);
1038 static inline struct ir3_instruction
*
1039 create_uniform(struct ir3_block
*block
, unsigned n
)
1041 struct ir3_instruction
*mov
;
1043 mov
= ir3_instr_create(block
, OPC_MOV
);
1044 /* TODO get types right? */
1045 mov
->cat1
.src_type
= TYPE_F32
;
1046 mov
->cat1
.dst_type
= TYPE_F32
;
1047 ir3_reg_create(mov
, 0, 0);
1048 ir3_reg_create(mov
, n
, IR3_REG_CONST
);
1053 static inline struct ir3_instruction
*
1054 create_uniform_indirect(struct ir3_block
*block
, int n
,
1055 struct ir3_instruction
*address
)
1057 struct ir3_instruction
*mov
;
1059 mov
= ir3_instr_create(block
, OPC_MOV
);
1060 mov
->cat1
.src_type
= TYPE_U32
;
1061 mov
->cat1
.dst_type
= TYPE_U32
;
1062 ir3_reg_create(mov
, 0, 0);
1063 ir3_reg_create(mov
, 0, IR3_REG_CONST
| IR3_REG_RELATIV
)->array
.offset
= n
;
1065 ir3_instr_set_address(mov
, address
);
1070 /* creates SSA src of correct type (ie. half vs full precision) */
1071 static inline struct ir3_register
* __ssa_src(struct ir3_instruction
*instr
,
1072 struct ir3_instruction
*src
, unsigned flags
)
1074 struct ir3_register
*reg
;
1075 if (src
->regs
[0]->flags
& IR3_REG_HALF
)
1076 flags
|= IR3_REG_HALF
;
1077 reg
= ir3_reg_create(instr
, 0, IR3_REG_SSA
| flags
);
1079 reg
->wrmask
= src
->regs
[0]->wrmask
;
1083 static inline struct ir3_instruction
*
1084 ir3_MOV(struct ir3_block
*block
, struct ir3_instruction
*src
, type_t type
)
1086 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1087 ir3_reg_create(instr
, 0, 0); /* dst */
1088 if (src
->regs
[0]->flags
& IR3_REG_ARRAY
) {
1089 struct ir3_register
*src_reg
= __ssa_src(instr
, src
, IR3_REG_ARRAY
);
1090 src_reg
->array
= src
->regs
[0]->array
;
1092 __ssa_src(instr
, src
, src
->regs
[0]->flags
& IR3_REG_HIGH
);
1094 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_RELATIV
));
1095 instr
->cat1
.src_type
= type
;
1096 instr
->cat1
.dst_type
= type
;
1100 static inline struct ir3_instruction
*
1101 ir3_COV(struct ir3_block
*block
, struct ir3_instruction
*src
,
1102 type_t src_type
, type_t dst_type
)
1104 struct ir3_instruction
*instr
= ir3_instr_create(block
, OPC_MOV
);
1105 unsigned dst_flags
= (type_size(dst_type
) < 32) ? IR3_REG_HALF
: 0;
1106 unsigned src_flags
= (type_size(src_type
) < 32) ? IR3_REG_HALF
: 0;
1108 debug_assert((src
->regs
[0]->flags
& IR3_REG_HALF
) == src_flags
);
1110 ir3_reg_create(instr
, 0, dst_flags
); /* dst */
1111 __ssa_src(instr
, src
, 0);
1112 instr
->cat1
.src_type
= src_type
;
1113 instr
->cat1
.dst_type
= dst_type
;
1114 debug_assert(!(src
->regs
[0]->flags
& IR3_REG_ARRAY
));
1118 static inline struct ir3_instruction
*
1119 ir3_NOP(struct ir3_block
*block
)
1121 return ir3_instr_create(block
, OPC_NOP
);
1124 #define INSTR0(name) \
1125 static inline struct ir3_instruction * \
1126 ir3_##name(struct ir3_block *block) \
1128 struct ir3_instruction *instr = \
1129 ir3_instr_create(block, OPC_##name); \
1133 #define INSTR1(name) \
1134 static inline struct ir3_instruction * \
1135 ir3_##name(struct ir3_block *block, \
1136 struct ir3_instruction *a, unsigned aflags) \
1138 struct ir3_instruction *instr = \
1139 ir3_instr_create(block, OPC_##name); \
1140 ir3_reg_create(instr, 0, 0); /* dst */ \
1141 __ssa_src(instr, a, aflags); \
1145 #define INSTR2(name) \
1146 static inline struct ir3_instruction * \
1147 ir3_##name(struct ir3_block *block, \
1148 struct ir3_instruction *a, unsigned aflags, \
1149 struct ir3_instruction *b, unsigned bflags) \
1151 struct ir3_instruction *instr = \
1152 ir3_instr_create(block, OPC_##name); \
1153 ir3_reg_create(instr, 0, 0); /* dst */ \
1154 __ssa_src(instr, a, aflags); \
1155 __ssa_src(instr, b, bflags); \
1159 #define INSTR3(name) \
1160 static inline struct ir3_instruction * \
1161 ir3_##name(struct ir3_block *block, \
1162 struct ir3_instruction *a, unsigned aflags, \
1163 struct ir3_instruction *b, unsigned bflags, \
1164 struct ir3_instruction *c, unsigned cflags) \
1166 struct ir3_instruction *instr = \
1167 ir3_instr_create(block, OPC_##name); \
1168 ir3_reg_create(instr, 0, 0); /* dst */ \
1169 __ssa_src(instr, a, aflags); \
1170 __ssa_src(instr, b, bflags); \
1171 __ssa_src(instr, c, cflags); \
1175 #define INSTR3F(f, name) \
1176 static inline struct ir3_instruction * \
1177 ir3_##name##_##f(struct ir3_block *block, \
1178 struct ir3_instruction *a, unsigned aflags, \
1179 struct ir3_instruction *b, unsigned bflags, \
1180 struct ir3_instruction *c, unsigned cflags) \
1182 struct ir3_instruction *instr = \
1183 ir3_instr_create2(block, OPC_##name, 5); \
1184 ir3_reg_create(instr, 0, 0); /* dst */ \
1185 __ssa_src(instr, a, aflags); \
1186 __ssa_src(instr, b, bflags); \
1187 __ssa_src(instr, c, cflags); \
1188 instr->flags |= IR3_INSTR_##f; \
1192 #define INSTR4(name) \
1193 static inline struct ir3_instruction * \
1194 ir3_##name(struct ir3_block *block, \
1195 struct ir3_instruction *a, unsigned aflags, \
1196 struct ir3_instruction *b, unsigned bflags, \
1197 struct ir3_instruction *c, unsigned cflags, \
1198 struct ir3_instruction *d, unsigned dflags) \
1200 struct ir3_instruction *instr = \
1201 ir3_instr_create2(block, OPC_##name, 5); \
1202 ir3_reg_create(instr, 0, 0); /* dst */ \
1203 __ssa_src(instr, a, aflags); \
1204 __ssa_src(instr, b, bflags); \
1205 __ssa_src(instr, c, cflags); \
1206 __ssa_src(instr, d, dflags); \
1210 #define INSTR4F(f, name) \
1211 static inline struct ir3_instruction * \
1212 ir3_##name##_##f(struct ir3_block *block, \
1213 struct ir3_instruction *a, unsigned aflags, \
1214 struct ir3_instruction *b, unsigned bflags, \
1215 struct ir3_instruction *c, unsigned cflags, \
1216 struct ir3_instruction *d, unsigned dflags) \
1218 struct ir3_instruction *instr = \
1219 ir3_instr_create2(block, OPC_##name, 5); \
1220 ir3_reg_create(instr, 0, 0); /* dst */ \
1221 __ssa_src(instr, a, aflags); \
1222 __ssa_src(instr, b, bflags); \
1223 __ssa_src(instr, c, cflags); \
1224 __ssa_src(instr, d, dflags); \
1225 instr->flags |= IR3_INSTR_##f; \
1229 /* cat0 instructions: */
1235 /* cat2 instructions, most 2 src but some 1 src: */
1283 /* cat3 instructions: */
1301 /* cat4 instructions: */
1310 /* cat5 instructions: */
1314 static inline struct ir3_instruction
*
1315 ir3_SAM(struct ir3_block
*block
, opc_t opc
, type_t type
,
1316 unsigned wrmask
, unsigned flags
, unsigned samp
, unsigned tex
,
1317 struct ir3_instruction
*src0
, struct ir3_instruction
*src1
)
1319 struct ir3_instruction
*sam
;
1320 struct ir3_register
*reg
;
1322 sam
= ir3_instr_create(block
, opc
);
1323 sam
->flags
|= flags
;
1324 ir3_reg_create(sam
, 0, 0)->wrmask
= wrmask
;
1326 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
1327 reg
->wrmask
= (1 << (src0
->regs_count
- 1)) - 1;
1331 reg
= ir3_reg_create(sam
, 0, IR3_REG_SSA
);
1333 reg
->wrmask
= (1 << (src1
->regs_count
- 1)) - 1;
1335 sam
->cat5
.samp
= samp
;
1336 sam
->cat5
.tex
= tex
;
1337 sam
->cat5
.type
= type
;
1342 /* cat6 instructions: */
1355 INSTR2(ATOMIC_CMPXCHG
)
1363 INSTR3F(G
, ATOMIC_ADD
)
1364 INSTR3F(G
, ATOMIC_SUB
)
1365 INSTR3F(G
, ATOMIC_XCHG
)
1366 INSTR3F(G
, ATOMIC_INC
)
1367 INSTR3F(G
, ATOMIC_DEC
)
1368 INSTR3F(G
, ATOMIC_CMPXCHG
)
1369 INSTR3F(G
, ATOMIC_MIN
)
1370 INSTR3F(G
, ATOMIC_MAX
)
1371 INSTR3F(G
, ATOMIC_AND
)
1372 INSTR3F(G
, ATOMIC_OR
)
1373 INSTR3F(G
, ATOMIC_XOR
)
1378 INSTR4F(G
, ATOMIC_ADD
)
1379 INSTR4F(G
, ATOMIC_SUB
)
1380 INSTR4F(G
, ATOMIC_XCHG
)
1381 INSTR4F(G
, ATOMIC_INC
)
1382 INSTR4F(G
, ATOMIC_DEC
)
1383 INSTR4F(G
, ATOMIC_CMPXCHG
)
1384 INSTR4F(G
, ATOMIC_MIN
)
1385 INSTR4F(G
, ATOMIC_MAX
)
1386 INSTR4F(G
, ATOMIC_AND
)
1387 INSTR4F(G
, ATOMIC_OR
)
1388 INSTR4F(G
, ATOMIC_XOR
)
1391 /* cat7 instructions: */
1395 /* ************************************************************************* */
1396 /* split this out or find some helper to use.. like main/bitset.h.. */
1402 typedef uint8_t regmask_t
[2 * MAX_REG
/ 8];
1404 static inline unsigned regmask_idx(struct ir3_register
*reg
)
1406 unsigned num
= (reg
->flags
& IR3_REG_RELATIV
) ? reg
->array
.offset
: reg
->num
;
1407 debug_assert(num
< MAX_REG
);
1408 if (reg
->flags
& IR3_REG_HALF
)
1413 static inline void regmask_init(regmask_t
*regmask
)
1415 memset(regmask
, 0, sizeof(*regmask
));
1418 static inline void regmask_set(regmask_t
*regmask
, struct ir3_register
*reg
)
1420 unsigned idx
= regmask_idx(reg
);
1421 if (reg
->flags
& IR3_REG_RELATIV
) {
1423 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1424 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1427 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1429 (*regmask
)[idx
/ 8] |= 1 << (idx
% 8);
1433 static inline void regmask_or(regmask_t
*dst
, regmask_t
*a
, regmask_t
*b
)
1436 for (i
= 0; i
< ARRAY_SIZE(*dst
); i
++)
1437 (*dst
)[i
] = (*a
)[i
] | (*b
)[i
];
1440 /* set bits in a if not set in b, conceptually:
1443 static inline void regmask_set_if_not(regmask_t
*a
,
1444 struct ir3_register
*reg
, regmask_t
*b
)
1446 unsigned idx
= regmask_idx(reg
);
1447 if (reg
->flags
& IR3_REG_RELATIV
) {
1449 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1450 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1451 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1454 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1456 if (!((*b
)[idx
/ 8] & (1 << (idx
% 8))))
1457 (*a
)[idx
/ 8] |= 1 << (idx
% 8);
1461 static inline bool regmask_get(regmask_t
*regmask
,
1462 struct ir3_register
*reg
)
1464 unsigned idx
= regmask_idx(reg
);
1465 if (reg
->flags
& IR3_REG_RELATIV
) {
1467 for (i
= 0; i
< reg
->size
; i
++, idx
++)
1468 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1472 for (mask
= reg
->wrmask
; mask
; mask
>>= 1, idx
++)
1474 if ((*regmask
)[idx
/ 8] & (1 << (idx
% 8)))
1480 /* ************************************************************************* */