2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "util/ralloc.h"
29 #include "ir3_compiler.h"
31 static const struct debug_named_value shader_debug_options
[] = {
32 {"vs", IR3_DBG_SHADER_VS
, "Print shader disasm for vertex shaders"},
33 {"tcs", IR3_DBG_SHADER_TCS
, "Print shader disasm for tess ctrl shaders"},
34 {"tes", IR3_DBG_SHADER_TES
, "Print shader disasm for tess eval shaders"},
35 {"gs", IR3_DBG_SHADER_GS
, "Print shader disasm for geometry shaders"},
36 {"fs", IR3_DBG_SHADER_FS
, "Print shader disasm for fragment shaders"},
37 {"cs", IR3_DBG_SHADER_CS
, "Print shader disasm for compute shaders"},
38 {"disasm", IR3_DBG_DISASM
, "Dump NIR and adreno shader disassembly"},
39 {"optmsgs", IR3_DBG_OPTMSGS
, "Enable optimizer debug messages"},
40 {"forces2en", IR3_DBG_FORCES2EN
, "Force s2en mode for tex sampler instructions"},
41 {"nouboopt", IR3_DBG_NOUBOOPT
, "Disable lowering UBO to uniform"},
42 {"nofp16", IR3_DBG_NOFP16
, "Don't lower mediump to fp16"},
44 /* DEBUG-only options: */
45 {"schedmsgs", IR3_DBG_SCHEDMSGS
, "Enable scheduler debug messages"},
46 {"ramsgs", IR3_DBG_RAMSGS
, "Enable register-allocation debug messages"},
51 DEBUG_GET_ONCE_FLAGS_OPTION(ir3_shader_debug
, "IR3_SHADER_DEBUG", shader_debug_options
, 0)
53 enum ir3_shader_debug ir3_shader_debug
= 0;
55 struct ir3_compiler
* ir3_compiler_create(struct fd_device
*dev
, uint32_t gpu_id
)
57 struct ir3_compiler
*compiler
= rzalloc(NULL
, struct ir3_compiler
);
59 ir3_shader_debug
= debug_get_option_ir3_shader_debug();
62 compiler
->gpu_id
= gpu_id
;
63 compiler
->set
= ir3_ra_alloc_reg_set(compiler
);
65 if (compiler
->gpu_id
>= 600) {
66 compiler
->samgq_workaround
= true;
69 if (compiler
->gpu_id
>= 400) {
70 /* need special handling for "flat" */
71 compiler
->flat_bypass
= true;
72 compiler
->levels_add_one
= false;
73 compiler
->unminify_coords
= false;
74 compiler
->txf_ms_with_isaml
= false;
75 compiler
->array_index_add_half
= true;
76 /* Some a6xxs can apparently do 640 consts, but not all. Need to
77 * characterize this better across GPUs
79 compiler
->max_const
= 512;
80 compiler
->const_upload_unit
= 4;
82 /* no special handling for "flat" */
83 compiler
->flat_bypass
= false;
84 compiler
->levels_add_one
= true;
85 compiler
->unminify_coords
= true;
86 compiler
->txf_ms_with_isaml
= true;
87 compiler
->array_index_add_half
= false;
88 compiler
->max_const
= 512;
89 compiler
->const_upload_unit
= 8;