src/freedreno/ir3/ir3_compiler.c

   1 /*
   2  * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/ralloc.h"
  28
  29 #include "ir3_compiler.h"
  30
  31 static const struct debug_named_value shader_debug_options[] = {
  32         {"vs",         IR3_DBG_SHADER_VS,  "Print shader disasm for vertex shaders"},
  33         {"tcs",        IR3_DBG_SHADER_TCS, "Print shader disasm for tess ctrl shaders"},
  34         {"tes",        IR3_DBG_SHADER_TES, "Print shader disasm for tess eval shaders"},
  35         {"gs",         IR3_DBG_SHADER_GS,  "Print shader disasm for geometry shaders"},
  36         {"fs",         IR3_DBG_SHADER_FS,  "Print shader disasm for fragment shaders"},
  37         {"cs",         IR3_DBG_SHADER_CS,  "Print shader disasm for compute shaders"},
  38         {"disasm",     IR3_DBG_DISASM,     "Dump NIR and adreno shader disassembly"},
  39         {"optmsgs",    IR3_DBG_OPTMSGS,    "Enable optimizer debug messages"},
  40         {"forces2en",  IR3_DBG_FORCES2EN,  "Force s2en mode for tex sampler instructions"},
  41         {"nouboopt",   IR3_DBG_NOUBOOPT,   "Disable lowering UBO to uniform"},
  42         DEBUG_NAMED_VALUE_END
  43 };
  44
  45 DEBUG_GET_ONCE_FLAGS_OPTION(ir3_shader_debug, "IR3_SHADER_DEBUG", shader_debug_options, 0)
  46
  47 enum ir3_shader_debug ir3_shader_debug = 0;
  48
  49 struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id)
  50 {
  51         struct ir3_compiler *compiler = rzalloc(NULL, struct ir3_compiler);
  52
  53         ir3_shader_debug = debug_get_option_ir3_shader_debug();
  54
  55         compiler->dev = dev;
  56         compiler->gpu_id = gpu_id;
  57         compiler->set = ir3_ra_alloc_reg_set(compiler);
  58
  59         if (compiler->gpu_id >= 600) {
  60                 compiler->samgq_workaround = true;
  61         }
  62
  63         if (compiler->gpu_id >= 400) {
  64                 /* need special handling for "flat" */
  65                 compiler->flat_bypass = true;
  66                 compiler->levels_add_one = false;
  67                 compiler->unminify_coords = false;
  68                 compiler->txf_ms_with_isaml = false;
  69                 compiler->array_index_add_half = true;
  70         } else {
  71                 /* no special handling for "flat" */
  72                 compiler->flat_bypass = false;
  73                 compiler->levels_add_one = true;
  74                 compiler->unminify_coords = true;
  75                 compiler->txf_ms_with_isaml = true;
  76                 compiler->array_index_add_half = false;
  77         }
  78
  79         return compiler;
  80 }