src/freedreno/ir3/ir3_compiler.c

   1 /*
   2  * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/ralloc.h"
  28
  29 #include "ir3_compiler.h"
  30
  31 static const struct debug_named_value shader_debug_options[] = {
  32         {"vs",         IR3_DBG_SHADER_VS,  "Print shader disasm for vertex shaders"},
  33         {"fs",         IR3_DBG_SHADER_FS,  "Print shader disasm for fragment shaders"},
  34         {"cs",         IR3_DBG_SHADER_CS,  "Print shader disasm for compute shaders"},
  35         {"disasm",     IR3_DBG_DISASM,     "Dump NIR and adreno shader disassembly"},
  36         {"optmsgs",    IR3_DBG_OPTMSGS,    "Enable optimizer debug messages"},
  37         {"forces2en",  IR3_DBG_FORCES2EN,  "Force s2en mode for tex sampler instructions"},
  38         DEBUG_NAMED_VALUE_END
  39 };
  40
  41 DEBUG_GET_ONCE_FLAGS_OPTION(ir3_shader_debug, "IR3_SHADER_DEBUG", shader_debug_options, 0)
  42
  43 enum ir3_shader_debug ir3_shader_debug = 0;
  44
  45 struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id)
  46 {
  47         struct ir3_compiler *compiler = rzalloc(NULL, struct ir3_compiler);
  48
  49         ir3_shader_debug = debug_get_option_ir3_shader_debug();
  50
  51         compiler->dev = dev;
  52         compiler->gpu_id = gpu_id;
  53         compiler->set = ir3_ra_alloc_reg_set(compiler);
  54
  55         if (compiler->gpu_id >= 400) {
  56                 /* need special handling for "flat" */
  57                 compiler->flat_bypass = true;
  58                 compiler->levels_add_one = false;
  59                 compiler->unminify_coords = false;
  60                 compiler->txf_ms_with_isaml = false;
  61                 compiler->array_index_add_half = true;
  62         } else {
  63                 /* no special handling for "flat" */
  64                 compiler->flat_bypass = false;
  65                 compiler->levels_add_one = true;
  66                 compiler->unminify_coords = true;
  67                 compiler->txf_ms_with_isaml = true;
  68                 compiler->array_index_add_half = false;
  69         }
  70
  71         return compiler;
  72 }