src/freedreno/ir3/ir3_compiler.h

   1 /*
   2  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #ifndef IR3_COMPILER_H_
  28 #define IR3_COMPILER_H_
  29
  30 #include "ir3_shader.h"
  31
  32 struct ir3_ra_reg_set;
  33
  34 struct ir3_compiler {
  35         struct fd_device *dev;
  36         uint32_t gpu_id;
  37         struct ir3_ra_reg_set *set;
  38         uint32_t shader_count;
  39
  40         /*
  41          * Configuration options for things that are handled differently on
  42          * different generations:
  43          */
  44
  45         /* a4xx (and later) drops SP_FS_FLAT_SHAD_MODE_REG_* for flat-interpolate
  46          * so we need to use ldlv.u32 to load the varying directly:
  47          */
  48         bool flat_bypass;
  49
  50         /* on a3xx, we need to add one to # of array levels:
  51          */
  52         bool levels_add_one;
  53
  54         /* on a3xx, we need to scale up integer coords for isaml based
  55          * on LoD:
  56          */
  57         bool unminify_coords;
  58
  59         /* on a3xx do txf_ms w/ isaml and scaled coords: */
  60         bool txf_ms_with_isaml;
  61
  62         /* on a4xx, for array textures we need to add 0.5 to the array
  63          * index coordinate:
  64          */
  65         bool array_index_add_half;
  66 };
  67
  68 struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id);
  69
  70 int ir3_compile_shader_nir(struct ir3_compiler *compiler,
  71                 struct ir3_shader_variant *so);
  72
  73 enum ir3_shader_debug {
  74         IR3_DBG_SHADER_VS = 0x01,
  75         IR3_DBG_SHADER_FS = 0x02,
  76         IR3_DBG_SHADER_CS = 0x04,
  77         IR3_DBG_DISASM    = 0x08,
  78         IR3_DBG_OPTMSGS   = 0x10,
  79         IR3_DBG_FORCES2EN = 0x20,
  80 };
  81
  82 extern enum ir3_shader_debug ir3_shader_debug;
  83
  84 static inline bool
  85 shader_debug_enabled(gl_shader_stage type)
  86 {
  87         switch (type) {
  88         case MESA_SHADER_VERTEX:      return !!(ir3_shader_debug & IR3_DBG_SHADER_VS);
  89         case MESA_SHADER_FRAGMENT:    return !!(ir3_shader_debug & IR3_DBG_SHADER_FS);
  90         case MESA_SHADER_COMPUTE:     return !!(ir3_shader_debug & IR3_DBG_SHADER_CS);
  91         default:
  92                 debug_assert(0);
  93                 return false;
  94         }
  95 }
  96
  97 #endif /* IR3_COMPILER_H_ */