src/freedreno/ir3/ir3_compiler.h

   1 /*
   2  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #ifndef IR3_COMPILER_H_
  28 #define IR3_COMPILER_H_
  29
  30 #include "ir3_shader.h"
  31
  32 struct ir3_ra_reg_set;
  33
  34 struct ir3_compiler {
  35         struct fd_device *dev;
  36         uint32_t gpu_id;
  37         struct ir3_ra_reg_set *set;
  38         struct ir3_ra_reg_set *mergedregs_set;
  39         uint32_t shader_count;
  40
  41         /*
  42          * Configuration options for things that are handled differently on
  43          * different generations:
  44          */
  45
  46         /* a4xx (and later) drops SP_FS_FLAT_SHAD_MODE_REG_* for flat-interpolate
  47          * so we need to use ldlv.u32 to load the varying directly:
  48          */
  49         bool flat_bypass;
  50
  51         /* on a3xx, we need to add one to # of array levels:
  52          */
  53         bool levels_add_one;
  54
  55         /* on a3xx, we need to scale up integer coords for isaml based
  56          * on LoD:
  57          */
  58         bool unminify_coords;
  59
  60         /* on a3xx do txf_ms w/ isaml and scaled coords: */
  61         bool txf_ms_with_isaml;
  62
  63         /* on a4xx, for array textures we need to add 0.5 to the array
  64          * index coordinate:
  65          */
  66         bool array_index_add_half;
  67
  68         /* on a6xx, rewrite samgp to sequence of samgq0-3 in vertex shaders:
  69          */
  70         bool samgq_workaround;
  71
  72         /* on a3xx, the limit on const access is lower than later gens (in vec4
  73          * units):
  74          */
  75         uint32_t max_const;
  76
  77         /* on a3xx, the unit of indirect const load is higher than later gens (in
  78          * vec4 units):
  79          */
  80         uint32_t const_upload_unit;
  81 };
  82
  83 struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id);
  84
  85 int ir3_compile_shader_nir(struct ir3_compiler *compiler,
  86                 struct ir3_shader_variant *so);
  87
  88 /* gpu pointer size in units of 32bit registers/slots */
  89 static inline
  90 unsigned ir3_pointer_size(struct ir3_compiler *compiler)
  91 {
  92         return (compiler->gpu_id >= 500) ? 2 : 1;
  93 }
  94
  95 enum ir3_shader_debug {
  96         IR3_DBG_SHADER_VS  = BITFIELD_BIT(0),
  97         IR3_DBG_SHADER_TCS = BITFIELD_BIT(1),
  98         IR3_DBG_SHADER_TES = BITFIELD_BIT(2),
  99         IR3_DBG_SHADER_GS  = BITFIELD_BIT(3),
 100         IR3_DBG_SHADER_FS  = BITFIELD_BIT(4),
 101         IR3_DBG_SHADER_CS  = BITFIELD_BIT(5),
 102         IR3_DBG_DISASM     = BITFIELD_BIT(6),
 103         IR3_DBG_OPTMSGS    = BITFIELD_BIT(7),
 104         IR3_DBG_FORCES2EN  = BITFIELD_BIT(8),
 105         IR3_DBG_NOUBOOPT   = BITFIELD_BIT(9),
 106         IR3_DBG_NOFP16     = BITFIELD_BIT(10),
 107
 108         /* DEBUG-only options: */
 109         IR3_DBG_SCHEDMSGS  = BITFIELD_BIT(20),
 110         IR3_DBG_RAMSGS     = BITFIELD_BIT(21),
 111 };
 112
 113 extern enum ir3_shader_debug ir3_shader_debug;
 114
 115 static inline bool
 116 shader_debug_enabled(gl_shader_stage type)
 117 {
 118         if (ir3_shader_debug & IR3_DBG_DISASM)
 119                 return true;
 120
 121         switch (type) {
 122         case MESA_SHADER_VERTEX:      return !!(ir3_shader_debug & IR3_DBG_SHADER_VS);
 123         case MESA_SHADER_TESS_CTRL:   return !!(ir3_shader_debug & IR3_DBG_SHADER_TCS);
 124         case MESA_SHADER_TESS_EVAL:   return !!(ir3_shader_debug & IR3_DBG_SHADER_TES);
 125         case MESA_SHADER_GEOMETRY:    return !!(ir3_shader_debug & IR3_DBG_SHADER_GS);
 126         case MESA_SHADER_FRAGMENT:    return !!(ir3_shader_debug & IR3_DBG_SHADER_FS);
 127         case MESA_SHADER_COMPUTE:     return !!(ir3_shader_debug & IR3_DBG_SHADER_CS);
 128         default:
 129                 debug_assert(0);
 130                 return false;
 131         }
 132 }
 133
 134 static inline void
 135 ir3_debug_print(struct ir3 *ir, const char *when)
 136 {
 137         if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
 138                 printf("%s:\n", when);
 139                 ir3_print(ir);
 140         }
 141 }
 142
 143 #endif /* IR3_COMPILER_H_ */