2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #ifndef IR3_COMPILER_H_
28 #define IR3_COMPILER_H_
32 struct ir3_ra_reg_set
;
36 struct fd_device
*dev
;
38 struct ir3_ra_reg_set
*set
;
39 struct ir3_ra_reg_set
*mergedregs_set
;
40 uint32_t shader_count
;
43 * Configuration options for things that are handled differently on
44 * different generations:
47 /* a4xx (and later) drops SP_FS_FLAT_SHAD_MODE_REG_* for flat-interpolate
48 * so we need to use ldlv.u32 to load the varying directly:
52 /* on a3xx, we need to add one to # of array levels:
56 /* on a3xx, we need to scale up integer coords for isaml based
61 /* on a3xx do txf_ms w/ isaml and scaled coords: */
62 bool txf_ms_with_isaml
;
64 /* on a4xx, for array textures we need to add 0.5 to the array
67 bool array_index_add_half
;
69 /* on a6xx, rewrite samgp to sequence of samgq0-3 in vertex shaders:
71 bool samgq_workaround
;
73 /* The maximum number of constants, in vec4's, across the entire graphics
76 uint16_t max_const_pipeline
;
78 /* The maximum number of constants, in vec4's, for VS+HS+DS+GS. */
79 uint16_t max_const_geom
;
81 /* The maximum number of constants, in vec4's, for FS. */
82 uint16_t max_const_frag
;
84 /* A "safe" max constlen that can be applied to each shader in the
85 * pipeline which we guarantee will never exceed any combined limits.
87 uint16_t max_const_safe
;
89 /* The maximum number of constants, in vec4's, for compute shaders. */
90 uint16_t max_const_compute
;
92 /* on a3xx, the unit of indirect const load is higher than later gens (in
95 uint32_t const_upload_unit
;
98 struct ir3_compiler
* ir3_compiler_create(struct fd_device
*dev
, uint32_t gpu_id
);
100 int ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
101 struct ir3_shader_variant
*so
);
103 /* gpu pointer size in units of 32bit registers/slots */
105 unsigned ir3_pointer_size(struct ir3_compiler
*compiler
)
107 return (compiler
->gpu_id
>= 500) ? 2 : 1;
110 enum ir3_shader_debug
{
111 IR3_DBG_SHADER_VS
= BITFIELD_BIT(0),
112 IR3_DBG_SHADER_TCS
= BITFIELD_BIT(1),
113 IR3_DBG_SHADER_TES
= BITFIELD_BIT(2),
114 IR3_DBG_SHADER_GS
= BITFIELD_BIT(3),
115 IR3_DBG_SHADER_FS
= BITFIELD_BIT(4),
116 IR3_DBG_SHADER_CS
= BITFIELD_BIT(5),
117 IR3_DBG_DISASM
= BITFIELD_BIT(6),
118 IR3_DBG_OPTMSGS
= BITFIELD_BIT(7),
119 IR3_DBG_FORCES2EN
= BITFIELD_BIT(8),
120 IR3_DBG_NOUBOOPT
= BITFIELD_BIT(9),
121 IR3_DBG_NOFP16
= BITFIELD_BIT(10),
123 /* DEBUG-only options: */
124 IR3_DBG_SCHEDMSGS
= BITFIELD_BIT(20),
125 IR3_DBG_RAMSGS
= BITFIELD_BIT(21),
128 extern enum ir3_shader_debug ir3_shader_debug
;
131 shader_debug_enabled(gl_shader_stage type
)
133 if (ir3_shader_debug
& IR3_DBG_DISASM
)
137 case MESA_SHADER_VERTEX
: return !!(ir3_shader_debug
& IR3_DBG_SHADER_VS
);
138 case MESA_SHADER_TESS_CTRL
: return !!(ir3_shader_debug
& IR3_DBG_SHADER_TCS
);
139 case MESA_SHADER_TESS_EVAL
: return !!(ir3_shader_debug
& IR3_DBG_SHADER_TES
);
140 case MESA_SHADER_GEOMETRY
: return !!(ir3_shader_debug
& IR3_DBG_SHADER_GS
);
141 case MESA_SHADER_FRAGMENT
: return !!(ir3_shader_debug
& IR3_DBG_SHADER_FS
);
142 case MESA_SHADER_COMPUTE
: return !!(ir3_shader_debug
& IR3_DBG_SHADER_CS
);
150 ir3_debug_print(struct ir3
*ir
, const char *when
)
152 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
153 printf("%s:\n", when
);
158 #endif /* IR3_COMPILER_H_ */