2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #ifndef IR3_COMPILER_H_
28 #define IR3_COMPILER_H_
30 #include "ir3_shader.h"
32 struct ir3_ra_reg_set
;
35 struct fd_device
*dev
;
37 struct ir3_ra_reg_set
*set
;
38 uint32_t shader_count
;
41 * Configuration options for things that are handled differently on
42 * different generations:
45 /* a4xx (and later) drops SP_FS_FLAT_SHAD_MODE_REG_* for flat-interpolate
46 * so we need to use ldlv.u32 to load the varying directly:
50 /* on a3xx, we need to add one to # of array levels:
54 /* on a3xx, we need to scale up integer coords for isaml based
59 /* on a3xx do txf_ms w/ isaml and scaled coords: */
60 bool txf_ms_with_isaml
;
62 /* on a4xx, for array textures we need to add 0.5 to the array
65 bool array_index_add_half
;
67 /* on a6xx, rewrite samgp to sequence of samgq0-3 in vertex shaders:
69 bool samgq_workaround
;
72 struct ir3_compiler
* ir3_compiler_create(struct fd_device
*dev
, uint32_t gpu_id
);
74 int ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
75 struct ir3_shader_variant
*so
);
77 /* gpu pointer size in units of 32bit registers/slots */
79 unsigned ir3_pointer_size(struct ir3_compiler
*compiler
)
81 return (compiler
->gpu_id
>= 500) ? 2 : 1;
84 enum ir3_shader_debug
{
85 IR3_DBG_SHADER_VS
= 0x001,
86 IR3_DBG_SHADER_TCS
= 0x002,
87 IR3_DBG_SHADER_TES
= 0x004,
88 IR3_DBG_SHADER_GS
= 0x008,
89 IR3_DBG_SHADER_FS
= 0x010,
90 IR3_DBG_SHADER_CS
= 0x020,
91 IR3_DBG_DISASM
= 0x040,
92 IR3_DBG_OPTMSGS
= 0x080,
93 IR3_DBG_FORCES2EN
= 0x100,
94 IR3_DBG_NOUBOOPT
= 0x200,
97 extern enum ir3_shader_debug ir3_shader_debug
;
100 shader_debug_enabled(gl_shader_stage type
)
102 if (ir3_shader_debug
& IR3_DBG_DISASM
)
106 case MESA_SHADER_VERTEX
: return !!(ir3_shader_debug
& IR3_DBG_SHADER_VS
);
107 case MESA_SHADER_TESS_CTRL
: return !!(ir3_shader_debug
& IR3_DBG_SHADER_TCS
);
108 case MESA_SHADER_TESS_EVAL
: return !!(ir3_shader_debug
& IR3_DBG_SHADER_TES
);
109 case MESA_SHADER_GEOMETRY
: return !!(ir3_shader_debug
& IR3_DBG_SHADER_GS
);
110 case MESA_SHADER_FRAGMENT
: return !!(ir3_shader_debug
& IR3_DBG_SHADER_FS
);
111 case MESA_SHADER_COMPUTE
: return !!(ir3_shader_debug
& IR3_DBG_SHADER_CS
);
118 #endif /* IR3_COMPILER_H_ */