2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
38 #include "instr-a3xx.h"
40 #include "ir3_context.h"
43 static struct ir3_instruction
*
44 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
45 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
47 struct ir3_block
*block
= ctx
->block
;
48 struct ir3_instruction
*mov
;
49 struct ir3_register
*src
;
51 mov
= ir3_instr_create(block
, OPC_MOV
);
52 mov
->cat1
.src_type
= TYPE_U32
;
53 mov
->cat1
.dst_type
= TYPE_U32
;
54 ir3_reg_create(mov
, 0, 0);
55 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
58 src
->array
.offset
= n
;
60 ir3_instr_set_address(mov
, address
);
65 static struct ir3_instruction
*
66 create_input_compmask(struct ir3_context
*ctx
, unsigned n
, unsigned compmask
)
68 struct ir3_instruction
*in
;
70 in
= ir3_instr_create(ctx
->in_block
, OPC_META_INPUT
);
71 in
->inout
.block
= ctx
->in_block
;
72 ir3_reg_create(in
, n
, 0);
74 in
->regs
[0]->wrmask
= compmask
;
79 static struct ir3_instruction
*
80 create_input(struct ir3_context
*ctx
, unsigned n
)
82 return create_input_compmask(ctx
, n
, 0x1);
85 static struct ir3_instruction
*
86 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
, unsigned n
)
88 struct ir3_block
*block
= ctx
->block
;
89 struct ir3_instruction
*instr
;
90 /* packed inloc is fixed up later: */
91 struct ir3_instruction
*inloc
= create_immed(block
, n
);
94 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
95 instr
->cat6
.type
= TYPE_U32
;
96 instr
->cat6
.iim_val
= 1;
98 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->ij_pixel
, 0);
99 instr
->regs
[2]->wrmask
= 0x3;
105 static struct ir3_instruction
*
106 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
111 unsigned n
= const_state
->offsets
.driver_param
;
112 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
113 return create_uniform(ctx
->block
, r
);
117 * Adreno uses uint rather than having dedicated bool type,
118 * which (potentially) requires some conversion, in particular
119 * when using output of an bool instr to int input, or visa
123 * -------+---------+-------+-
127 * To convert from an adreno bool (uint) to nir, use:
129 * absneg.s dst, (neg)src
131 * To convert back in the other direction:
133 * absneg.s dst, (abs)arc
135 * The CP step can clean up the absneg.s that cancel each other
136 * out, and with a slight bit of extra cleverness (to recognize
137 * the instructions which produce either a 0 or 1) can eliminate
138 * the absneg.s's completely when an instruction that wants
139 * 0/1 consumes the result. For example, when a nir 'bcsel'
140 * consumes the result of 'feq'. So we should be able to get by
141 * without a boolean resolve step, and without incuring any
142 * extra penalty in instruction count.
145 /* NIR bool -> native (adreno): */
146 static struct ir3_instruction
*
147 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
149 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
152 /* native (adreno) -> NIR bool: */
153 static struct ir3_instruction
*
154 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
156 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
160 * alu/sfu instructions:
163 static struct ir3_instruction
*
164 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
165 unsigned src_bitsize
, nir_op op
)
167 type_t src_type
, dst_type
;
171 case nir_op_f2f16_rtne
:
172 case nir_op_f2f16_rtz
:
180 switch (src_bitsize
) {
188 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
197 switch (src_bitsize
) {
208 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
217 switch (src_bitsize
) {
228 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
233 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
243 case nir_op_f2f16_rtne
:
244 case nir_op_f2f16_rtz
:
246 /* TODO how to handle rounding mode? */
283 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
286 return ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
290 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
292 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
293 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
294 unsigned bs
[info
->num_inputs
]; /* bit size */
295 struct ir3_block
*b
= ctx
->block
;
296 unsigned dst_sz
, wrmask
;
297 type_t dst_type
= nir_dest_bit_size(alu
->dest
.dest
) < 32 ?
300 if (alu
->dest
.dest
.is_ssa
) {
301 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
302 wrmask
= (1 << dst_sz
) - 1;
304 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
305 wrmask
= alu
->dest
.write_mask
;
308 dst
= ir3_get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
310 /* Vectors are special in that they have non-scalarized writemasks,
311 * and just take the first swizzle channel for each argument in
312 * order into each writemask channel.
314 if ((alu
->op
== nir_op_vec2
) ||
315 (alu
->op
== nir_op_vec3
) ||
316 (alu
->op
== nir_op_vec4
)) {
318 for (int i
= 0; i
< info
->num_inputs
; i
++) {
319 nir_alu_src
*asrc
= &alu
->src
[i
];
321 compile_assert(ctx
, !asrc
->abs
);
322 compile_assert(ctx
, !asrc
->negate
);
324 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
326 src
[i
] = create_immed_typed(ctx
->block
, 0, dst_type
);
327 dst
[i
] = ir3_MOV(b
, src
[i
], dst_type
);
330 ir3_put_dst(ctx
, &alu
->dest
.dest
);
334 /* We also get mov's with more than one component for mov's so
335 * handle those specially:
337 if (alu
->op
== nir_op_mov
) {
338 nir_alu_src
*asrc
= &alu
->src
[0];
339 struct ir3_instruction
*const *src0
= ir3_get_src(ctx
, &asrc
->src
);
341 for (unsigned i
= 0; i
< dst_sz
; i
++) {
342 if (wrmask
& (1 << i
)) {
343 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], dst_type
);
349 ir3_put_dst(ctx
, &alu
->dest
.dest
);
353 /* General case: We can just grab the one used channel per src. */
354 for (int i
= 0; i
< info
->num_inputs
; i
++) {
355 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
356 nir_alu_src
*asrc
= &alu
->src
[i
];
358 compile_assert(ctx
, !asrc
->abs
);
359 compile_assert(ctx
, !asrc
->negate
);
361 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
362 bs
[i
] = nir_src_bit_size(asrc
->src
);
364 compile_assert(ctx
, src
[i
]);
369 case nir_op_f2f16_rtne
:
370 case nir_op_f2f16_rtz
:
388 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
390 case nir_op_fquantize2f16
:
391 dst
[0] = create_cov(ctx
,
392 create_cov(ctx
, src
[0], 32, nir_op_f2f16
),
396 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
397 dst
[0]->cat2
.condition
= IR3_COND_NE
;
398 dst
[0] = ir3_n2b(b
, dst
[0]);
401 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F16
);
404 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
409 dst
[0] = ir3_b2n(b
, src
[0]);
412 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
413 dst
[0]->cat2
.condition
= IR3_COND_NE
;
414 dst
[0] = ir3_n2b(b
, dst
[0]);
418 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
421 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
424 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
427 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
430 /* if there is just a single use of the src, and it supports
431 * (sat) bit, we can just fold the (sat) flag back to the
432 * src instruction and create a mov. This is easier for cp
435 * TODO probably opc_cat==4 is ok too
437 if (alu
->src
[0].src
.is_ssa
&&
438 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
439 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
440 src
[0]->flags
|= IR3_INSTR_SAT
;
441 dst
[0] = ir3_MOV(b
, src
[0], dst_type
);
443 /* otherwise generate a max.f that saturates.. blob does
444 * similar (generating a cat2 mov using max.f)
446 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
447 dst
[0]->flags
|= IR3_INSTR_SAT
;
451 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
454 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
457 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
460 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
463 case nir_op_fddx_coarse
:
464 dst
[0] = ir3_DSX(b
, src
[0], 0);
465 dst
[0]->cat5
.type
= TYPE_F32
;
468 case nir_op_fddy_coarse
:
469 dst
[0] = ir3_DSY(b
, src
[0], 0);
470 dst
[0]->cat5
.type
= TYPE_F32
;
474 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
475 dst
[0]->cat2
.condition
= IR3_COND_LT
;
476 dst
[0] = ir3_n2b(b
, dst
[0]);
479 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
480 dst
[0]->cat2
.condition
= IR3_COND_GE
;
481 dst
[0] = ir3_n2b(b
, dst
[0]);
484 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
485 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
486 dst
[0] = ir3_n2b(b
, dst
[0]);
489 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
490 dst
[0]->cat2
.condition
= IR3_COND_NE
;
491 dst
[0] = ir3_n2b(b
, dst
[0]);
494 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
497 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
500 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
502 case nir_op_fround_even
:
503 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
506 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
510 dst
[0] = ir3_SIN(b
, src
[0], 0);
513 dst
[0] = ir3_COS(b
, src
[0], 0);
516 dst
[0] = ir3_RSQ(b
, src
[0], 0);
519 dst
[0] = ir3_RCP(b
, src
[0], 0);
522 dst
[0] = ir3_LOG2(b
, src
[0], 0);
525 dst
[0] = ir3_EXP2(b
, src
[0], 0);
528 dst
[0] = ir3_SQRT(b
, src
[0], 0);
532 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
535 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
538 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
541 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
544 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
547 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
550 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
552 case nir_op_umul_low
:
553 dst
[0] = ir3_MULL_U(b
, src
[0], 0, src
[1], 0);
555 case nir_op_imadsh_mix16
:
556 dst
[0] = ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0, src
[2], 0);
559 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
562 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
565 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
568 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
571 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
574 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
577 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
580 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
583 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
584 dst
[0]->cat2
.condition
= IR3_COND_LT
;
585 dst
[0] = ir3_n2b(b
, dst
[0]);
588 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
589 dst
[0]->cat2
.condition
= IR3_COND_GE
;
590 dst
[0] = ir3_n2b(b
, dst
[0]);
593 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
594 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
595 dst
[0] = ir3_n2b(b
, dst
[0]);
598 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
599 dst
[0]->cat2
.condition
= IR3_COND_NE
;
600 dst
[0] = ir3_n2b(b
, dst
[0]);
603 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
604 dst
[0]->cat2
.condition
= IR3_COND_LT
;
605 dst
[0] = ir3_n2b(b
, dst
[0]);
608 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
609 dst
[0]->cat2
.condition
= IR3_COND_GE
;
610 dst
[0] = ir3_n2b(b
, dst
[0]);
613 case nir_op_b32csel
: {
614 struct ir3_instruction
*cond
= ir3_b2n(b
, src
[0]);
615 compile_assert(ctx
, bs
[1] == bs
[2]);
616 /* the boolean condition is 32b even if src[1] and src[2] are
617 * half-precision, but sel.b16 wants all three src's to be the
621 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
622 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
625 case nir_op_bit_count
: {
626 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
627 // double check on earlier gen's. Once half-precision support is
628 // in place, this should probably move to a NIR lowering pass:
629 struct ir3_instruction
*hi
, *lo
;
631 hi
= ir3_COV(b
, ir3_SHR_B(b
, src
[0], 0, create_immed(b
, 16), 0),
633 lo
= ir3_COV(b
, src
[0], TYPE_U32
, TYPE_U16
);
635 hi
= ir3_CBITS_B(b
, hi
, 0);
636 lo
= ir3_CBITS_B(b
, lo
, 0);
638 // TODO maybe the builders should default to making dst half-precision
639 // if the src's were half precision, to make this less awkward.. otoh
640 // we should probably just do this lowering in NIR.
641 hi
->regs
[0]->flags
|= IR3_REG_HALF
;
642 lo
->regs
[0]->flags
|= IR3_REG_HALF
;
644 dst
[0] = ir3_ADD_S(b
, hi
, 0, lo
, 0);
645 dst
[0]->regs
[0]->flags
|= IR3_REG_HALF
;
646 dst
[0] = ir3_COV(b
, dst
[0], TYPE_U16
, TYPE_U32
);
649 case nir_op_ifind_msb
: {
650 struct ir3_instruction
*cmp
;
651 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
652 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
653 cmp
->cat2
.condition
= IR3_COND_GE
;
654 dst
[0] = ir3_SEL_B32(b
,
655 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
659 case nir_op_ufind_msb
:
660 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
661 dst
[0] = ir3_SEL_B32(b
,
662 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
663 src
[0], 0, dst
[0], 0);
665 case nir_op_find_lsb
:
666 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
667 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
669 case nir_op_bitfield_reverse
:
670 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
674 ir3_context_error(ctx
, "Unhandled ALU op: %s\n",
675 nir_op_infos
[alu
->op
].name
);
679 ir3_put_dst(ctx
, &alu
->dest
.dest
);
682 /* handles direct/indirect UBO reads: */
684 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
685 struct ir3_instruction
**dst
)
687 struct ir3_block
*b
= ctx
->block
;
688 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
689 /* UBO addresses are the first driver params, but subtract 2 here to
690 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
691 * is the uniforms: */
692 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
693 unsigned ubo
= regid(const_state
->offsets
.ubo
, 0) - 2;
694 const unsigned ptrsz
= ir3_pointer_size(ctx
->compiler
);
698 /* First src is ubo index, which could either be an immed or not: */
699 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0];
700 if (is_same_type_mov(src0
) &&
701 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
702 base_lo
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
703 base_hi
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
705 base_lo
= create_uniform_indirect(b
, ubo
, ir3_get_addr(ctx
, src0
, ptrsz
));
706 base_hi
= create_uniform_indirect(b
, ubo
+ 1, ir3_get_addr(ctx
, src0
, ptrsz
));
708 /* NOTE: since relative addressing is used, make sure constlen is
709 * at least big enough to cover all the UBO addresses, since the
710 * assembler won't know what the max address reg is.
712 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
713 const_state
->offsets
.ubo
+ (ctx
->s
->info
.num_ubos
* ptrsz
));
716 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
719 if (nir_src_is_const(intr
->src
[1])) {
720 off
+= nir_src_as_uint(intr
->src
[1]);
722 /* For load_ubo_indirect, second src is indirect offset: */
723 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0];
725 /* and add offset to addr: */
726 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
729 /* if offset is to large to encode in the ldg, split it out: */
730 if ((off
+ (intr
->num_components
* 4)) > 1024) {
731 /* split out the minimal amount to improve the odds that
732 * cp can fit the immediate in the add.s instruction:
734 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
735 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
740 struct ir3_instruction
*carry
;
742 /* handle 32b rollover, ie:
743 * if (addr < base_lo)
746 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
747 carry
->cat2
.condition
= IR3_COND_LT
;
748 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
750 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
753 for (int i
= 0; i
< intr
->num_components
; i
++) {
754 struct ir3_instruction
*load
=
755 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0, /* num components */
756 create_immed(b
, off
+ i
* 4), 0);
757 load
->cat6
.type
= TYPE_U32
;
762 /* src[] = { block_index } */
764 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
765 struct ir3_instruction
**dst
)
767 /* SSBO size stored as a const starting at ssbo_sizes: */
768 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
769 unsigned blk_idx
= nir_src_as_uint(intr
->src
[0]);
770 unsigned idx
= regid(const_state
->offsets
.ssbo_sizes
, 0) +
771 const_state
->ssbo_size
.off
[blk_idx
];
773 debug_assert(const_state
->ssbo_size
.mask
& (1 << blk_idx
));
775 dst
[0] = create_uniform(ctx
->block
, idx
);
778 /* src[] = { offset }. const_index[] = { base } */
780 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
781 struct ir3_instruction
**dst
)
783 struct ir3_block
*b
= ctx
->block
;
784 struct ir3_instruction
*ldl
, *offset
;
787 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
788 base
= nir_intrinsic_base(intr
);
790 ldl
= ir3_LDL(b
, offset
, 0,
791 create_immed(b
, intr
->num_components
), 0,
792 create_immed(b
, base
), 0);
794 ldl
->cat6
.type
= utype_dst(intr
->dest
);
795 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
797 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
798 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
800 ir3_split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
803 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
805 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
807 struct ir3_block
*b
= ctx
->block
;
808 struct ir3_instruction
*stl
, *offset
;
809 struct ir3_instruction
* const *value
;
810 unsigned base
, wrmask
;
812 value
= ir3_get_src(ctx
, &intr
->src
[0]);
813 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
815 base
= nir_intrinsic_base(intr
);
816 wrmask
= nir_intrinsic_write_mask(intr
);
818 /* Combine groups of consecutive enabled channels in one write
819 * message. We use ffs to find the first enabled channel and then ffs on
820 * the bit-inverse, down-shifted writemask to determine the length of
821 * the block of enabled bits.
823 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
826 unsigned first_component
= ffs(wrmask
) - 1;
827 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
829 stl
= ir3_STL(b
, offset
, 0,
830 ir3_create_collect(ctx
, &value
[first_component
], length
), 0,
831 create_immed(b
, length
), 0);
832 stl
->cat6
.dst_offset
= first_component
+ base
;
833 stl
->cat6
.type
= utype_src(intr
->src
[0]);
834 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
835 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
837 array_insert(b
, b
->keeps
, stl
);
839 /* Clear the bits in the writemask that we just wrote, then try
840 * again to see if more channels are left.
842 wrmask
&= (15 << (first_component
+ length
));
846 /* src[] = { offset }. const_index[] = { base } */
848 emit_intrinsic_load_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
849 struct ir3_instruction
**dst
)
851 struct ir3_block
*b
= ctx
->block
;
852 struct ir3_instruction
*load
, *offset
;
855 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
856 base
= nir_intrinsic_base(intr
);
858 load
= ir3_LDLW(b
, offset
, 0,
859 create_immed(b
, intr
->num_components
), 0,
860 create_immed(b
, base
), 0);
862 load
->cat6
.type
= utype_dst(intr
->dest
);
863 load
->regs
[0]->wrmask
= MASK(intr
->num_components
);
865 load
->barrier_class
= IR3_BARRIER_SHARED_R
;
866 load
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
868 ir3_split_dest(b
, dst
, load
, 0, intr
->num_components
);
871 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
873 emit_intrinsic_store_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
875 struct ir3_block
*b
= ctx
->block
;
876 struct ir3_instruction
*store
, *offset
;
877 struct ir3_instruction
* const *value
;
878 unsigned base
, wrmask
;
880 value
= ir3_get_src(ctx
, &intr
->src
[0]);
881 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
883 base
= nir_intrinsic_base(intr
);
884 wrmask
= nir_intrinsic_write_mask(intr
);
886 /* Combine groups of consecutive enabled channels in one write
887 * message. We use ffs to find the first enabled channel and then ffs on
888 * the bit-inverse, down-shifted writemask to determine the length of
889 * the block of enabled bits.
891 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
894 unsigned first_component
= ffs(wrmask
) - 1;
895 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
897 store
= ir3_STLW(b
, offset
, 0,
898 ir3_create_collect(ctx
, &value
[first_component
], length
), 0,
899 create_immed(b
, length
), 0);
901 store
->cat6
.dst_offset
= first_component
+ base
;
902 store
->cat6
.type
= utype_src(intr
->src
[0]);
903 store
->barrier_class
= IR3_BARRIER_SHARED_W
;
904 store
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
906 array_insert(b
, b
->keeps
, store
);
908 /* Clear the bits in the writemask that we just wrote, then try
909 * again to see if more channels are left.
911 wrmask
&= (15 << (first_component
+ length
));
916 * CS shared variable atomic intrinsics
918 * All of the shared variable atomic memory operations read a value from
919 * memory, compute a new value using one of the operations below, write the
920 * new value to memory, and return the original value read.
922 * All operations take 2 sources except CompSwap that takes 3. These
925 * 0: The offset into the shared variable storage region that the atomic
926 * operation will operate on.
927 * 1: The data parameter to the atomic function (i.e. the value to add
928 * in shared_atomic_add, etc).
929 * 2: For CompSwap only: the second data parameter.
931 static struct ir3_instruction
*
932 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
934 struct ir3_block
*b
= ctx
->block
;
935 struct ir3_instruction
*atomic
, *src0
, *src1
;
936 type_t type
= TYPE_U32
;
938 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0]; /* offset */
939 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0]; /* value */
941 switch (intr
->intrinsic
) {
942 case nir_intrinsic_shared_atomic_add
:
943 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
945 case nir_intrinsic_shared_atomic_imin
:
946 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
949 case nir_intrinsic_shared_atomic_umin
:
950 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
952 case nir_intrinsic_shared_atomic_imax
:
953 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
956 case nir_intrinsic_shared_atomic_umax
:
957 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
959 case nir_intrinsic_shared_atomic_and
:
960 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
962 case nir_intrinsic_shared_atomic_or
:
963 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
965 case nir_intrinsic_shared_atomic_xor
:
966 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
968 case nir_intrinsic_shared_atomic_exchange
:
969 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
971 case nir_intrinsic_shared_atomic_comp_swap
:
972 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
973 src1
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
974 ir3_get_src(ctx
, &intr
->src
[2])[0],
977 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
983 atomic
->cat6
.iim_val
= 1;
985 atomic
->cat6
.type
= type
;
986 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
987 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
989 /* even if nothing consume the result, we can't DCE the instruction: */
990 array_insert(b
, b
->keeps
, atomic
);
995 /* TODO handle actual indirect/dynamic case.. which is going to be weird
996 * to handle with the image_mapping table..
998 static struct ir3_instruction
*
999 get_image_samp_tex_src(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1001 unsigned slot
= ir3_get_image_slot(nir_src_as_deref(intr
->src
[0]));
1002 unsigned tex_idx
= ir3_image_to_tex(&ctx
->so
->image_mapping
, slot
);
1003 struct ir3_instruction
*texture
, *sampler
;
1005 texture
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1006 sampler
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1008 return ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1014 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1016 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1017 struct ir3_instruction
**dst
)
1019 struct ir3_block
*b
= ctx
->block
;
1020 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
1021 struct ir3_instruction
*samp_tex
= get_image_samp_tex_src(ctx
, intr
);
1022 struct ir3_instruction
*sam
;
1023 struct ir3_instruction
* const *src0
= ir3_get_src(ctx
, &intr
->src
[1]);
1024 struct ir3_instruction
*coords
[4];
1025 unsigned flags
, ncoords
= ir3_get_image_coords(var
, &flags
);
1026 type_t type
= ir3_get_image_type(var
);
1028 /* hmm, this seems a bit odd, but it is what blob does and (at least
1029 * a5xx) just faults on bogus addresses otherwise:
1031 if (flags
& IR3_INSTR_3D
) {
1032 flags
&= ~IR3_INSTR_3D
;
1033 flags
|= IR3_INSTR_A
;
1036 for (unsigned i
= 0; i
< ncoords
; i
++)
1037 coords
[i
] = src0
[i
];
1040 coords
[ncoords
++] = create_immed(b
, 0);
1042 sam
= ir3_SAM(b
, OPC_ISAM
, type
, 0b1111, flags
,
1043 samp_tex
, ir3_create_collect(ctx
, coords
, ncoords
), NULL
);
1045 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1046 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1048 ir3_split_dest(b
, dst
, sam
, 0, 4);
1052 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1053 struct ir3_instruction
**dst
)
1055 struct ir3_block
*b
= ctx
->block
;
1056 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
1057 struct ir3_instruction
*samp_tex
= get_image_samp_tex_src(ctx
, intr
);
1058 struct ir3_instruction
*sam
, *lod
;
1059 unsigned flags
, ncoords
= ir3_get_image_coords(var
, &flags
);
1061 lod
= create_immed(b
, 0);
1062 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, 0b1111, flags
,
1063 samp_tex
, lod
, NULL
);
1065 /* Array size actually ends up in .w rather than .z. This doesn't
1066 * matter for miplevel 0, but for higher mips the value in z is
1067 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1068 * returned, which means that we have to add 1 to it for arrays for
1071 * Note use a temporary dst and then copy, since the size of the dst
1072 * array that is passed in is based on nir's understanding of the
1073 * result size, not the hardware's
1075 struct ir3_instruction
*tmp
[4];
1077 ir3_split_dest(b
, tmp
, sam
, 0, 4);
1079 /* get_size instruction returns size in bytes instead of texels
1080 * for imageBuffer, so we need to divide it by the pixel size
1081 * of the image format.
1083 * TODO: This is at least true on a5xx. Check other gens.
1085 enum glsl_sampler_dim dim
=
1086 glsl_get_sampler_dim(glsl_without_array(var
->type
));
1087 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
1088 /* Since all the possible values the divisor can take are
1089 * power-of-two (4, 8, or 16), the division is implemented
1091 * During shader setup, the log2 of the image format's
1092 * bytes-per-pixel should have been emitted in 2nd slot of
1093 * image_dims. See ir3_shader::emit_image_dims().
1095 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
1096 unsigned cb
= regid(const_state
->offsets
.image_dims
, 0) +
1097 const_state
->image_dims
.off
[var
->data
.driver_location
];
1098 struct ir3_instruction
*aux
= create_uniform(b
, cb
+ 1);
1100 tmp
[0] = ir3_SHR_B(b
, tmp
[0], 0, aux
, 0);
1103 for (unsigned i
= 0; i
< ncoords
; i
++)
1106 if (flags
& IR3_INSTR_A
) {
1107 if (ctx
->compiler
->levels_add_one
) {
1108 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
1110 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
1116 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1118 struct ir3_block
*b
= ctx
->block
;
1119 struct ir3_instruction
*barrier
;
1121 switch (intr
->intrinsic
) {
1122 case nir_intrinsic_barrier
:
1123 barrier
= ir3_BAR(b
);
1124 barrier
->cat7
.g
= true;
1125 barrier
->cat7
.l
= true;
1126 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1127 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1129 case nir_intrinsic_memory_barrier
:
1130 barrier
= ir3_FENCE(b
);
1131 barrier
->cat7
.g
= true;
1132 barrier
->cat7
.r
= true;
1133 barrier
->cat7
.w
= true;
1134 barrier
->cat7
.l
= true;
1135 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1136 IR3_BARRIER_BUFFER_W
;
1137 barrier
->barrier_conflict
=
1138 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1139 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1141 case nir_intrinsic_memory_barrier_atomic_counter
:
1142 case nir_intrinsic_memory_barrier_buffer
:
1143 barrier
= ir3_FENCE(b
);
1144 barrier
->cat7
.g
= true;
1145 barrier
->cat7
.r
= true;
1146 barrier
->cat7
.w
= true;
1147 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1148 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1149 IR3_BARRIER_BUFFER_W
;
1151 case nir_intrinsic_memory_barrier_image
:
1152 // TODO double check if this should have .g set
1153 barrier
= ir3_FENCE(b
);
1154 barrier
->cat7
.g
= true;
1155 barrier
->cat7
.r
= true;
1156 barrier
->cat7
.w
= true;
1157 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1158 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1159 IR3_BARRIER_IMAGE_W
;
1161 case nir_intrinsic_memory_barrier_shared
:
1162 barrier
= ir3_FENCE(b
);
1163 barrier
->cat7
.g
= true;
1164 barrier
->cat7
.l
= true;
1165 barrier
->cat7
.r
= true;
1166 barrier
->cat7
.w
= true;
1167 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1168 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1169 IR3_BARRIER_SHARED_W
;
1171 case nir_intrinsic_group_memory_barrier
:
1172 barrier
= ir3_FENCE(b
);
1173 barrier
->cat7
.g
= true;
1174 barrier
->cat7
.l
= true;
1175 barrier
->cat7
.r
= true;
1176 barrier
->cat7
.w
= true;
1177 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1178 IR3_BARRIER_IMAGE_W
|
1179 IR3_BARRIER_BUFFER_W
;
1180 barrier
->barrier_conflict
=
1181 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1182 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1183 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1189 /* make sure barrier doesn't get DCE'd */
1190 array_insert(b
, b
->keeps
, barrier
);
1193 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1194 gl_system_value slot
, unsigned compmask
,
1195 struct ir3_instruction
*instr
)
1197 struct ir3_shader_variant
*so
= ctx
->so
;
1198 unsigned r
= regid(so
->inputs_count
, 0);
1199 unsigned n
= so
->inputs_count
++;
1201 so
->inputs
[n
].sysval
= true;
1202 so
->inputs
[n
].slot
= slot
;
1203 so
->inputs
[n
].compmask
= compmask
;
1204 so
->inputs
[n
].regid
= r
;
1205 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1208 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1209 ctx
->ir
->inputs
[r
] = instr
;
1212 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1213 struct ir3_instruction
*instr
)
1215 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
1218 static struct ir3_instruction
*
1219 get_barycentric_centroid(struct ir3_context
*ctx
)
1221 if (!ctx
->ij_centroid
) {
1222 struct ir3_instruction
*xy
[2];
1223 struct ir3_instruction
*ij
;
1225 ij
= create_input_compmask(ctx
, 0, 0x3);
1226 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1228 ctx
->ij_centroid
= ir3_create_collect(ctx
, xy
, 2);
1230 add_sysval_input_compmask(ctx
,
1231 SYSTEM_VALUE_BARYCENTRIC_CENTROID
,
1235 return ctx
->ij_centroid
;
1238 static struct ir3_instruction
*
1239 get_barycentric_sample(struct ir3_context
*ctx
)
1241 if (!ctx
->ij_sample
) {
1242 struct ir3_instruction
*xy
[2];
1243 struct ir3_instruction
*ij
;
1245 ij
= create_input_compmask(ctx
, 0, 0x3);
1246 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1248 ctx
->ij_sample
= ir3_create_collect(ctx
, xy
, 2);
1250 add_sysval_input_compmask(ctx
,
1251 SYSTEM_VALUE_BARYCENTRIC_SAMPLE
,
1255 return ctx
->ij_sample
;
1258 static struct ir3_instruction
*
1259 get_barycentric_pixel(struct ir3_context
*ctx
)
1261 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1262 * this to create ij_pixel only on demand:
1264 return ctx
->ij_pixel
;
1267 static struct ir3_instruction
*
1268 get_frag_coord(struct ir3_context
*ctx
)
1270 if (!ctx
->frag_coord
) {
1271 struct ir3_block
*b
= ctx
->block
;
1272 struct ir3_instruction
*xyzw
[4];
1273 struct ir3_instruction
*hw_frag_coord
;
1275 hw_frag_coord
= create_input_compmask(ctx
, 0, 0xf);
1276 ir3_split_dest(ctx
->block
, xyzw
, hw_frag_coord
, 0, 4);
1278 /* for frag_coord.xy, we get unsigned values.. we need
1279 * to subtract (integer) 8 and divide by 16 (right-
1280 * shift by 4) then convert to float:
1284 * mov.u32f32 dst, tmp
1287 for (int i
= 0; i
< 2; i
++) {
1288 xyzw
[i
] = ir3_SUB_S(b
, xyzw
[i
], 0,
1289 create_immed(b
, 8), 0);
1290 xyzw
[i
] = ir3_SHR_B(b
, xyzw
[i
], 0,
1291 create_immed(b
, 4), 0);
1292 xyzw
[i
] = ir3_COV(b
, xyzw
[i
], TYPE_U32
, TYPE_F32
);
1295 ctx
->frag_coord
= ir3_create_collect(ctx
, xyzw
, 4);
1297 add_sysval_input_compmask(ctx
,
1298 SYSTEM_VALUE_FRAG_COORD
,
1299 0xf, hw_frag_coord
);
1301 ctx
->so
->frag_coord
= true;
1304 return ctx
->frag_coord
;
1308 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1310 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1311 struct ir3_instruction
**dst
;
1312 struct ir3_instruction
* const *src
;
1313 struct ir3_block
*b
= ctx
->block
;
1316 if (info
->has_dest
) {
1317 unsigned n
= nir_intrinsic_dest_components(intr
);
1318 dst
= ir3_get_dst(ctx
, &intr
->dest
, n
);
1323 const unsigned primitive_param
= ctx
->so
->shader
->const_state
.offsets
.primitive_param
* 4;
1324 const unsigned primitive_map
= ctx
->so
->shader
->const_state
.offsets
.primitive_map
* 4;
1326 switch (intr
->intrinsic
) {
1327 case nir_intrinsic_load_uniform
:
1328 idx
= nir_intrinsic_base(intr
);
1329 if (nir_src_is_const(intr
->src
[0])) {
1330 idx
+= nir_src_as_uint(intr
->src
[0]);
1331 for (int i
= 0; i
< intr
->num_components
; i
++) {
1332 dst
[i
] = create_uniform_typed(b
, idx
+ i
,
1333 nir_dest_bit_size(intr
->dest
) < 32 ? TYPE_F16
: TYPE_F32
);
1336 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1337 for (int i
= 0; i
< intr
->num_components
; i
++) {
1338 dst
[i
] = create_uniform_indirect(b
, idx
+ i
,
1339 ir3_get_addr(ctx
, src
[0], 1));
1341 /* NOTE: if relative addressing is used, we set
1342 * constlen in the compiler (to worst-case value)
1343 * since we don't know in the assembler what the max
1344 * addr reg value can be:
1346 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
1347 ctx
->so
->shader
->ubo_state
.size
/ 16);
1351 case nir_intrinsic_load_vs_primitive_stride_ir3
:
1352 dst
[0] = create_uniform(b
, primitive_param
+ 0);
1354 case nir_intrinsic_load_vs_vertex_stride_ir3
:
1355 dst
[0] = create_uniform(b
, primitive_param
+ 1);
1357 case nir_intrinsic_load_primitive_location_ir3
:
1358 idx
= nir_intrinsic_driver_location(intr
);
1359 dst
[0] = create_uniform(b
, primitive_map
+ idx
);
1362 case nir_intrinsic_load_gs_header_ir3
:
1363 dst
[0] = ctx
->gs_header
;
1366 case nir_intrinsic_load_primitive_id
:
1367 dst
[0] = ctx
->primitive_id
;
1370 case nir_intrinsic_load_ubo
:
1371 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1373 case nir_intrinsic_load_frag_coord
:
1374 ir3_split_dest(b
, dst
, get_frag_coord(ctx
), 0, 4);
1376 case nir_intrinsic_load_sample_pos_from_id
: {
1377 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1378 * but that doesn't seem necessary.
1380 struct ir3_instruction
*offset
=
1381 ir3_RGETPOS(b
, ir3_get_src(ctx
, &intr
->src
[0])[0], 0);
1382 offset
->regs
[0]->wrmask
= 0x3;
1383 offset
->cat5
.type
= TYPE_F32
;
1385 ir3_split_dest(b
, dst
, offset
, 0, 2);
1389 case nir_intrinsic_load_size_ir3
:
1390 if (!ctx
->ij_size
) {
1391 ctx
->ij_size
= create_input(ctx
, 0);
1393 add_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_SIZE
,
1396 dst
[0] = ctx
->ij_size
;
1398 case nir_intrinsic_load_barycentric_centroid
:
1399 ir3_split_dest(b
, dst
, get_barycentric_centroid(ctx
), 0, 2);
1401 case nir_intrinsic_load_barycentric_sample
:
1402 if (ctx
->so
->key
.msaa
) {
1403 ir3_split_dest(b
, dst
, get_barycentric_sample(ctx
), 0, 2);
1405 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1408 case nir_intrinsic_load_barycentric_pixel
:
1409 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1411 case nir_intrinsic_load_interpolated_input
:
1412 idx
= nir_intrinsic_base(intr
);
1413 comp
= nir_intrinsic_component(intr
);
1414 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1415 if (nir_src_is_const(intr
->src
[1])) {
1416 struct ir3_instruction
*coord
= ir3_create_collect(ctx
, src
, 2);
1417 idx
+= nir_src_as_uint(intr
->src
[1]);
1418 for (int i
= 0; i
< intr
->num_components
; i
++) {
1419 unsigned inloc
= idx
* 4 + i
+ comp
;
1420 if (ctx
->so
->inputs
[idx
].bary
&&
1421 !ctx
->so
->inputs
[idx
].use_ldlv
) {
1422 dst
[i
] = ir3_BARY_F(b
, create_immed(b
, inloc
), 0, coord
, 0);
1424 /* for non-varyings use the pre-setup input, since
1425 * that is easier than mapping things back to a
1426 * nir_variable to figure out what it is.
1428 dst
[i
] = ctx
->ir
->inputs
[inloc
];
1432 ir3_context_error(ctx
, "unhandled");
1435 case nir_intrinsic_load_input
:
1436 idx
= nir_intrinsic_base(intr
);
1437 comp
= nir_intrinsic_component(intr
);
1438 if (nir_src_is_const(intr
->src
[0])) {
1439 idx
+= nir_src_as_uint(intr
->src
[0]);
1440 for (int i
= 0; i
< intr
->num_components
; i
++) {
1441 unsigned n
= idx
* 4 + i
+ comp
;
1442 dst
[i
] = ctx
->ir
->inputs
[n
];
1443 compile_assert(ctx
, ctx
->ir
->inputs
[n
]);
1446 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1447 struct ir3_instruction
*collect
=
1448 ir3_create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1449 struct ir3_instruction
*addr
= ir3_get_addr(ctx
, src
[0], 4);
1450 for (int i
= 0; i
< intr
->num_components
; i
++) {
1451 unsigned n
= idx
* 4 + i
+ comp
;
1452 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1457 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1458 * pass and replaced by an ir3-specifc version that adds the
1459 * dword-offset in the last source.
1461 case nir_intrinsic_load_ssbo_ir3
:
1462 ctx
->funcs
->emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1464 case nir_intrinsic_store_ssbo_ir3
:
1465 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1466 !ctx
->s
->info
.fs
.early_fragment_tests
)
1467 ctx
->so
->no_earlyz
= true;
1468 ctx
->funcs
->emit_intrinsic_store_ssbo(ctx
, intr
);
1470 case nir_intrinsic_get_buffer_size
:
1471 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
1473 case nir_intrinsic_ssbo_atomic_add_ir3
:
1474 case nir_intrinsic_ssbo_atomic_imin_ir3
:
1475 case nir_intrinsic_ssbo_atomic_umin_ir3
:
1476 case nir_intrinsic_ssbo_atomic_imax_ir3
:
1477 case nir_intrinsic_ssbo_atomic_umax_ir3
:
1478 case nir_intrinsic_ssbo_atomic_and_ir3
:
1479 case nir_intrinsic_ssbo_atomic_or_ir3
:
1480 case nir_intrinsic_ssbo_atomic_xor_ir3
:
1481 case nir_intrinsic_ssbo_atomic_exchange_ir3
:
1482 case nir_intrinsic_ssbo_atomic_comp_swap_ir3
:
1483 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1484 !ctx
->s
->info
.fs
.early_fragment_tests
)
1485 ctx
->so
->no_earlyz
= true;
1486 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_ssbo(ctx
, intr
);
1488 case nir_intrinsic_load_shared
:
1489 emit_intrinsic_load_shared(ctx
, intr
, dst
);
1491 case nir_intrinsic_store_shared
:
1492 emit_intrinsic_store_shared(ctx
, intr
);
1494 case nir_intrinsic_shared_atomic_add
:
1495 case nir_intrinsic_shared_atomic_imin
:
1496 case nir_intrinsic_shared_atomic_umin
:
1497 case nir_intrinsic_shared_atomic_imax
:
1498 case nir_intrinsic_shared_atomic_umax
:
1499 case nir_intrinsic_shared_atomic_and
:
1500 case nir_intrinsic_shared_atomic_or
:
1501 case nir_intrinsic_shared_atomic_xor
:
1502 case nir_intrinsic_shared_atomic_exchange
:
1503 case nir_intrinsic_shared_atomic_comp_swap
:
1504 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
1506 case nir_intrinsic_image_deref_load
:
1507 emit_intrinsic_load_image(ctx
, intr
, dst
);
1509 case nir_intrinsic_image_deref_store
:
1510 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1511 !ctx
->s
->info
.fs
.early_fragment_tests
)
1512 ctx
->so
->no_earlyz
= true;
1513 ctx
->funcs
->emit_intrinsic_store_image(ctx
, intr
);
1515 case nir_intrinsic_image_deref_size
:
1516 emit_intrinsic_image_size(ctx
, intr
, dst
);
1518 case nir_intrinsic_image_deref_atomic_add
:
1519 case nir_intrinsic_image_deref_atomic_imin
:
1520 case nir_intrinsic_image_deref_atomic_umin
:
1521 case nir_intrinsic_image_deref_atomic_imax
:
1522 case nir_intrinsic_image_deref_atomic_umax
:
1523 case nir_intrinsic_image_deref_atomic_and
:
1524 case nir_intrinsic_image_deref_atomic_or
:
1525 case nir_intrinsic_image_deref_atomic_xor
:
1526 case nir_intrinsic_image_deref_atomic_exchange
:
1527 case nir_intrinsic_image_deref_atomic_comp_swap
:
1528 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1529 !ctx
->s
->info
.fs
.early_fragment_tests
)
1530 ctx
->so
->no_earlyz
= true;
1531 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_image(ctx
, intr
);
1533 case nir_intrinsic_barrier
:
1534 case nir_intrinsic_memory_barrier
:
1535 case nir_intrinsic_group_memory_barrier
:
1536 case nir_intrinsic_memory_barrier_atomic_counter
:
1537 case nir_intrinsic_memory_barrier_buffer
:
1538 case nir_intrinsic_memory_barrier_image
:
1539 case nir_intrinsic_memory_barrier_shared
:
1540 emit_intrinsic_barrier(ctx
, intr
);
1541 /* note that blk ptr no longer valid, make that obvious: */
1544 case nir_intrinsic_store_output
:
1545 idx
= nir_intrinsic_base(intr
);
1546 comp
= nir_intrinsic_component(intr
);
1547 compile_assert(ctx
, nir_src_is_const(intr
->src
[1]));
1548 idx
+= nir_src_as_uint(intr
->src
[1]);
1550 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1551 for (int i
= 0; i
< intr
->num_components
; i
++) {
1552 unsigned n
= idx
* 4 + i
+ comp
;
1553 ctx
->ir
->outputs
[n
] = src
[i
];
1556 case nir_intrinsic_load_base_vertex
:
1557 case nir_intrinsic_load_first_vertex
:
1558 if (!ctx
->basevertex
) {
1559 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1560 add_sysval_input(ctx
, SYSTEM_VALUE_FIRST_VERTEX
, ctx
->basevertex
);
1562 dst
[0] = ctx
->basevertex
;
1564 case nir_intrinsic_load_vertex_id_zero_base
:
1565 case nir_intrinsic_load_vertex_id
:
1566 if (!ctx
->vertex_id
) {
1567 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
1568 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
1569 ctx
->vertex_id
= create_input(ctx
, 0);
1570 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
1572 dst
[0] = ctx
->vertex_id
;
1574 case nir_intrinsic_load_instance_id
:
1575 if (!ctx
->instance_id
) {
1576 ctx
->instance_id
= create_input(ctx
, 0);
1577 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1580 dst
[0] = ctx
->instance_id
;
1582 case nir_intrinsic_load_sample_id
:
1583 ctx
->so
->per_samp
= true;
1585 case nir_intrinsic_load_sample_id_no_per_sample
:
1586 if (!ctx
->samp_id
) {
1587 ctx
->samp_id
= create_input(ctx
, 0);
1588 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
1589 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
,
1592 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
1594 case nir_intrinsic_load_sample_mask_in
:
1595 if (!ctx
->samp_mask_in
) {
1596 ctx
->samp_mask_in
= create_input(ctx
, 0);
1597 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
,
1600 dst
[0] = ctx
->samp_mask_in
;
1602 case nir_intrinsic_load_user_clip_plane
:
1603 idx
= nir_intrinsic_ucp_id(intr
);
1604 for (int i
= 0; i
< intr
->num_components
; i
++) {
1605 unsigned n
= idx
* 4 + i
;
1606 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1609 case nir_intrinsic_load_front_face
:
1610 if (!ctx
->frag_face
) {
1611 ctx
->so
->frag_face
= true;
1612 ctx
->frag_face
= create_input(ctx
, 0);
1613 add_sysval_input(ctx
, SYSTEM_VALUE_FRONT_FACE
, ctx
->frag_face
);
1614 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1616 /* for fragface, we get -1 for back and 0 for front. However this is
1617 * the inverse of what nir expects (where ~0 is true).
1619 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
1620 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
1622 case nir_intrinsic_load_local_invocation_id
:
1623 if (!ctx
->local_invocation_id
) {
1624 ctx
->local_invocation_id
= create_input_compmask(ctx
, 0, 0x7);
1625 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
1626 0x7, ctx
->local_invocation_id
);
1628 ir3_split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
1630 case nir_intrinsic_load_work_group_id
:
1631 if (!ctx
->work_group_id
) {
1632 ctx
->work_group_id
= create_input_compmask(ctx
, 0, 0x7);
1633 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
1634 0x7, ctx
->work_group_id
);
1635 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
1637 ir3_split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
1639 case nir_intrinsic_load_num_work_groups
:
1640 for (int i
= 0; i
< intr
->num_components
; i
++) {
1641 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
1644 case nir_intrinsic_load_local_group_size
:
1645 for (int i
= 0; i
< intr
->num_components
; i
++) {
1646 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
1649 case nir_intrinsic_discard_if
:
1650 case nir_intrinsic_discard
: {
1651 struct ir3_instruction
*cond
, *kill
;
1653 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1654 /* conditional discard: */
1655 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1656 cond
= ir3_b2n(b
, src
[0]);
1658 /* unconditional discard: */
1659 cond
= create_immed(b
, 1);
1662 /* NOTE: only cmps.*.* can write p0.x: */
1663 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1664 cond
->cat2
.condition
= IR3_COND_NE
;
1666 /* condition always goes in predicate register: */
1667 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1669 kill
= ir3_KILL(b
, cond
, 0);
1670 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1672 array_insert(b
, b
->keeps
, kill
);
1673 ctx
->so
->no_earlyz
= true;
1677 case nir_intrinsic_load_shared_ir3
:
1678 emit_intrinsic_load_shared_ir3(ctx
, intr
, dst
);
1680 case nir_intrinsic_store_shared_ir3
:
1681 emit_intrinsic_store_shared_ir3(ctx
, intr
);
1684 ir3_context_error(ctx
, "Unhandled intrinsic type: %s\n",
1685 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1690 ir3_put_dst(ctx
, &intr
->dest
);
1694 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
1696 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &instr
->def
,
1697 instr
->def
.num_components
);
1699 if (instr
->def
.bit_size
< 32) {
1700 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1701 dst
[i
] = create_immed_typed(ctx
->block
,
1702 instr
->value
[i
].u16
,
1705 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1706 dst
[i
] = create_immed_typed(ctx
->block
,
1707 instr
->value
[i
].u32
,
1714 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
1716 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &undef
->def
,
1717 undef
->def
.num_components
);
1718 type_t type
= (undef
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
1720 /* backend doesn't want undefined instructions, so just plug
1723 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1724 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
1728 * texture fetch/sample instructions:
1732 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1734 unsigned coords
, flags
= 0;
1736 /* note: would use tex->coord_components.. except txs.. also,
1737 * since array index goes after shadow ref, we don't want to
1740 switch (tex
->sampler_dim
) {
1741 case GLSL_SAMPLER_DIM_1D
:
1742 case GLSL_SAMPLER_DIM_BUF
:
1745 case GLSL_SAMPLER_DIM_2D
:
1746 case GLSL_SAMPLER_DIM_RECT
:
1747 case GLSL_SAMPLER_DIM_EXTERNAL
:
1748 case GLSL_SAMPLER_DIM_MS
:
1751 case GLSL_SAMPLER_DIM_3D
:
1752 case GLSL_SAMPLER_DIM_CUBE
:
1754 flags
|= IR3_INSTR_3D
;
1757 unreachable("bad sampler_dim");
1760 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1761 flags
|= IR3_INSTR_S
;
1763 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1764 flags
|= IR3_INSTR_A
;
1770 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1771 * or immediate (in which case it will get lowered later to a non .s2en
1772 * version of the tex instruction which encode tex/samp as immediates:
1774 static struct ir3_instruction
*
1775 get_tex_samp_tex_src(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1777 int texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
);
1778 int sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
);
1779 struct ir3_instruction
*texture
, *sampler
;
1781 if (texture_idx
>= 0) {
1782 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
1783 texture
= ir3_COV(ctx
->block
, texture
, TYPE_U32
, TYPE_U16
);
1785 /* TODO what to do for dynamic case? I guess we only need the
1786 * max index for astc srgb workaround so maybe not a problem
1787 * to worry about if we don't enable indirect samplers for
1790 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex
->texture_index
);
1791 texture
= create_immed_typed(ctx
->block
, tex
->texture_index
, TYPE_U16
);
1794 if (sampler_idx
>= 0) {
1795 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
1796 sampler
= ir3_COV(ctx
->block
, sampler
, TYPE_U32
, TYPE_U16
);
1798 sampler
= create_immed_typed(ctx
->block
, tex
->sampler_index
, TYPE_U16
);
1801 return ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1808 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1810 struct ir3_block
*b
= ctx
->block
;
1811 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1812 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
1813 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
1814 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1815 unsigned i
, coords
, flags
, ncomp
;
1816 unsigned nsrc0
= 0, nsrc1
= 0;
1820 ncomp
= nir_dest_num_components(tex
->dest
);
1822 coord
= off
= ddx
= ddy
= NULL
;
1823 lod
= proj
= compare
= sample_index
= NULL
;
1825 dst
= ir3_get_dst(ctx
, &tex
->dest
, ncomp
);
1827 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1828 switch (tex
->src
[i
].src_type
) {
1829 case nir_tex_src_coord
:
1830 coord
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1832 case nir_tex_src_bias
:
1833 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1836 case nir_tex_src_lod
:
1837 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1840 case nir_tex_src_comparator
: /* shadow comparator */
1841 compare
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1843 case nir_tex_src_projector
:
1844 proj
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1847 case nir_tex_src_offset
:
1848 off
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1851 case nir_tex_src_ddx
:
1852 ddx
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1854 case nir_tex_src_ddy
:
1855 ddy
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1857 case nir_tex_src_ms_index
:
1858 sample_index
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1860 case nir_tex_src_texture_offset
:
1861 case nir_tex_src_sampler_offset
:
1862 /* handled in get_tex_samp_src() */
1865 ir3_context_error(ctx
, "Unhandled NIR tex src type: %d\n",
1866 tex
->src
[i
].src_type
);
1872 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
1873 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1874 case nir_texop_txl
: opc
= OPC_SAML
; break;
1875 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1876 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1877 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
1879 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1880 * what blob does, seems gather is broken?), and a3xx did
1881 * not support it (but probably could also emulate).
1883 switch (tex
->component
) {
1884 case 0: opc
= OPC_GATHER4R
; break;
1885 case 1: opc
= OPC_GATHER4G
; break;
1886 case 2: opc
= OPC_GATHER4B
; break;
1887 case 3: opc
= OPC_GATHER4A
; break;
1890 case nir_texop_txf_ms_fb
:
1891 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
1893 ir3_context_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1897 tex_info(tex
, &flags
, &coords
);
1900 * lay out the first argument in the proper order:
1901 * - actual coordinates first
1902 * - shadow reference
1905 * - starting at offset 4, dpdx.xy, dpdy.xy
1907 * bias/lod go into the second arg
1910 /* insert tex coords: */
1911 for (i
= 0; i
< coords
; i
++)
1916 /* scale up integer coords for TXF based on the LOD */
1917 if (ctx
->compiler
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1919 for (i
= 0; i
< coords
; i
++)
1920 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
1924 /* hw doesn't do 1d, so we treat it as 2d with
1925 * height of 1, and patch up the y coord.
1928 src0
[nsrc0
++] = create_immed(b
, 0);
1930 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1934 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1935 src0
[nsrc0
++] = compare
;
1937 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
1938 struct ir3_instruction
*idx
= coord
[coords
];
1940 /* the array coord for cube arrays needs 0.5 added to it */
1941 if (ctx
->compiler
->array_index_add_half
&& !is_isam(opc
))
1942 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
1944 src0
[nsrc0
++] = idx
;
1948 src0
[nsrc0
++] = proj
;
1949 flags
|= IR3_INSTR_P
;
1952 /* pad to 4, then ddx/ddy: */
1953 if (tex
->op
== nir_texop_txd
) {
1955 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1956 for (i
= 0; i
< coords
; i
++)
1957 src0
[nsrc0
++] = ddx
[i
];
1959 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1960 for (i
= 0; i
< coords
; i
++)
1961 src0
[nsrc0
++] = ddy
[i
];
1963 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1966 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1967 * with scaled x coord according to requested sample:
1969 if (opc
== OPC_ISAMM
) {
1970 if (ctx
->compiler
->txf_ms_with_isaml
) {
1971 /* the samples are laid out in x dimension as
1973 * x_ms = (x << ms) + sample_index;
1975 struct ir3_instruction
*ms
;
1976 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
1978 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
1979 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
1983 src0
[nsrc0
++] = sample_index
;
1988 * second argument (if applicable):
1993 if (has_off
| has_lod
| has_bias
) {
1995 unsigned off_coords
= coords
;
1996 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1998 for (i
= 0; i
< off_coords
; i
++)
1999 src1
[nsrc1
++] = off
[i
];
2001 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2002 flags
|= IR3_INSTR_O
;
2005 if (has_lod
| has_bias
)
2006 src1
[nsrc1
++] = lod
;
2009 switch (tex
->dest_type
) {
2010 case nir_type_invalid
:
2011 case nir_type_float
:
2022 unreachable("bad dest_type");
2025 if (opc
== OPC_GETLOD
)
2028 struct ir3_instruction
*samp_tex
;
2030 if (tex
->op
== nir_texop_txf_ms_fb
) {
2031 /* only expect a single txf_ms_fb per shader: */
2032 compile_assert(ctx
, !ctx
->so
->fb_read
);
2033 compile_assert(ctx
, ctx
->so
->type
== MESA_SHADER_FRAGMENT
);
2035 ctx
->so
->fb_read
= true;
2036 samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2037 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2038 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2041 ctx
->so
->num_samp
++;
2043 samp_tex
= get_tex_samp_tex_src(ctx
, tex
);
2046 struct ir3_instruction
*col0
= ir3_create_collect(ctx
, src0
, nsrc0
);
2047 struct ir3_instruction
*col1
= ir3_create_collect(ctx
, src1
, nsrc1
);
2049 sam
= ir3_SAM(b
, opc
, type
, MASK(ncomp
), flags
,
2050 samp_tex
, col0
, col1
);
2052 if ((ctx
->astc_srgb
& (1 << tex
->texture_index
)) && !nir_tex_instr_is_query(tex
)) {
2053 /* only need first 3 components: */
2054 sam
->regs
[0]->wrmask
= 0x7;
2055 ir3_split_dest(b
, dst
, sam
, 0, 3);
2057 /* we need to sample the alpha separately with a non-ASTC
2060 sam
= ir3_SAM(b
, opc
, type
, 0b1000, flags
,
2061 samp_tex
, col0
, col1
);
2063 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2065 /* fixup .w component: */
2066 ir3_split_dest(b
, &dst
[3], sam
, 3, 1);
2068 /* normal (non-workaround) case: */
2069 ir3_split_dest(b
, dst
, sam
, 0, ncomp
);
2072 /* GETLOD returns results in 4.8 fixed point */
2073 if (opc
== OPC_GETLOD
) {
2074 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2076 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2077 for (i
= 0; i
< 2; i
++) {
2078 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_S32
, TYPE_F32
), 0,
2083 ir3_put_dst(ctx
, &tex
->dest
);
2087 emit_tex_info(struct ir3_context
*ctx
, nir_tex_instr
*tex
, unsigned idx
)
2089 struct ir3_block
*b
= ctx
->block
;
2090 struct ir3_instruction
**dst
, *sam
;
2092 dst
= ir3_get_dst(ctx
, &tex
->dest
, 1);
2094 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, 1 << idx
, 0,
2095 get_tex_samp_tex_src(ctx
, tex
), NULL
, NULL
);
2097 /* even though there is only one component, since it ends
2098 * up in .y/.z/.w rather than .x, we need a split_dest()
2101 ir3_split_dest(b
, dst
, sam
, 0, idx
+ 1);
2103 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2104 * the value in TEX_CONST_0 is zero-based.
2106 if (ctx
->compiler
->levels_add_one
)
2107 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2109 ir3_put_dst(ctx
, &tex
->dest
);
2113 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2115 struct ir3_block
*b
= ctx
->block
;
2116 struct ir3_instruction
**dst
, *sam
;
2117 struct ir3_instruction
*lod
;
2118 unsigned flags
, coords
;
2120 tex_info(tex
, &flags
, &coords
);
2122 /* Actually we want the number of dimensions, not coordinates. This
2123 * distinction only matters for cubes.
2125 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2128 dst
= ir3_get_dst(ctx
, &tex
->dest
, 4);
2130 compile_assert(ctx
, tex
->num_srcs
== 1);
2131 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2133 lod
= ir3_get_src(ctx
, &tex
->src
[0].src
)[0];
2135 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, 0b1111, flags
,
2136 get_tex_samp_tex_src(ctx
, tex
), lod
, NULL
);
2138 ir3_split_dest(b
, dst
, sam
, 0, 4);
2140 /* Array size actually ends up in .w rather than .z. This doesn't
2141 * matter for miplevel 0, but for higher mips the value in z is
2142 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2143 * returned, which means that we have to add 1 to it for arrays.
2145 if (tex
->is_array
) {
2146 if (ctx
->compiler
->levels_add_one
) {
2147 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2149 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2153 ir3_put_dst(ctx
, &tex
->dest
);
2157 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2159 switch (jump
->type
) {
2160 case nir_jump_break
:
2161 case nir_jump_continue
:
2162 case nir_jump_return
:
2163 /* I *think* we can simply just ignore this, and use the
2164 * successor block link to figure out where we need to
2165 * jump to for break/continue
2169 ir3_context_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2175 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2177 switch (instr
->type
) {
2178 case nir_instr_type_alu
:
2179 emit_alu(ctx
, nir_instr_as_alu(instr
));
2181 case nir_instr_type_deref
:
2182 /* ignored, handled as part of the intrinsic they are src to */
2184 case nir_instr_type_intrinsic
:
2185 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2187 case nir_instr_type_load_const
:
2188 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2190 case nir_instr_type_ssa_undef
:
2191 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2193 case nir_instr_type_tex
: {
2194 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2195 /* couple tex instructions get special-cased:
2199 emit_tex_txs(ctx
, tex
);
2201 case nir_texop_query_levels
:
2202 emit_tex_info(ctx
, tex
, 2);
2204 case nir_texop_texture_samples
:
2205 emit_tex_info(ctx
, tex
, 3);
2213 case nir_instr_type_jump
:
2214 emit_jump(ctx
, nir_instr_as_jump(instr
));
2216 case nir_instr_type_phi
:
2217 /* we have converted phi webs to regs in NIR by now */
2218 ir3_context_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2220 case nir_instr_type_call
:
2221 case nir_instr_type_parallel_copy
:
2222 ir3_context_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2227 static struct ir3_block
*
2228 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2230 struct ir3_block
*block
;
2231 struct hash_entry
*hentry
;
2233 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2235 return hentry
->data
;
2237 block
= ir3_block_create(ctx
->ir
);
2238 block
->nblock
= nblock
;
2239 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2241 block
->predecessors
= _mesa_pointer_set_create(block
);
2242 set_foreach(nblock
->predecessors
, sentry
) {
2243 _mesa_set_add(block
->predecessors
, get_block(ctx
, sentry
->key
));
2250 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2252 struct ir3_block
*block
= get_block(ctx
, nblock
);
2254 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2255 if (nblock
->successors
[i
]) {
2256 block
->successors
[i
] =
2257 get_block(ctx
, nblock
->successors
[i
]);
2262 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2264 /* re-emit addr register in each block if needed: */
2265 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
2266 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
2267 ctx
->addr_ht
[i
] = NULL
;
2270 nir_foreach_instr(instr
, nblock
) {
2271 ctx
->cur_instr
= instr
;
2272 emit_instr(ctx
, instr
);
2273 ctx
->cur_instr
= NULL
;
2279 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2282 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2284 struct ir3_instruction
*condition
= ir3_get_src(ctx
, &nif
->condition
)[0];
2286 ctx
->block
->condition
=
2287 ir3_get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2289 emit_cf_list(ctx
, &nif
->then_list
);
2290 emit_cf_list(ctx
, &nif
->else_list
);
2294 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2296 emit_cf_list(ctx
, &nloop
->body
);
2301 stack_push(struct ir3_context
*ctx
)
2304 ctx
->max_stack
= MAX2(ctx
->max_stack
, ctx
->stack
);
2308 stack_pop(struct ir3_context
*ctx
)
2310 compile_assert(ctx
, ctx
->stack
> 0);
2315 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2317 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2318 switch (node
->type
) {
2319 case nir_cf_node_block
:
2320 emit_block(ctx
, nir_cf_node_as_block(node
));
2322 case nir_cf_node_if
:
2324 emit_if(ctx
, nir_cf_node_as_if(node
));
2327 case nir_cf_node_loop
:
2329 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2332 case nir_cf_node_function
:
2333 ir3_context_error(ctx
, "TODO\n");
2339 /* emit stream-out code. At this point, the current block is the original
2340 * (nir) end block, and nir ensures that all flow control paths terminate
2341 * into the end block. We re-purpose the original end block to generate
2342 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2343 * block holding stream-out write instructions, followed by the new end
2347 * p0.x = (vtxcnt < maxvtxcnt)
2348 * // succs: blockStreamOut, blockNewEnd
2351 * ... stream-out instructions ...
2352 * // succs: blockNewEnd
2358 emit_stream_out(struct ir3_context
*ctx
)
2360 struct ir3
*ir
= ctx
->ir
;
2361 struct ir3_stream_output_info
*strmout
=
2362 &ctx
->so
->shader
->stream_output
;
2363 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2364 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2365 struct ir3_instruction
*bases
[IR3_MAX_SO_BUFFERS
];
2367 /* create vtxcnt input in input block at top of shader,
2368 * so that it is seen as live over the entire duration
2371 vtxcnt
= create_input(ctx
, 0);
2372 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2374 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2376 /* at this point, we are at the original 'end' block,
2377 * re-purpose this block to stream-out condition, then
2378 * append stream-out block and new-end block
2380 orig_end_block
= ctx
->block
;
2382 // TODO these blocks need to update predecessors..
2383 // maybe w/ store_global intrinsic, we could do this
2384 // stuff in nir->nir pass
2386 stream_out_block
= ir3_block_create(ir
);
2387 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2389 new_end_block
= ir3_block_create(ir
);
2390 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2392 orig_end_block
->successors
[0] = stream_out_block
;
2393 orig_end_block
->successors
[1] = new_end_block
;
2394 stream_out_block
->successors
[0] = new_end_block
;
2396 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2397 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2398 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2399 cond
->cat2
.condition
= IR3_COND_LT
;
2401 /* condition goes on previous block to the conditional,
2402 * since it is used to pick which of the two successor
2405 orig_end_block
->condition
= cond
;
2407 /* switch to stream_out_block to generate the stream-out
2410 ctx
->block
= stream_out_block
;
2412 /* Calculate base addresses based on vtxcnt. Instructions
2413 * generated for bases not used in following loop will be
2414 * stripped out in the backend.
2416 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2417 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
2418 unsigned stride
= strmout
->stride
[i
];
2419 struct ir3_instruction
*base
, *off
;
2421 base
= create_uniform(ctx
->block
, regid(const_state
->offsets
.tfbo
, i
));
2423 /* 24-bit should be enough: */
2424 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2425 create_immed(ctx
->block
, stride
* 4), 0);
2427 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2430 /* Generate the per-output store instructions: */
2431 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2432 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2433 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2434 struct ir3_instruction
*base
, *out
, *stg
;
2436 base
= bases
[strmout
->output
[i
].output_buffer
];
2437 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2439 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2440 create_immed(ctx
->block
, 1), 0);
2441 stg
->cat6
.type
= TYPE_U32
;
2442 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2444 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2448 /* and finally switch to the new_end_block: */
2449 ctx
->block
= new_end_block
;
2453 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2455 nir_metadata_require(impl
, nir_metadata_block_index
);
2457 compile_assert(ctx
, ctx
->stack
== 0);
2459 emit_cf_list(ctx
, &impl
->body
);
2460 emit_block(ctx
, impl
->end_block
);
2462 compile_assert(ctx
, ctx
->stack
== 0);
2464 /* at this point, we should have a single empty block,
2465 * into which we emit the 'end' instruction.
2467 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2469 /* If stream-out (aka transform-feedback) enabled, emit the
2470 * stream-out instructions, followed by a new empty block (into
2471 * which the 'end' instruction lands).
2473 * NOTE: it is done in this order, rather than inserting before
2474 * we emit end_block, because NIR guarantees that all blocks
2475 * flow into end_block, and that end_block has no successors.
2476 * So by re-purposing end_block as the first block of stream-
2477 * out, we guarantee that all exit paths flow into the stream-
2480 if ((ctx
->compiler
->gpu_id
< 500) &&
2481 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2482 !ctx
->so
->binning_pass
) {
2483 debug_assert(ctx
->so
->type
== MESA_SHADER_VERTEX
);
2484 emit_stream_out(ctx
);
2487 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2488 * NOP and has an epilogue that writes the VS outputs to local storage, to
2489 * be read by the HS. Then it resets execution mask (chmask) and chains
2490 * to the next shader (chsh).
2492 if (ctx
->so
->type
== MESA_SHADER_VERTEX
&& ctx
->so
->key
.has_gs
) {
2493 struct ir3_instruction
*chmask
=
2494 ir3_CHMASK(ctx
->block
);
2495 chmask
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2496 chmask
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2498 struct ir3_instruction
*chsh
=
2499 ir3_CHSH(ctx
->block
);
2500 chsh
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2501 chsh
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2503 ir3_END(ctx
->block
);
2508 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2510 struct ir3_shader_variant
*so
= ctx
->so
;
2511 unsigned ncomp
= glsl_get_components(in
->type
);
2512 unsigned n
= in
->data
.driver_location
;
2513 unsigned frac
= in
->data
.location_frac
;
2514 unsigned slot
= in
->data
.location
;
2516 /* Inputs are loaded using ldlw or ldg for these stages. */
2517 if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
||
2518 ctx
->so
->type
== MESA_SHADER_TESS_EVAL
||
2519 ctx
->so
->type
== MESA_SHADER_GEOMETRY
)
2522 /* skip unread inputs, we could end up with (for example), unsplit
2523 * matrix/etc inputs in the case they are not read, so just silently
2529 so
->inputs
[n
].slot
= slot
;
2530 so
->inputs
[n
].compmask
= (1 << (ncomp
+ frac
)) - 1;
2531 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2532 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2534 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2536 /* if any varyings have 'sample' qualifer, that triggers us
2537 * to run in per-sample mode:
2539 so
->per_samp
|= in
->data
.sample
;
2541 for (int i
= 0; i
< ncomp
; i
++) {
2542 struct ir3_instruction
*instr
= NULL
;
2543 unsigned idx
= (n
* 4) + i
+ frac
;
2545 if (slot
== VARYING_SLOT_POS
) {
2546 ir3_context_error(ctx
, "fragcoord should be a sysval!\n");
2547 } else if (slot
== VARYING_SLOT_PNTC
) {
2548 /* see for example st_nir_fixup_varying_slots().. this is
2549 * maybe a bit mesa/st specific. But we need things to line
2550 * up for this in fdN_program:
2551 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2552 * if (emit->sprite_coord_enable & texmask) {
2556 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2557 so
->inputs
[n
].bary
= true;
2558 instr
= create_frag_input(ctx
, false, idx
);
2560 /* detect the special case for front/back colors where
2561 * we need to do flat vs smooth shading depending on
2564 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2566 case VARYING_SLOT_COL0
:
2567 case VARYING_SLOT_COL1
:
2568 case VARYING_SLOT_BFC0
:
2569 case VARYING_SLOT_BFC1
:
2570 so
->inputs
[n
].rasterflat
= true;
2577 if (ctx
->compiler
->flat_bypass
) {
2578 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2579 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2580 so
->inputs
[n
].use_ldlv
= true;
2583 so
->inputs
[n
].bary
= true;
2585 instr
= create_frag_input(ctx
, so
->inputs
[n
].use_ldlv
, idx
);
2588 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2590 ctx
->ir
->inputs
[idx
] = instr
;
2592 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
2593 for (int i
= 0; i
< ncomp
; i
++) {
2594 unsigned idx
= (n
* 4) + i
+ frac
;
2595 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2596 ctx
->ir
->inputs
[idx
] = create_input(ctx
, idx
);
2599 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2602 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== MESA_SHADER_VERTEX
)) {
2603 so
->total_in
+= ncomp
;
2607 /* Initially we assign non-packed inloc's for varyings, as we don't really
2608 * know up-front which components will be unused. After all the compilation
2609 * stages we scan the shader to see which components are actually used, and
2610 * re-pack the inlocs to eliminate unneeded varyings.
2613 pack_inlocs(struct ir3_context
*ctx
)
2615 struct ir3_shader_variant
*so
= ctx
->so
;
2616 uint8_t used_components
[so
->inputs_count
];
2618 memset(used_components
, 0, sizeof(used_components
));
2621 * First Step: scan shader to find which bary.f/ldlv remain:
2624 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2625 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
2626 if (is_input(instr
)) {
2627 unsigned inloc
= instr
->regs
[1]->iim_val
;
2628 unsigned i
= inloc
/ 4;
2629 unsigned j
= inloc
% 4;
2631 compile_assert(ctx
, instr
->regs
[1]->flags
& IR3_REG_IMMED
);
2632 compile_assert(ctx
, i
< so
->inputs_count
);
2634 used_components
[i
] |= 1 << j
;
2640 * Second Step: reassign varying inloc/slots:
2643 unsigned actual_in
= 0;
2646 for (unsigned i
= 0; i
< so
->inputs_count
; i
++) {
2647 unsigned compmask
= 0, maxcomp
= 0;
2649 so
->inputs
[i
].inloc
= inloc
;
2650 so
->inputs
[i
].bary
= false;
2652 for (unsigned j
= 0; j
< 4; j
++) {
2653 if (!(used_components
[i
] & (1 << j
)))
2656 compmask
|= (1 << j
);
2660 /* at this point, since used_components[i] mask is only
2661 * considering varyings (ie. not sysvals) we know this
2664 so
->inputs
[i
].bary
= true;
2667 if (so
->inputs
[i
].bary
) {
2669 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
2675 * Third Step: reassign packed inloc's:
2678 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2679 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
2680 if (is_input(instr
)) {
2681 unsigned inloc
= instr
->regs
[1]->iim_val
;
2682 unsigned i
= inloc
/ 4;
2683 unsigned j
= inloc
% 4;
2685 instr
->regs
[1]->iim_val
= so
->inputs
[i
].inloc
+ j
;
2692 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
2694 struct ir3_shader_variant
*so
= ctx
->so
;
2695 unsigned ncomp
= glsl_get_components(out
->type
);
2696 unsigned n
= out
->data
.driver_location
;
2697 unsigned frac
= out
->data
.location_frac
;
2698 unsigned slot
= out
->data
.location
;
2701 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2703 case FRAG_RESULT_DEPTH
:
2704 comp
= 2; /* tgsi will write to .z component */
2705 so
->writes_pos
= true;
2707 case FRAG_RESULT_COLOR
:
2710 case FRAG_RESULT_SAMPLE_MASK
:
2711 so
->writes_smask
= true;
2714 if (slot
>= FRAG_RESULT_DATA0
)
2716 ir3_context_error(ctx
, "unknown FS output name: %s\n",
2717 gl_frag_result_name(slot
));
2719 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
2720 ctx
->so
->type
== MESA_SHADER_GEOMETRY
) {
2722 case VARYING_SLOT_POS
:
2723 so
->writes_pos
= true;
2725 case VARYING_SLOT_PSIZ
:
2726 so
->writes_psize
= true;
2728 case VARYING_SLOT_PRIMITIVE_ID
:
2729 case VARYING_SLOT_LAYER
:
2730 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3
:
2731 debug_assert(ctx
->so
->type
== MESA_SHADER_GEOMETRY
);
2733 case VARYING_SLOT_COL0
:
2734 case VARYING_SLOT_COL1
:
2735 case VARYING_SLOT_BFC0
:
2736 case VARYING_SLOT_BFC1
:
2737 case VARYING_SLOT_FOGC
:
2738 case VARYING_SLOT_CLIP_DIST0
:
2739 case VARYING_SLOT_CLIP_DIST1
:
2740 case VARYING_SLOT_CLIP_VERTEX
:
2743 if (slot
>= VARYING_SLOT_VAR0
)
2745 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2747 ir3_context_error(ctx
, "unknown %s shader output name: %s\n",
2748 _mesa_shader_stage_to_string(ctx
->so
->type
),
2749 gl_varying_slot_name(slot
));
2752 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2755 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2757 so
->outputs
[n
].slot
= slot
;
2758 so
->outputs
[n
].regid
= regid(n
, comp
);
2759 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2761 for (int i
= 0; i
< ncomp
; i
++) {
2762 unsigned idx
= (n
* 4) + i
+ frac
;
2763 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
2764 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2767 /* if varying packing doesn't happen, we could end up in a situation
2768 * with "holes" in the output, and since the per-generation code that
2769 * sets up varying linkage registers doesn't expect to have more than
2770 * one varying per vec4 slot, pad the holes.
2772 * Note that this should probably generate a performance warning of
2775 for (int i
= 0; i
< frac
; i
++) {
2776 unsigned idx
= (n
* 4) + i
;
2777 if (!ctx
->ir
->outputs
[idx
]) {
2778 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2784 max_drvloc(struct exec_list
*vars
)
2787 nir_foreach_variable(var
, vars
) {
2788 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
2793 static const unsigned max_sysvals
[] = {
2794 [MESA_SHADER_VERTEX
] = 16,
2795 [MESA_SHADER_GEOMETRY
] = 16,
2796 [MESA_SHADER_FRAGMENT
] = 24, // TODO
2797 [MESA_SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
2798 [MESA_SHADER_KERNEL
] = 16, // TODO how many do we actually need?
2802 emit_instructions(struct ir3_context
*ctx
)
2804 unsigned ninputs
, noutputs
;
2805 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
2807 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
2808 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
2810 /* we need to leave room for sysvals:
2812 ninputs
+= max_sysvals
[ctx
->so
->type
];
2813 if (ctx
->so
->type
== MESA_SHADER_VERTEX
)
2814 noutputs
+= 8; /* gs or tess header + primitive_id */
2816 ctx
->ir
= ir3_create(ctx
->compiler
, ctx
->so
->type
, ninputs
, noutputs
);
2818 /* Create inputs in first block: */
2819 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2820 ctx
->in_block
= ctx
->block
;
2821 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2823 ninputs
-= max_sysvals
[ctx
->so
->type
];
2825 if (ctx
->so
->key
.has_gs
) {
2826 if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
2827 ctx
->so
->type
== MESA_SHADER_GEOMETRY
) {
2828 ctx
->gs_header
= create_input(ctx
, 0);
2829 ctx
->primitive_id
= create_input(ctx
, 0);
2833 /* for fragment shader, the vcoord input register is used as the
2834 * base for bary.f varying fetch instrs:
2836 * TODO defer creating ctx->ij_pixel and corresponding sysvals
2837 * until emit_intrinsic when we know they are actually needed.
2838 * For now, we defer creating ctx->ij_centroid, etc, since we
2839 * only need ij_pixel for "old style" varying inputs (ie.
2842 struct ir3_instruction
*vcoord
= NULL
;
2843 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2844 struct ir3_instruction
*xy
[2];
2846 vcoord
= create_input_compmask(ctx
, 0, 0x3);
2847 ir3_split_dest(ctx
->block
, xy
, vcoord
, 0, 2);
2849 ctx
->ij_pixel
= ir3_create_collect(ctx
, xy
, 2);
2853 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
2854 setup_input(ctx
, var
);
2857 /* Defer add_sysval_input() stuff until after setup_inputs(),
2858 * because sysvals need to be appended after varyings:
2861 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_BARYCENTRIC_PIXEL
,
2865 if (ctx
->primitive_id
)
2866 add_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, ctx
->primitive_id
);
2868 add_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, ctx
->gs_header
);
2870 /* Setup outputs: */
2871 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
2872 setup_output(ctx
, var
);
2875 /* Set up the gs header as an output for the vertex shader so it won't
2876 * clobber it for the tess ctrl shader. */
2877 if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
2878 struct ir3_shader_variant
*so
= ctx
->so
;
2879 if (ctx
->primitive_id
) {
2880 unsigned n
= so
->outputs_count
++;
2881 so
->outputs
[n
].slot
= VARYING_SLOT_PRIMITIVE_ID
;
2882 so
->outputs
[n
].regid
= regid(n
, 0);
2883 ctx
->ir
->outputs
[n
* 4] = ctx
->primitive_id
;
2885 compile_assert(ctx
, n
* 4 < ctx
->ir
->noutputs
);
2888 if (ctx
->gs_header
) {
2889 unsigned n
= so
->outputs_count
++;
2890 so
->outputs
[n
].slot
= VARYING_SLOT_GS_HEADER_IR3
;
2891 so
->outputs
[n
].regid
= regid(n
, 0);
2892 ctx
->ir
->outputs
[n
* 4] = ctx
->gs_header
;
2894 compile_assert(ctx
, n
* 4 < ctx
->ir
->noutputs
);
2899 /* Find # of samplers: */
2900 nir_foreach_variable(var
, &ctx
->s
->uniforms
) {
2901 ctx
->so
->num_samp
+= glsl_type_get_sampler_count(var
->type
);
2902 /* just assume that we'll be reading from images.. if it
2903 * is write-only we don't have to count it, but not sure
2904 * if there is a good way to know?
2906 ctx
->so
->num_samp
+= glsl_type_get_image_count(var
->type
);
2909 /* NOTE: need to do something more clever when we support >1 fxn */
2910 nir_foreach_register(reg
, &fxn
->registers
) {
2911 ir3_declare_array(ctx
, reg
);
2913 /* And emit the body: */
2915 emit_function(ctx
, fxn
);
2918 /* from NIR perspective, we actually have varying inputs. But the varying
2919 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2920 * only actual inputs are the sysvals.
2923 fixup_frag_inputs(struct ir3_context
*ctx
)
2925 struct ir3_shader_variant
*so
= ctx
->so
;
2926 struct ir3
*ir
= ctx
->ir
;
2929 /* sysvals should appear at the end of the inputs, drop everything else: */
2930 while ((i
< so
->inputs_count
) && !so
->inputs
[i
].sysval
)
2933 /* at IR level, inputs are always blocks of 4 scalars: */
2936 ir
->inputs
= &ir
->inputs
[i
];
2940 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2941 * need to assign the tex state indexes for these after we know the
2945 fixup_astc_srgb(struct ir3_context
*ctx
)
2947 struct ir3_shader_variant
*so
= ctx
->so
;
2948 /* indexed by original tex idx, value is newly assigned alpha sampler
2949 * state tex idx. Zero is invalid since there is at least one sampler
2952 unsigned alt_tex_state
[16] = {0};
2953 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
2956 so
->astc_srgb
.base
= tex_idx
;
2958 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
2959 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
2961 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
2963 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
2964 /* assign new alternate/alpha tex state slot: */
2965 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
2966 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
2967 so
->astc_srgb
.count
++;
2970 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
2975 fixup_binning_pass(struct ir3_context
*ctx
)
2977 struct ir3_shader_variant
*so
= ctx
->so
;
2978 struct ir3
*ir
= ctx
->ir
;
2981 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2982 unsigned slot
= so
->outputs
[i
].slot
;
2984 /* throw away everything but first position/psize */
2985 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2987 so
->outputs
[j
] = so
->outputs
[i
];
2988 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2989 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2990 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2991 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2996 so
->outputs_count
= j
;
2997 ir
->noutputs
= j
* 4;
3001 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3002 struct ir3_shader_variant
*so
)
3004 struct ir3_context
*ctx
;
3006 struct ir3_instruction
**inputs
;
3008 int ret
= 0, max_bary
;
3012 ctx
= ir3_context_init(compiler
, so
);
3014 DBG("INIT failed!");
3019 emit_instructions(ctx
);
3022 DBG("EMIT failed!");
3027 ir
= so
->ir
= ctx
->ir
;
3029 /* keep track of the inputs from TGSI perspective.. */
3030 inputs
= ir
->inputs
;
3032 /* but fixup actual inputs for frag shader: */
3033 if (so
->type
== MESA_SHADER_FRAGMENT
)
3034 fixup_frag_inputs(ctx
);
3036 /* at this point, for binning pass, throw away unneeded outputs: */
3037 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
< 600))
3038 fixup_binning_pass(ctx
);
3040 /* if we want half-precision outputs, mark the output registers
3043 if (so
->key
.half_precision
) {
3044 for (i
= 0; i
< ir
->noutputs
; i
++) {
3045 struct ir3_instruction
*out
= ir
->outputs
[i
];
3050 /* if frag shader writes z, that needs to be full precision: */
3051 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
3054 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3055 /* output could be a fanout (ie. texture fetch output)
3056 * in which case we need to propagate the half-reg flag
3057 * up to the definer so that RA sees it:
3059 if (out
->opc
== OPC_META_FO
) {
3060 out
= out
->regs
[1]->instr
;
3061 out
->regs
[0]->flags
|= IR3_REG_HALF
;
3064 if (out
->opc
== OPC_MOV
) {
3065 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
3070 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3071 printf("BEFORE CP:\n");
3077 /* at this point, for binning pass, throw away unneeded outputs:
3078 * Note that for a6xx and later, we do this after ir3_cp to ensure
3079 * that the uniform/constant layout for BS and VS matches, so that
3080 * we can re-use same VS_CONST state group.
3082 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
>= 600))
3083 fixup_binning_pass(ctx
);
3085 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3086 * need to make sure not to remove any inputs that are used by
3087 * the nonbinning VS.
3089 if (ctx
->compiler
->gpu_id
>= 600 && so
->binning_pass
) {
3090 debug_assert(so
->type
== MESA_SHADER_VERTEX
);
3091 for (int i
= 0; i
< ir
->ninputs
; i
++) {
3092 struct ir3_instruction
*in
= ir
->inputs
[i
];
3100 debug_assert(n
< so
->nonbinning
->inputs_count
);
3102 if (so
->nonbinning
->inputs
[n
].sysval
)
3105 /* be sure to keep inputs, even if only used in VS */
3106 if (so
->nonbinning
->inputs
[n
].compmask
& (1 << c
))
3107 array_insert(in
->block
, in
->block
->keeps
, in
);
3111 /* Insert mov if there's same instruction for each output.
3112 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
3114 for (int i
= ir
->noutputs
- 1; i
>= 0; i
--) {
3115 if (!ir
->outputs
[i
])
3117 for (unsigned j
= 0; j
< i
; j
++) {
3118 if (ir
->outputs
[i
] == ir
->outputs
[j
]) {
3120 ir3_MOV(ir
->outputs
[i
]->block
, ir
->outputs
[i
], TYPE_F32
);
3125 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3126 printf("BEFORE GROUPING:\n");
3130 ir3_sched_add_deps(ir
);
3132 /* Group left/right neighbors, inserting mov's where needed to
3137 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3138 printf("AFTER GROUPING:\n");
3144 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3145 printf("AFTER DEPTH:\n");
3149 /* do Sethi–Ullman numbering before scheduling: */
3152 ret
= ir3_sched(ir
);
3154 DBG("SCHED failed!");
3158 if (compiler
->gpu_id
>= 600) {
3159 ir3_a6xx_fixup_atomic_dests(ir
, so
);
3162 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3163 printf("AFTER SCHED:\n");
3167 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3168 * with draw pass VS, so binning and draw pass can both use the
3171 * Note that VS inputs are expected to be full precision.
3173 bool pre_assign_inputs
= (ir
->compiler
->gpu_id
>= 600) &&
3174 (ir
->type
== MESA_SHADER_VERTEX
) &&
3177 if (pre_assign_inputs
) {
3178 for (unsigned i
= 0; i
< ir
->ninputs
; i
++) {
3179 struct ir3_instruction
*instr
= ir
->inputs
[i
];
3186 unsigned regid
= so
->nonbinning
->inputs
[n
].regid
+ c
;
3188 instr
->regs
[0]->num
= regid
;
3191 ret
= ir3_ra(so
, ir
->inputs
, ir
->ninputs
);
3192 } else if (ctx
->gs_header
) {
3193 /* We need to have these values in the same registers between VS and GS
3194 * since the VS chains to GS and doesn't get the sysvals redelivered.
3197 ctx
->gs_header
->regs
[0]->num
= 0;
3198 ctx
->primitive_id
->regs
[0]->num
= 1;
3199 struct ir3_instruction
*precolor
[] = { ctx
->gs_header
, ctx
->primitive_id
};
3200 ret
= ir3_ra(so
, precolor
, ARRAY_SIZE(precolor
));
3202 ret
= ir3_ra(so
, NULL
, 0);
3210 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3211 printf("AFTER RA:\n");
3215 if (so
->type
== MESA_SHADER_FRAGMENT
)
3218 /* fixup input/outputs: */
3219 for (i
= 0; i
< so
->outputs_count
; i
++) {
3220 /* sometimes we get outputs that don't write the .x coord, like:
3222 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
3224 * Presumably the result of varying packing and then eliminating
3225 * some unneeded varyings? Just skip head to the first valid
3226 * component of the output.
3228 for (unsigned j
= 0; j
< 4; j
++) {
3229 struct ir3_instruction
*instr
= ir
->outputs
[(i
*4) + j
];
3231 so
->outputs
[i
].regid
= instr
->regs
[0]->num
;
3232 so
->outputs
[i
].half
= !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
3238 /* Note that some or all channels of an input may be unused: */
3239 for (i
= 0; i
< so
->inputs_count
; i
++) {
3240 unsigned j
, reg
= regid(63,0);
3242 for (j
= 0; j
< 4; j
++) {
3243 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3248 if (in
->flags
& IR3_INSTR_UNUSED
)
3251 reg
= in
->regs
[0]->num
- j
;
3253 compile_assert(ctx
, in
->regs
[0]->flags
& IR3_REG_HALF
);
3255 half
= !!(in
->regs
[0]->flags
& IR3_REG_HALF
);
3258 so
->inputs
[i
].regid
= reg
;
3259 so
->inputs
[i
].half
= half
;
3263 fixup_astc_srgb(ctx
);
3265 /* We need to do legalize after (for frag shader's) the "bary.f"
3266 * offsets (inloc) have been assigned.
3268 ir3_legalize(ir
, &so
->has_ssbo
, &so
->need_pixlod
, &max_bary
);
3270 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3271 printf("AFTER LEGALIZE:\n");
3275 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3276 * know what we might have to wait on when coming in from VS chsh.
3278 if (so
->type
== MESA_SHADER_TESS_CTRL
||
3279 so
->type
== MESA_SHADER_GEOMETRY
) {
3280 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
) {
3281 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
3282 instr
->flags
|= IR3_INSTR_SS
| IR3_INSTR_SY
;
3288 so
->branchstack
= ctx
->max_stack
;
3290 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3291 if (so
->type
== MESA_SHADER_FRAGMENT
)
3292 so
->total_in
= max_bary
+ 1;
3294 so
->max_sun
= ir
->max_sun
;
3299 ir3_destroy(so
->ir
);
3302 ir3_context_free(ctx
);