2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
38 #include "instr-a3xx.h"
40 #include "ir3_context.h"
43 static struct ir3_instruction
*
44 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
45 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
47 struct ir3_block
*block
= ctx
->block
;
48 struct ir3_instruction
*mov
;
49 struct ir3_register
*src
;
51 mov
= ir3_instr_create(block
, OPC_MOV
);
52 mov
->cat1
.src_type
= TYPE_U32
;
53 mov
->cat1
.dst_type
= TYPE_U32
;
54 ir3_reg_create(mov
, 0, 0);
55 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
58 src
->array
.offset
= n
;
60 ir3_instr_set_address(mov
, address
);
65 static struct ir3_instruction
*
66 create_input_compmask(struct ir3_context
*ctx
, unsigned n
, unsigned compmask
)
68 struct ir3_instruction
*in
;
70 in
= ir3_instr_create(ctx
->in_block
, OPC_META_INPUT
);
71 in
->inout
.block
= ctx
->in_block
;
72 ir3_reg_create(in
, n
, 0);
74 in
->regs
[0]->wrmask
= compmask
;
79 static struct ir3_instruction
*
80 create_input(struct ir3_context
*ctx
, unsigned n
)
82 return create_input_compmask(ctx
, n
, 0x1);
85 static struct ir3_instruction
*
86 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
, unsigned n
)
88 struct ir3_block
*block
= ctx
->block
;
89 struct ir3_instruction
*instr
;
90 /* packed inloc is fixed up later: */
91 struct ir3_instruction
*inloc
= create_immed(block
, n
);
94 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
95 instr
->cat6
.type
= TYPE_U32
;
96 instr
->cat6
.iim_val
= 1;
98 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->ij_pixel
, 0);
99 instr
->regs
[2]->wrmask
= 0x3;
105 static struct ir3_instruction
*
106 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
111 unsigned n
= const_state
->offsets
.driver_param
;
112 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
113 return create_uniform(ctx
->block
, r
);
117 * Adreno uses uint rather than having dedicated bool type,
118 * which (potentially) requires some conversion, in particular
119 * when using output of an bool instr to int input, or visa
123 * -------+---------+-------+-
127 * To convert from an adreno bool (uint) to nir, use:
129 * absneg.s dst, (neg)src
131 * To convert back in the other direction:
133 * absneg.s dst, (abs)arc
135 * The CP step can clean up the absneg.s that cancel each other
136 * out, and with a slight bit of extra cleverness (to recognize
137 * the instructions which produce either a 0 or 1) can eliminate
138 * the absneg.s's completely when an instruction that wants
139 * 0/1 consumes the result. For example, when a nir 'bcsel'
140 * consumes the result of 'feq'. So we should be able to get by
141 * without a boolean resolve step, and without incuring any
142 * extra penalty in instruction count.
145 /* NIR bool -> native (adreno): */
146 static struct ir3_instruction
*
147 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
149 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
152 /* native (adreno) -> NIR bool: */
153 static struct ir3_instruction
*
154 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
156 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
160 * alu/sfu instructions:
163 static struct ir3_instruction
*
164 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
165 unsigned src_bitsize
, nir_op op
)
167 type_t src_type
, dst_type
;
171 case nir_op_f2f16_rtne
:
172 case nir_op_f2f16_rtz
:
180 switch (src_bitsize
) {
188 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
197 switch (src_bitsize
) {
208 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
217 switch (src_bitsize
) {
228 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
233 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
243 case nir_op_f2f16_rtne
:
244 case nir_op_f2f16_rtz
:
246 /* TODO how to handle rounding mode? */
283 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
286 return ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
290 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
292 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
293 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
294 unsigned bs
[info
->num_inputs
]; /* bit size */
295 struct ir3_block
*b
= ctx
->block
;
296 unsigned dst_sz
, wrmask
;
298 if (alu
->dest
.dest
.is_ssa
) {
299 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
300 wrmask
= (1 << dst_sz
) - 1;
302 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
303 wrmask
= alu
->dest
.write_mask
;
306 dst
= ir3_get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
308 /* Vectors are special in that they have non-scalarized writemasks,
309 * and just take the first swizzle channel for each argument in
310 * order into each writemask channel.
312 if ((alu
->op
== nir_op_vec2
) ||
313 (alu
->op
== nir_op_vec3
) ||
314 (alu
->op
== nir_op_vec4
)) {
316 for (int i
= 0; i
< info
->num_inputs
; i
++) {
317 nir_alu_src
*asrc
= &alu
->src
[i
];
319 compile_assert(ctx
, !asrc
->abs
);
320 compile_assert(ctx
, !asrc
->negate
);
322 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
324 src
[i
] = create_immed(ctx
->block
, 0);
325 dst
[i
] = ir3_MOV(b
, src
[i
], TYPE_U32
);
328 ir3_put_dst(ctx
, &alu
->dest
.dest
);
332 /* We also get mov's with more than one component for mov's so
333 * handle those specially:
335 if (alu
->op
== nir_op_mov
) {
336 type_t type
= TYPE_U32
;
337 nir_alu_src
*asrc
= &alu
->src
[0];
338 struct ir3_instruction
*const *src0
= ir3_get_src(ctx
, &asrc
->src
);
340 for (unsigned i
= 0; i
< dst_sz
; i
++) {
341 if (wrmask
& (1 << i
)) {
342 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], type
);
348 ir3_put_dst(ctx
, &alu
->dest
.dest
);
352 /* General case: We can just grab the one used channel per src. */
353 for (int i
= 0; i
< info
->num_inputs
; i
++) {
354 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
355 nir_alu_src
*asrc
= &alu
->src
[i
];
357 compile_assert(ctx
, !asrc
->abs
);
358 compile_assert(ctx
, !asrc
->negate
);
360 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
361 bs
[i
] = nir_src_bit_size(asrc
->src
);
363 compile_assert(ctx
, src
[i
]);
368 case nir_op_f2f16_rtne
:
369 case nir_op_f2f16_rtz
:
387 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
390 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
391 dst
[0]->cat2
.condition
= IR3_COND_NE
;
392 dst
[0] = ir3_n2b(b
, dst
[0]);
396 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
401 dst
[0] = ir3_b2n(b
, src
[0]);
404 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
405 dst
[0]->cat2
.condition
= IR3_COND_NE
;
406 dst
[0] = ir3_n2b(b
, dst
[0]);
410 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
413 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
416 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
419 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
422 /* if there is just a single use of the src, and it supports
423 * (sat) bit, we can just fold the (sat) flag back to the
424 * src instruction and create a mov. This is easier for cp
427 * TODO probably opc_cat==4 is ok too
429 if (alu
->src
[0].src
.is_ssa
&&
430 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
431 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
432 src
[0]->flags
|= IR3_INSTR_SAT
;
433 dst
[0] = ir3_MOV(b
, src
[0], TYPE_U32
);
435 /* otherwise generate a max.f that saturates.. blob does
436 * similar (generating a cat2 mov using max.f)
438 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
439 dst
[0]->flags
|= IR3_INSTR_SAT
;
443 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
446 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
449 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
452 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
455 dst
[0] = ir3_DSX(b
, src
[0], 0);
456 dst
[0]->cat5
.type
= TYPE_F32
;
459 dst
[0] = ir3_DSY(b
, src
[0], 0);
460 dst
[0]->cat5
.type
= TYPE_F32
;
464 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
465 dst
[0]->cat2
.condition
= IR3_COND_LT
;
466 dst
[0] = ir3_n2b(b
, dst
[0]);
469 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
470 dst
[0]->cat2
.condition
= IR3_COND_GE
;
471 dst
[0] = ir3_n2b(b
, dst
[0]);
474 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
475 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
476 dst
[0] = ir3_n2b(b
, dst
[0]);
479 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
480 dst
[0]->cat2
.condition
= IR3_COND_NE
;
481 dst
[0] = ir3_n2b(b
, dst
[0]);
484 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
487 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
490 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
492 case nir_op_fround_even
:
493 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
496 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
500 dst
[0] = ir3_SIN(b
, src
[0], 0);
503 dst
[0] = ir3_COS(b
, src
[0], 0);
506 dst
[0] = ir3_RSQ(b
, src
[0], 0);
509 dst
[0] = ir3_RCP(b
, src
[0], 0);
512 dst
[0] = ir3_LOG2(b
, src
[0], 0);
515 dst
[0] = ir3_EXP2(b
, src
[0], 0);
518 dst
[0] = ir3_SQRT(b
, src
[0], 0);
522 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
525 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
528 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
531 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
534 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
537 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
540 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
544 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
545 * mull.u tmp0, a, b ; mul low, i.e. al * bl
546 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
547 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
549 dst
[0] = ir3_MADSH_M16(b
, src
[1], 0, src
[0], 0,
550 ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0,
551 ir3_MULL_U(b
, src
[0], 0, src
[1], 0), 0), 0);
554 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
557 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
560 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
563 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
566 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
569 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
572 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
575 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
578 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
579 dst
[0]->cat2
.condition
= IR3_COND_LT
;
580 dst
[0] = ir3_n2b(b
, dst
[0]);
583 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
584 dst
[0]->cat2
.condition
= IR3_COND_GE
;
585 dst
[0] = ir3_n2b(b
, dst
[0]);
588 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
589 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
590 dst
[0] = ir3_n2b(b
, dst
[0]);
593 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
594 dst
[0]->cat2
.condition
= IR3_COND_NE
;
595 dst
[0] = ir3_n2b(b
, dst
[0]);
598 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
599 dst
[0]->cat2
.condition
= IR3_COND_LT
;
600 dst
[0] = ir3_n2b(b
, dst
[0]);
603 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
604 dst
[0]->cat2
.condition
= IR3_COND_GE
;
605 dst
[0] = ir3_n2b(b
, dst
[0]);
608 case nir_op_b32csel
: {
609 struct ir3_instruction
*cond
= ir3_b2n(b
, src
[0]);
610 compile_assert(ctx
, bs
[1] == bs
[2]);
611 /* the boolean condition is 32b even if src[1] and src[2] are
612 * half-precision, but sel.b16 wants all three src's to be the
616 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
617 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
620 case nir_op_bit_count
: {
621 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
622 // double check on earlier gen's. Once half-precision support is
623 // in place, this should probably move to a NIR lowering pass:
624 struct ir3_instruction
*hi
, *lo
;
626 hi
= ir3_COV(b
, ir3_SHR_B(b
, src
[0], 0, create_immed(b
, 16), 0),
628 lo
= ir3_COV(b
, src
[0], TYPE_U32
, TYPE_U16
);
630 hi
= ir3_CBITS_B(b
, hi
, 0);
631 lo
= ir3_CBITS_B(b
, lo
, 0);
633 // TODO maybe the builders should default to making dst half-precision
634 // if the src's were half precision, to make this less awkward.. otoh
635 // we should probably just do this lowering in NIR.
636 hi
->regs
[0]->flags
|= IR3_REG_HALF
;
637 lo
->regs
[0]->flags
|= IR3_REG_HALF
;
639 dst
[0] = ir3_ADD_S(b
, hi
, 0, lo
, 0);
640 dst
[0]->regs
[0]->flags
|= IR3_REG_HALF
;
641 dst
[0] = ir3_COV(b
, dst
[0], TYPE_U16
, TYPE_U32
);
644 case nir_op_ifind_msb
: {
645 struct ir3_instruction
*cmp
;
646 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
647 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
648 cmp
->cat2
.condition
= IR3_COND_GE
;
649 dst
[0] = ir3_SEL_B32(b
,
650 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
654 case nir_op_ufind_msb
:
655 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
656 dst
[0] = ir3_SEL_B32(b
,
657 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
658 src
[0], 0, dst
[0], 0);
660 case nir_op_find_lsb
:
661 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
662 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
664 case nir_op_bitfield_reverse
:
665 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
669 ir3_context_error(ctx
, "Unhandled ALU op: %s\n",
670 nir_op_infos
[alu
->op
].name
);
674 ir3_put_dst(ctx
, &alu
->dest
.dest
);
677 /* handles direct/indirect UBO reads: */
679 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
680 struct ir3_instruction
**dst
)
682 struct ir3_block
*b
= ctx
->block
;
683 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
684 /* UBO addresses are the first driver params, but subtract 2 here to
685 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
686 * is the uniforms: */
687 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
688 unsigned ubo
= regid(const_state
->offsets
.ubo
, 0) - 2;
689 const unsigned ptrsz
= ir3_pointer_size(ctx
->compiler
);
693 /* First src is ubo index, which could either be an immed or not: */
694 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0];
695 if (is_same_type_mov(src0
) &&
696 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
697 base_lo
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
698 base_hi
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
700 base_lo
= create_uniform_indirect(b
, ubo
, ir3_get_addr(ctx
, src0
, ptrsz
));
701 base_hi
= create_uniform_indirect(b
, ubo
+ 1, ir3_get_addr(ctx
, src0
, ptrsz
));
704 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
707 if (nir_src_is_const(intr
->src
[1])) {
708 off
+= nir_src_as_uint(intr
->src
[1]);
710 /* For load_ubo_indirect, second src is indirect offset: */
711 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0];
713 /* and add offset to addr: */
714 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
717 /* if offset is to large to encode in the ldg, split it out: */
718 if ((off
+ (intr
->num_components
* 4)) > 1024) {
719 /* split out the minimal amount to improve the odds that
720 * cp can fit the immediate in the add.s instruction:
722 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
723 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
728 struct ir3_instruction
*carry
;
730 /* handle 32b rollover, ie:
731 * if (addr < base_lo)
734 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
735 carry
->cat2
.condition
= IR3_COND_LT
;
736 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
738 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
741 for (int i
= 0; i
< intr
->num_components
; i
++) {
742 struct ir3_instruction
*load
=
743 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0);
744 load
->cat6
.type
= TYPE_U32
;
745 load
->cat6
.src_offset
= off
+ i
* 4; /* byte offset */
750 /* src[] = { block_index } */
752 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
753 struct ir3_instruction
**dst
)
755 /* SSBO size stored as a const starting at ssbo_sizes: */
756 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
757 unsigned blk_idx
= nir_src_as_uint(intr
->src
[0]);
758 unsigned idx
= regid(const_state
->offsets
.ssbo_sizes
, 0) +
759 const_state
->ssbo_size
.off
[blk_idx
];
761 debug_assert(const_state
->ssbo_size
.mask
& (1 << blk_idx
));
763 dst
[0] = create_uniform(ctx
->block
, idx
);
766 /* src[] = { offset }. const_index[] = { base } */
768 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
769 struct ir3_instruction
**dst
)
771 struct ir3_block
*b
= ctx
->block
;
772 struct ir3_instruction
*ldl
, *offset
;
775 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
776 base
= nir_intrinsic_base(intr
);
778 ldl
= ir3_LDL(b
, offset
, 0, create_immed(b
, intr
->num_components
), 0);
779 ldl
->cat6
.src_offset
= base
;
780 ldl
->cat6
.type
= utype_dst(intr
->dest
);
781 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
783 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
784 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
786 ir3_split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
789 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
791 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
793 struct ir3_block
*b
= ctx
->block
;
794 struct ir3_instruction
*stl
, *offset
;
795 struct ir3_instruction
* const *value
;
796 unsigned base
, wrmask
;
798 value
= ir3_get_src(ctx
, &intr
->src
[0]);
799 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
801 base
= nir_intrinsic_base(intr
);
802 wrmask
= nir_intrinsic_write_mask(intr
);
804 /* Combine groups of consecutive enabled channels in one write
805 * message. We use ffs to find the first enabled channel and then ffs on
806 * the bit-inverse, down-shifted writemask to determine the length of
807 * the block of enabled bits.
809 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
812 unsigned first_component
= ffs(wrmask
) - 1;
813 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
815 stl
= ir3_STL(b
, offset
, 0,
816 ir3_create_collect(ctx
, &value
[first_component
], length
), 0,
817 create_immed(b
, length
), 0);
818 stl
->cat6
.dst_offset
= first_component
+ base
;
819 stl
->cat6
.type
= utype_src(intr
->src
[0]);
820 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
821 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
823 array_insert(b
, b
->keeps
, stl
);
825 /* Clear the bits in the writemask that we just wrote, then try
826 * again to see if more channels are left.
828 wrmask
&= (15 << (first_component
+ length
));
833 * CS shared variable atomic intrinsics
835 * All of the shared variable atomic memory operations read a value from
836 * memory, compute a new value using one of the operations below, write the
837 * new value to memory, and return the original value read.
839 * All operations take 2 sources except CompSwap that takes 3. These
842 * 0: The offset into the shared variable storage region that the atomic
843 * operation will operate on.
844 * 1: The data parameter to the atomic function (i.e. the value to add
845 * in shared_atomic_add, etc).
846 * 2: For CompSwap only: the second data parameter.
848 static struct ir3_instruction
*
849 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
851 struct ir3_block
*b
= ctx
->block
;
852 struct ir3_instruction
*atomic
, *src0
, *src1
;
853 type_t type
= TYPE_U32
;
855 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0]; /* offset */
856 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0]; /* value */
858 switch (intr
->intrinsic
) {
859 case nir_intrinsic_shared_atomic_add
:
860 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
862 case nir_intrinsic_shared_atomic_imin
:
863 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
866 case nir_intrinsic_shared_atomic_umin
:
867 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
869 case nir_intrinsic_shared_atomic_imax
:
870 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
873 case nir_intrinsic_shared_atomic_umax
:
874 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
876 case nir_intrinsic_shared_atomic_and
:
877 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
879 case nir_intrinsic_shared_atomic_or
:
880 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
882 case nir_intrinsic_shared_atomic_xor
:
883 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
885 case nir_intrinsic_shared_atomic_exchange
:
886 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
888 case nir_intrinsic_shared_atomic_comp_swap
:
889 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
890 src1
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
891 ir3_get_src(ctx
, &intr
->src
[2])[0],
894 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
900 atomic
->cat6
.iim_val
= 1;
902 atomic
->cat6
.type
= type
;
903 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
904 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
906 /* even if nothing consume the result, we can't DCE the instruction: */
907 array_insert(b
, b
->keeps
, atomic
);
912 /* TODO handle actual indirect/dynamic case.. which is going to be weird
913 * to handle with the image_mapping table..
915 static struct ir3_instruction
*
916 get_image_samp_tex_src(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
918 unsigned slot
= ir3_get_image_slot(nir_src_as_deref(intr
->src
[0]));
919 unsigned tex_idx
= ir3_image_to_tex(&ctx
->so
->image_mapping
, slot
);
920 struct ir3_instruction
*texture
, *sampler
;
922 texture
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
923 sampler
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
925 return ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
931 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
933 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
934 struct ir3_instruction
**dst
)
936 struct ir3_block
*b
= ctx
->block
;
937 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
938 struct ir3_instruction
*samp_tex
= get_image_samp_tex_src(ctx
, intr
);
939 struct ir3_instruction
*sam
;
940 struct ir3_instruction
* const *src0
= ir3_get_src(ctx
, &intr
->src
[1]);
941 struct ir3_instruction
*coords
[4];
942 unsigned flags
, ncoords
= ir3_get_image_coords(var
, &flags
);
943 type_t type
= ir3_get_image_type(var
);
945 /* hmm, this seems a bit odd, but it is what blob does and (at least
946 * a5xx) just faults on bogus addresses otherwise:
948 if (flags
& IR3_INSTR_3D
) {
949 flags
&= ~IR3_INSTR_3D
;
950 flags
|= IR3_INSTR_A
;
953 for (unsigned i
= 0; i
< ncoords
; i
++)
957 coords
[ncoords
++] = create_immed(b
, 0);
959 sam
= ir3_SAM(b
, OPC_ISAM
, type
, 0b1111, flags
,
960 samp_tex
, ir3_create_collect(ctx
, coords
, ncoords
), NULL
);
962 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
963 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
965 ir3_split_dest(b
, dst
, sam
, 0, 4);
969 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
970 struct ir3_instruction
**dst
)
972 struct ir3_block
*b
= ctx
->block
;
973 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
974 struct ir3_instruction
*samp_tex
= get_image_samp_tex_src(ctx
, intr
);
975 struct ir3_instruction
*sam
, *lod
;
976 unsigned flags
, ncoords
= ir3_get_image_coords(var
, &flags
);
978 lod
= create_immed(b
, 0);
979 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, 0b1111, flags
,
980 samp_tex
, lod
, NULL
);
982 /* Array size actually ends up in .w rather than .z. This doesn't
983 * matter for miplevel 0, but for higher mips the value in z is
984 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
985 * returned, which means that we have to add 1 to it for arrays for
988 * Note use a temporary dst and then copy, since the size of the dst
989 * array that is passed in is based on nir's understanding of the
990 * result size, not the hardware's
992 struct ir3_instruction
*tmp
[4];
994 ir3_split_dest(b
, tmp
, sam
, 0, 4);
996 /* get_size instruction returns size in bytes instead of texels
997 * for imageBuffer, so we need to divide it by the pixel size
998 * of the image format.
1000 * TODO: This is at least true on a5xx. Check other gens.
1002 enum glsl_sampler_dim dim
=
1003 glsl_get_sampler_dim(glsl_without_array(var
->type
));
1004 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
1005 /* Since all the possible values the divisor can take are
1006 * power-of-two (4, 8, or 16), the division is implemented
1008 * During shader setup, the log2 of the image format's
1009 * bytes-per-pixel should have been emitted in 2nd slot of
1010 * image_dims. See ir3_shader::emit_image_dims().
1012 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
1013 unsigned cb
= regid(const_state
->offsets
.image_dims
, 0) +
1014 const_state
->image_dims
.off
[var
->data
.driver_location
];
1015 struct ir3_instruction
*aux
= create_uniform(b
, cb
+ 1);
1017 tmp
[0] = ir3_SHR_B(b
, tmp
[0], 0, aux
, 0);
1020 for (unsigned i
= 0; i
< ncoords
; i
++)
1023 if (flags
& IR3_INSTR_A
) {
1024 if (ctx
->compiler
->levels_add_one
) {
1025 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
1027 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
1033 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1035 struct ir3_block
*b
= ctx
->block
;
1036 struct ir3_instruction
*barrier
;
1038 switch (intr
->intrinsic
) {
1039 case nir_intrinsic_barrier
:
1040 barrier
= ir3_BAR(b
);
1041 barrier
->cat7
.g
= true;
1042 barrier
->cat7
.l
= true;
1043 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1044 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1046 case nir_intrinsic_memory_barrier
:
1047 barrier
= ir3_FENCE(b
);
1048 barrier
->cat7
.g
= true;
1049 barrier
->cat7
.r
= true;
1050 barrier
->cat7
.w
= true;
1051 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1052 IR3_BARRIER_BUFFER_W
;
1053 barrier
->barrier_conflict
=
1054 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1055 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1057 case nir_intrinsic_memory_barrier_atomic_counter
:
1058 case nir_intrinsic_memory_barrier_buffer
:
1059 barrier
= ir3_FENCE(b
);
1060 barrier
->cat7
.g
= true;
1061 barrier
->cat7
.r
= true;
1062 barrier
->cat7
.w
= true;
1063 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1064 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1065 IR3_BARRIER_BUFFER_W
;
1067 case nir_intrinsic_memory_barrier_image
:
1068 // TODO double check if this should have .g set
1069 barrier
= ir3_FENCE(b
);
1070 barrier
->cat7
.g
= true;
1071 barrier
->cat7
.r
= true;
1072 barrier
->cat7
.w
= true;
1073 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1074 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1075 IR3_BARRIER_IMAGE_W
;
1077 case nir_intrinsic_memory_barrier_shared
:
1078 barrier
= ir3_FENCE(b
);
1079 barrier
->cat7
.g
= true;
1080 barrier
->cat7
.l
= true;
1081 barrier
->cat7
.r
= true;
1082 barrier
->cat7
.w
= true;
1083 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1084 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1085 IR3_BARRIER_SHARED_W
;
1087 case nir_intrinsic_group_memory_barrier
:
1088 barrier
= ir3_FENCE(b
);
1089 barrier
->cat7
.g
= true;
1090 barrier
->cat7
.l
= true;
1091 barrier
->cat7
.r
= true;
1092 barrier
->cat7
.w
= true;
1093 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1094 IR3_BARRIER_IMAGE_W
|
1095 IR3_BARRIER_BUFFER_W
;
1096 barrier
->barrier_conflict
=
1097 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1098 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1099 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1105 /* make sure barrier doesn't get DCE'd */
1106 array_insert(b
, b
->keeps
, barrier
);
1109 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1110 gl_system_value slot
, unsigned compmask
,
1111 struct ir3_instruction
*instr
)
1113 struct ir3_shader_variant
*so
= ctx
->so
;
1114 unsigned r
= regid(so
->inputs_count
, 0);
1115 unsigned n
= so
->inputs_count
++;
1117 so
->inputs
[n
].sysval
= true;
1118 so
->inputs
[n
].slot
= slot
;
1119 so
->inputs
[n
].compmask
= compmask
;
1120 so
->inputs
[n
].regid
= r
;
1121 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1124 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1125 ctx
->ir
->inputs
[r
] = instr
;
1128 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1129 struct ir3_instruction
*instr
)
1131 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
1134 static struct ir3_instruction
*
1135 get_barycentric_centroid(struct ir3_context
*ctx
)
1137 if (!ctx
->ij_centroid
) {
1138 struct ir3_instruction
*xy
[2];
1139 struct ir3_instruction
*ij
;
1141 ij
= create_input_compmask(ctx
, 0, 0x3);
1142 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1144 ctx
->ij_centroid
= ir3_create_collect(ctx
, xy
, 2);
1146 add_sysval_input_compmask(ctx
,
1147 SYSTEM_VALUE_BARYCENTRIC_CENTROID
,
1151 return ctx
->ij_centroid
;
1154 static struct ir3_instruction
*
1155 get_barycentric_sample(struct ir3_context
*ctx
)
1157 if (!ctx
->ij_sample
) {
1158 struct ir3_instruction
*xy
[2];
1159 struct ir3_instruction
*ij
;
1161 ij
= create_input_compmask(ctx
, 0, 0x3);
1162 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1164 ctx
->ij_sample
= ir3_create_collect(ctx
, xy
, 2);
1166 add_sysval_input_compmask(ctx
,
1167 SYSTEM_VALUE_BARYCENTRIC_SAMPLE
,
1171 return ctx
->ij_sample
;
1174 static struct ir3_instruction
*
1175 get_barycentric_pixel(struct ir3_context
*ctx
)
1177 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1178 * this to create ij_pixel only on demand:
1180 return ctx
->ij_pixel
;
1183 static struct ir3_instruction
*
1184 get_frag_coord(struct ir3_context
*ctx
)
1186 if (!ctx
->frag_coord
) {
1187 struct ir3_block
*b
= ctx
->block
;
1188 struct ir3_instruction
*xyzw
[4];
1189 struct ir3_instruction
*hw_frag_coord
;
1191 hw_frag_coord
= create_input_compmask(ctx
, 0, 0xf);
1192 ir3_split_dest(ctx
->block
, xyzw
, hw_frag_coord
, 0, 4);
1194 /* for frag_coord.xy, we get unsigned values.. we need
1195 * to subtract (integer) 8 and divide by 16 (right-
1196 * shift by 4) then convert to float:
1200 * mov.u32f32 dst, tmp
1203 for (int i
= 0; i
< 2; i
++) {
1204 xyzw
[i
] = ir3_SUB_S(b
, xyzw
[i
], 0,
1205 create_immed(b
, 8), 0);
1206 xyzw
[i
] = ir3_SHR_B(b
, xyzw
[i
], 0,
1207 create_immed(b
, 4), 0);
1208 xyzw
[i
] = ir3_COV(b
, xyzw
[i
], TYPE_U32
, TYPE_F32
);
1211 ctx
->frag_coord
= ir3_create_collect(ctx
, xyzw
, 4);
1213 add_sysval_input_compmask(ctx
,
1214 SYSTEM_VALUE_FRAG_COORD
,
1215 0xf, hw_frag_coord
);
1217 ctx
->so
->frag_coord
= true;
1220 return ctx
->frag_coord
;
1224 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1226 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1227 struct ir3_instruction
**dst
;
1228 struct ir3_instruction
* const *src
;
1229 struct ir3_block
*b
= ctx
->block
;
1232 if (info
->has_dest
) {
1233 unsigned n
= nir_intrinsic_dest_components(intr
);
1234 dst
= ir3_get_dst(ctx
, &intr
->dest
, n
);
1239 switch (intr
->intrinsic
) {
1240 case nir_intrinsic_load_uniform
:
1241 idx
= nir_intrinsic_base(intr
);
1242 if (nir_src_is_const(intr
->src
[0])) {
1243 idx
+= nir_src_as_uint(intr
->src
[0]);
1244 for (int i
= 0; i
< intr
->num_components
; i
++) {
1245 dst
[i
] = create_uniform(b
, idx
+ i
);
1248 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1249 for (int i
= 0; i
< intr
->num_components
; i
++) {
1250 dst
[i
] = create_uniform_indirect(b
, idx
+ i
,
1251 ir3_get_addr(ctx
, src
[0], 1));
1253 /* NOTE: if relative addressing is used, we set
1254 * constlen in the compiler (to worst-case value)
1255 * since we don't know in the assembler what the max
1256 * addr reg value can be:
1258 ctx
->so
->constlen
= ctx
->s
->num_uniforms
;
1261 case nir_intrinsic_load_ubo
:
1262 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1264 case nir_intrinsic_load_frag_coord
:
1265 ir3_split_dest(b
, dst
, get_frag_coord(ctx
), 0, 4);
1267 case nir_intrinsic_load_sample_pos_from_id
: {
1268 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1269 * but that doesn't seem necessary.
1271 struct ir3_instruction
*offset
=
1272 ir3_RGETPOS(b
, ir3_get_src(ctx
, &intr
->src
[0])[0], 0);
1273 offset
->regs
[0]->wrmask
= 0x3;
1274 offset
->cat5
.type
= TYPE_F32
;
1276 ir3_split_dest(b
, dst
, offset
, 0, 2);
1280 case nir_intrinsic_load_size_ir3
:
1281 if (!ctx
->ij_size
) {
1282 ctx
->ij_size
= create_input(ctx
, 0);
1284 add_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_SIZE
,
1287 dst
[0] = ctx
->ij_size
;
1289 case nir_intrinsic_load_barycentric_centroid
:
1290 ir3_split_dest(b
, dst
, get_barycentric_centroid(ctx
), 0, 2);
1292 case nir_intrinsic_load_barycentric_sample
:
1293 if (ctx
->so
->key
.msaa
) {
1294 ir3_split_dest(b
, dst
, get_barycentric_sample(ctx
), 0, 2);
1296 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1299 case nir_intrinsic_load_barycentric_pixel
:
1300 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1302 case nir_intrinsic_load_interpolated_input
:
1303 idx
= nir_intrinsic_base(intr
);
1304 comp
= nir_intrinsic_component(intr
);
1305 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1306 if (nir_src_is_const(intr
->src
[1])) {
1307 struct ir3_instruction
*coord
= ir3_create_collect(ctx
, src
, 2);
1308 idx
+= nir_src_as_uint(intr
->src
[1]);
1309 for (int i
= 0; i
< intr
->num_components
; i
++) {
1310 unsigned inloc
= idx
* 4 + i
+ comp
;
1311 if (ctx
->so
->inputs
[idx
].bary
&&
1312 !ctx
->so
->inputs
[idx
].use_ldlv
) {
1313 dst
[i
] = ir3_BARY_F(b
, create_immed(b
, inloc
), 0, coord
, 0);
1315 /* for non-varyings use the pre-setup input, since
1316 * that is easier than mapping things back to a
1317 * nir_variable to figure out what it is.
1319 dst
[i
] = ctx
->ir
->inputs
[inloc
];
1323 ir3_context_error(ctx
, "unhandled");
1326 case nir_intrinsic_load_input
:
1327 idx
= nir_intrinsic_base(intr
);
1328 comp
= nir_intrinsic_component(intr
);
1329 if (nir_src_is_const(intr
->src
[0])) {
1330 idx
+= nir_src_as_uint(intr
->src
[0]);
1331 for (int i
= 0; i
< intr
->num_components
; i
++) {
1332 unsigned n
= idx
* 4 + i
+ comp
;
1333 dst
[i
] = ctx
->ir
->inputs
[n
];
1334 compile_assert(ctx
, ctx
->ir
->inputs
[n
]);
1337 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1338 struct ir3_instruction
*collect
=
1339 ir3_create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1340 struct ir3_instruction
*addr
= ir3_get_addr(ctx
, src
[0], 4);
1341 for (int i
= 0; i
< intr
->num_components
; i
++) {
1342 unsigned n
= idx
* 4 + i
+ comp
;
1343 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1348 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1349 * pass and replaced by an ir3-specifc version that adds the
1350 * dword-offset in the last source.
1352 case nir_intrinsic_load_ssbo_ir3
:
1353 ctx
->funcs
->emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1355 case nir_intrinsic_store_ssbo_ir3
:
1356 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1357 !ctx
->s
->info
.fs
.early_fragment_tests
)
1358 ctx
->so
->no_earlyz
= true;
1359 ctx
->funcs
->emit_intrinsic_store_ssbo(ctx
, intr
);
1361 case nir_intrinsic_get_buffer_size
:
1362 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
1364 case nir_intrinsic_ssbo_atomic_add_ir3
:
1365 case nir_intrinsic_ssbo_atomic_imin_ir3
:
1366 case nir_intrinsic_ssbo_atomic_umin_ir3
:
1367 case nir_intrinsic_ssbo_atomic_imax_ir3
:
1368 case nir_intrinsic_ssbo_atomic_umax_ir3
:
1369 case nir_intrinsic_ssbo_atomic_and_ir3
:
1370 case nir_intrinsic_ssbo_atomic_or_ir3
:
1371 case nir_intrinsic_ssbo_atomic_xor_ir3
:
1372 case nir_intrinsic_ssbo_atomic_exchange_ir3
:
1373 case nir_intrinsic_ssbo_atomic_comp_swap_ir3
:
1374 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1375 !ctx
->s
->info
.fs
.early_fragment_tests
)
1376 ctx
->so
->no_earlyz
= true;
1377 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_ssbo(ctx
, intr
);
1379 case nir_intrinsic_load_shared
:
1380 emit_intrinsic_load_shared(ctx
, intr
, dst
);
1382 case nir_intrinsic_store_shared
:
1383 emit_intrinsic_store_shared(ctx
, intr
);
1385 case nir_intrinsic_shared_atomic_add
:
1386 case nir_intrinsic_shared_atomic_imin
:
1387 case nir_intrinsic_shared_atomic_umin
:
1388 case nir_intrinsic_shared_atomic_imax
:
1389 case nir_intrinsic_shared_atomic_umax
:
1390 case nir_intrinsic_shared_atomic_and
:
1391 case nir_intrinsic_shared_atomic_or
:
1392 case nir_intrinsic_shared_atomic_xor
:
1393 case nir_intrinsic_shared_atomic_exchange
:
1394 case nir_intrinsic_shared_atomic_comp_swap
:
1395 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
1397 case nir_intrinsic_image_deref_load
:
1398 emit_intrinsic_load_image(ctx
, intr
, dst
);
1400 case nir_intrinsic_image_deref_store
:
1401 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1402 !ctx
->s
->info
.fs
.early_fragment_tests
)
1403 ctx
->so
->no_earlyz
= true;
1404 ctx
->funcs
->emit_intrinsic_store_image(ctx
, intr
);
1406 case nir_intrinsic_image_deref_size
:
1407 emit_intrinsic_image_size(ctx
, intr
, dst
);
1409 case nir_intrinsic_image_deref_atomic_add
:
1410 case nir_intrinsic_image_deref_atomic_min
:
1411 case nir_intrinsic_image_deref_atomic_max
:
1412 case nir_intrinsic_image_deref_atomic_and
:
1413 case nir_intrinsic_image_deref_atomic_or
:
1414 case nir_intrinsic_image_deref_atomic_xor
:
1415 case nir_intrinsic_image_deref_atomic_exchange
:
1416 case nir_intrinsic_image_deref_atomic_comp_swap
:
1417 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1418 !ctx
->s
->info
.fs
.early_fragment_tests
)
1419 ctx
->so
->no_earlyz
= true;
1420 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_image(ctx
, intr
);
1422 case nir_intrinsic_barrier
:
1423 case nir_intrinsic_memory_barrier
:
1424 case nir_intrinsic_group_memory_barrier
:
1425 case nir_intrinsic_memory_barrier_atomic_counter
:
1426 case nir_intrinsic_memory_barrier_buffer
:
1427 case nir_intrinsic_memory_barrier_image
:
1428 case nir_intrinsic_memory_barrier_shared
:
1429 emit_intrinsic_barrier(ctx
, intr
);
1430 /* note that blk ptr no longer valid, make that obvious: */
1433 case nir_intrinsic_store_output
:
1434 idx
= nir_intrinsic_base(intr
);
1435 comp
= nir_intrinsic_component(intr
);
1436 compile_assert(ctx
, nir_src_is_const(intr
->src
[1]));
1437 idx
+= nir_src_as_uint(intr
->src
[1]);
1439 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1440 for (int i
= 0; i
< intr
->num_components
; i
++) {
1441 unsigned n
= idx
* 4 + i
+ comp
;
1442 ctx
->ir
->outputs
[n
] = src
[i
];
1445 case nir_intrinsic_load_base_vertex
:
1446 case nir_intrinsic_load_first_vertex
:
1447 if (!ctx
->basevertex
) {
1448 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1449 add_sysval_input(ctx
, SYSTEM_VALUE_FIRST_VERTEX
, ctx
->basevertex
);
1451 dst
[0] = ctx
->basevertex
;
1453 case nir_intrinsic_load_vertex_id_zero_base
:
1454 case nir_intrinsic_load_vertex_id
:
1455 if (!ctx
->vertex_id
) {
1456 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
1457 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
1458 ctx
->vertex_id
= create_input(ctx
, 0);
1459 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
1461 dst
[0] = ctx
->vertex_id
;
1463 case nir_intrinsic_load_instance_id
:
1464 if (!ctx
->instance_id
) {
1465 ctx
->instance_id
= create_input(ctx
, 0);
1466 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1469 dst
[0] = ctx
->instance_id
;
1471 case nir_intrinsic_load_sample_id
:
1472 ctx
->so
->per_samp
= true;
1474 case nir_intrinsic_load_sample_id_no_per_sample
:
1475 if (!ctx
->samp_id
) {
1476 ctx
->samp_id
= create_input(ctx
, 0);
1477 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
1478 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
,
1481 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
1483 case nir_intrinsic_load_sample_mask_in
:
1484 if (!ctx
->samp_mask_in
) {
1485 ctx
->samp_mask_in
= create_input(ctx
, 0);
1486 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
,
1489 dst
[0] = ctx
->samp_mask_in
;
1491 case nir_intrinsic_load_user_clip_plane
:
1492 idx
= nir_intrinsic_ucp_id(intr
);
1493 for (int i
= 0; i
< intr
->num_components
; i
++) {
1494 unsigned n
= idx
* 4 + i
;
1495 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1498 case nir_intrinsic_load_front_face
:
1499 if (!ctx
->frag_face
) {
1500 ctx
->so
->frag_face
= true;
1501 ctx
->frag_face
= create_input(ctx
, 0);
1502 add_sysval_input(ctx
, SYSTEM_VALUE_FRONT_FACE
, ctx
->frag_face
);
1503 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1505 /* for fragface, we get -1 for back and 0 for front. However this is
1506 * the inverse of what nir expects (where ~0 is true).
1508 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
1509 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
1511 case nir_intrinsic_load_local_invocation_id
:
1512 if (!ctx
->local_invocation_id
) {
1513 ctx
->local_invocation_id
= create_input_compmask(ctx
, 0, 0x7);
1514 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
1515 0x7, ctx
->local_invocation_id
);
1517 ir3_split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
1519 case nir_intrinsic_load_work_group_id
:
1520 if (!ctx
->work_group_id
) {
1521 ctx
->work_group_id
= create_input_compmask(ctx
, 0, 0x7);
1522 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
1523 0x7, ctx
->work_group_id
);
1524 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
1526 ir3_split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
1528 case nir_intrinsic_load_num_work_groups
:
1529 for (int i
= 0; i
< intr
->num_components
; i
++) {
1530 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
1533 case nir_intrinsic_load_local_group_size
:
1534 for (int i
= 0; i
< intr
->num_components
; i
++) {
1535 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
1538 case nir_intrinsic_discard_if
:
1539 case nir_intrinsic_discard
: {
1540 struct ir3_instruction
*cond
, *kill
;
1542 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1543 /* conditional discard: */
1544 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1545 cond
= ir3_b2n(b
, src
[0]);
1547 /* unconditional discard: */
1548 cond
= create_immed(b
, 1);
1551 /* NOTE: only cmps.*.* can write p0.x: */
1552 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1553 cond
->cat2
.condition
= IR3_COND_NE
;
1555 /* condition always goes in predicate register: */
1556 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1558 kill
= ir3_KILL(b
, cond
, 0);
1559 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1561 array_insert(b
, b
->keeps
, kill
);
1562 ctx
->so
->no_earlyz
= true;
1567 ir3_context_error(ctx
, "Unhandled intrinsic type: %s\n",
1568 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1573 ir3_put_dst(ctx
, &intr
->dest
);
1577 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
1579 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &instr
->def
,
1580 instr
->def
.num_components
);
1581 type_t type
= (instr
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
1583 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1584 dst
[i
] = create_immed_typed(ctx
->block
, instr
->value
[i
].u32
, type
);
1588 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
1590 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &undef
->def
,
1591 undef
->def
.num_components
);
1592 type_t type
= (undef
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
1594 /* backend doesn't want undefined instructions, so just plug
1597 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1598 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
1602 * texture fetch/sample instructions:
1606 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1608 unsigned coords
, flags
= 0;
1610 /* note: would use tex->coord_components.. except txs.. also,
1611 * since array index goes after shadow ref, we don't want to
1614 switch (tex
->sampler_dim
) {
1615 case GLSL_SAMPLER_DIM_1D
:
1616 case GLSL_SAMPLER_DIM_BUF
:
1619 case GLSL_SAMPLER_DIM_2D
:
1620 case GLSL_SAMPLER_DIM_RECT
:
1621 case GLSL_SAMPLER_DIM_EXTERNAL
:
1622 case GLSL_SAMPLER_DIM_MS
:
1625 case GLSL_SAMPLER_DIM_3D
:
1626 case GLSL_SAMPLER_DIM_CUBE
:
1628 flags
|= IR3_INSTR_3D
;
1631 unreachable("bad sampler_dim");
1634 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1635 flags
|= IR3_INSTR_S
;
1637 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1638 flags
|= IR3_INSTR_A
;
1644 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1645 * or immediate (in which case it will get lowered later to a non .s2en
1646 * version of the tex instruction which encode tex/samp as immediates:
1648 static struct ir3_instruction
*
1649 get_tex_samp_tex_src(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1651 int texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
);
1652 int sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
);
1653 struct ir3_instruction
*texture
, *sampler
;
1655 if (texture_idx
>= 0) {
1656 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
1657 texture
= ir3_COV(ctx
->block
, texture
, TYPE_U32
, TYPE_U16
);
1659 /* TODO what to do for dynamic case? I guess we only need the
1660 * max index for astc srgb workaround so maybe not a problem
1661 * to worry about if we don't enable indirect samplers for
1664 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex
->texture_index
);
1665 texture
= create_immed_typed(ctx
->block
, tex
->texture_index
, TYPE_U16
);
1668 if (sampler_idx
>= 0) {
1669 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
1670 sampler
= ir3_COV(ctx
->block
, sampler
, TYPE_U32
, TYPE_U16
);
1672 sampler
= create_immed_typed(ctx
->block
, tex
->sampler_index
, TYPE_U16
);
1675 return ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1682 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1684 struct ir3_block
*b
= ctx
->block
;
1685 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1686 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
1687 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
1688 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1689 unsigned i
, coords
, flags
, ncomp
;
1690 unsigned nsrc0
= 0, nsrc1
= 0;
1694 ncomp
= nir_dest_num_components(tex
->dest
);
1696 coord
= off
= ddx
= ddy
= NULL
;
1697 lod
= proj
= compare
= sample_index
= NULL
;
1699 dst
= ir3_get_dst(ctx
, &tex
->dest
, ncomp
);
1701 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1702 switch (tex
->src
[i
].src_type
) {
1703 case nir_tex_src_coord
:
1704 coord
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1706 case nir_tex_src_bias
:
1707 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1710 case nir_tex_src_lod
:
1711 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1714 case nir_tex_src_comparator
: /* shadow comparator */
1715 compare
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1717 case nir_tex_src_projector
:
1718 proj
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1721 case nir_tex_src_offset
:
1722 off
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1725 case nir_tex_src_ddx
:
1726 ddx
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1728 case nir_tex_src_ddy
:
1729 ddy
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1731 case nir_tex_src_ms_index
:
1732 sample_index
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1734 case nir_tex_src_texture_offset
:
1735 case nir_tex_src_sampler_offset
:
1736 /* handled in get_tex_samp_src() */
1739 ir3_context_error(ctx
, "Unhandled NIR tex src type: %d\n",
1740 tex
->src
[i
].src_type
);
1746 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
1747 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1748 case nir_texop_txl
: opc
= OPC_SAML
; break;
1749 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1750 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1751 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
1753 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1754 * what blob does, seems gather is broken?), and a3xx did
1755 * not support it (but probably could also emulate).
1757 switch (tex
->component
) {
1758 case 0: opc
= OPC_GATHER4R
; break;
1759 case 1: opc
= OPC_GATHER4G
; break;
1760 case 2: opc
= OPC_GATHER4B
; break;
1761 case 3: opc
= OPC_GATHER4A
; break;
1764 case nir_texop_txf_ms_fb
:
1765 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
1767 ir3_context_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1771 tex_info(tex
, &flags
, &coords
);
1774 * lay out the first argument in the proper order:
1775 * - actual coordinates first
1776 * - shadow reference
1779 * - starting at offset 4, dpdx.xy, dpdy.xy
1781 * bias/lod go into the second arg
1784 /* insert tex coords: */
1785 for (i
= 0; i
< coords
; i
++)
1790 /* scale up integer coords for TXF based on the LOD */
1791 if (ctx
->compiler
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1793 for (i
= 0; i
< coords
; i
++)
1794 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
1798 /* hw doesn't do 1d, so we treat it as 2d with
1799 * height of 1, and patch up the y coord.
1802 src0
[nsrc0
++] = create_immed(b
, 0);
1804 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1808 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1809 src0
[nsrc0
++] = compare
;
1811 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
1812 struct ir3_instruction
*idx
= coord
[coords
];
1814 /* the array coord for cube arrays needs 0.5 added to it */
1815 if (ctx
->compiler
->array_index_add_half
&& !is_isam(opc
))
1816 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
1818 src0
[nsrc0
++] = idx
;
1822 src0
[nsrc0
++] = proj
;
1823 flags
|= IR3_INSTR_P
;
1826 /* pad to 4, then ddx/ddy: */
1827 if (tex
->op
== nir_texop_txd
) {
1829 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1830 for (i
= 0; i
< coords
; i
++)
1831 src0
[nsrc0
++] = ddx
[i
];
1833 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1834 for (i
= 0; i
< coords
; i
++)
1835 src0
[nsrc0
++] = ddy
[i
];
1837 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1840 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1841 * with scaled x coord according to requested sample:
1843 if (opc
== OPC_ISAMM
) {
1844 if (ctx
->compiler
->txf_ms_with_isaml
) {
1845 /* the samples are laid out in x dimension as
1847 * x_ms = (x << ms) + sample_index;
1849 struct ir3_instruction
*ms
;
1850 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
1852 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
1853 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
1857 src0
[nsrc0
++] = sample_index
;
1862 * second argument (if applicable):
1867 if (has_off
| has_lod
| has_bias
) {
1869 unsigned off_coords
= coords
;
1870 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1872 for (i
= 0; i
< off_coords
; i
++)
1873 src1
[nsrc1
++] = off
[i
];
1875 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1876 flags
|= IR3_INSTR_O
;
1879 if (has_lod
| has_bias
)
1880 src1
[nsrc1
++] = lod
;
1883 switch (tex
->dest_type
) {
1884 case nir_type_invalid
:
1885 case nir_type_float
:
1896 unreachable("bad dest_type");
1899 if (opc
== OPC_GETLOD
)
1902 struct ir3_instruction
*samp_tex
;
1904 if (tex
->op
== nir_texop_txf_ms_fb
) {
1905 /* only expect a single txf_ms_fb per shader: */
1906 compile_assert(ctx
, !ctx
->so
->fb_read
);
1907 compile_assert(ctx
, ctx
->so
->type
== MESA_SHADER_FRAGMENT
);
1909 ctx
->so
->fb_read
= true;
1910 samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1911 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
1912 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
1915 ctx
->so
->num_samp
++;
1917 samp_tex
= get_tex_samp_tex_src(ctx
, tex
);
1920 struct ir3_instruction
*col0
= ir3_create_collect(ctx
, src0
, nsrc0
);
1921 struct ir3_instruction
*col1
= ir3_create_collect(ctx
, src1
, nsrc1
);
1923 sam
= ir3_SAM(b
, opc
, type
, MASK(ncomp
), flags
,
1924 samp_tex
, col0
, col1
);
1926 if ((ctx
->astc_srgb
& (1 << tex
->texture_index
)) && !nir_tex_instr_is_query(tex
)) {
1927 /* only need first 3 components: */
1928 sam
->regs
[0]->wrmask
= 0x7;
1929 ir3_split_dest(b
, dst
, sam
, 0, 3);
1931 /* we need to sample the alpha separately with a non-ASTC
1934 sam
= ir3_SAM(b
, opc
, type
, 0b1000, flags
,
1935 samp_tex
, col0
, col1
);
1937 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
1939 /* fixup .w component: */
1940 ir3_split_dest(b
, &dst
[3], sam
, 3, 1);
1942 /* normal (non-workaround) case: */
1943 ir3_split_dest(b
, dst
, sam
, 0, ncomp
);
1946 /* GETLOD returns results in 4.8 fixed point */
1947 if (opc
== OPC_GETLOD
) {
1948 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
1950 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
1951 for (i
= 0; i
< 2; i
++) {
1952 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_U32
, TYPE_F32
), 0,
1957 ir3_put_dst(ctx
, &tex
->dest
);
1961 emit_tex_query_levels(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1963 struct ir3_block
*b
= ctx
->block
;
1964 struct ir3_instruction
**dst
, *sam
;
1966 dst
= ir3_get_dst(ctx
, &tex
->dest
, 1);
1968 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, 0b0100, 0,
1969 get_tex_samp_tex_src(ctx
, tex
), NULL
, NULL
);
1971 /* even though there is only one component, since it ends
1972 * up in .z rather than .x, we need a split_dest()
1974 ir3_split_dest(b
, dst
, sam
, 0, 3);
1976 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1977 * the value in TEX_CONST_0 is zero-based.
1979 if (ctx
->compiler
->levels_add_one
)
1980 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
1982 ir3_put_dst(ctx
, &tex
->dest
);
1986 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1988 struct ir3_block
*b
= ctx
->block
;
1989 struct ir3_instruction
**dst
, *sam
;
1990 struct ir3_instruction
*lod
;
1991 unsigned flags
, coords
;
1993 tex_info(tex
, &flags
, &coords
);
1995 /* Actually we want the number of dimensions, not coordinates. This
1996 * distinction only matters for cubes.
1998 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2001 dst
= ir3_get_dst(ctx
, &tex
->dest
, 4);
2003 compile_assert(ctx
, tex
->num_srcs
== 1);
2004 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2006 lod
= ir3_get_src(ctx
, &tex
->src
[0].src
)[0];
2008 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, 0b1111, flags
,
2009 get_tex_samp_tex_src(ctx
, tex
), lod
, NULL
);
2011 ir3_split_dest(b
, dst
, sam
, 0, 4);
2013 /* Array size actually ends up in .w rather than .z. This doesn't
2014 * matter for miplevel 0, but for higher mips the value in z is
2015 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2016 * returned, which means that we have to add 1 to it for arrays.
2018 if (tex
->is_array
) {
2019 if (ctx
->compiler
->levels_add_one
) {
2020 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2022 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2026 ir3_put_dst(ctx
, &tex
->dest
);
2030 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2032 switch (jump
->type
) {
2033 case nir_jump_break
:
2034 case nir_jump_continue
:
2035 case nir_jump_return
:
2036 /* I *think* we can simply just ignore this, and use the
2037 * successor block link to figure out where we need to
2038 * jump to for break/continue
2042 ir3_context_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2048 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2050 switch (instr
->type
) {
2051 case nir_instr_type_alu
:
2052 emit_alu(ctx
, nir_instr_as_alu(instr
));
2054 case nir_instr_type_deref
:
2055 /* ignored, handled as part of the intrinsic they are src to */
2057 case nir_instr_type_intrinsic
:
2058 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2060 case nir_instr_type_load_const
:
2061 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2063 case nir_instr_type_ssa_undef
:
2064 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2066 case nir_instr_type_tex
: {
2067 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2068 /* couple tex instructions get special-cased:
2072 emit_tex_txs(ctx
, tex
);
2074 case nir_texop_query_levels
:
2075 emit_tex_query_levels(ctx
, tex
);
2083 case nir_instr_type_jump
:
2084 emit_jump(ctx
, nir_instr_as_jump(instr
));
2086 case nir_instr_type_phi
:
2087 /* we have converted phi webs to regs in NIR by now */
2088 ir3_context_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2090 case nir_instr_type_call
:
2091 case nir_instr_type_parallel_copy
:
2092 ir3_context_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2097 static struct ir3_block
*
2098 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2100 struct ir3_block
*block
;
2101 struct hash_entry
*hentry
;
2104 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2106 return hentry
->data
;
2108 block
= ir3_block_create(ctx
->ir
);
2109 block
->nblock
= nblock
;
2110 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2112 block
->predecessors_count
= nblock
->predecessors
->entries
;
2113 block
->predecessors
= ralloc_array_size(block
,
2114 sizeof(block
->predecessors
[0]), block
->predecessors_count
);
2116 set_foreach(nblock
->predecessors
, sentry
) {
2117 block
->predecessors
[i
++] = get_block(ctx
, sentry
->key
);
2124 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2126 struct ir3_block
*block
= get_block(ctx
, nblock
);
2128 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2129 if (nblock
->successors
[i
]) {
2130 block
->successors
[i
] =
2131 get_block(ctx
, nblock
->successors
[i
]);
2136 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2138 /* re-emit addr register in each block if needed: */
2139 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
2140 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
2141 ctx
->addr_ht
[i
] = NULL
;
2144 nir_foreach_instr(instr
, nblock
) {
2145 ctx
->cur_instr
= instr
;
2146 emit_instr(ctx
, instr
);
2147 ctx
->cur_instr
= NULL
;
2153 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2156 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2158 struct ir3_instruction
*condition
= ir3_get_src(ctx
, &nif
->condition
)[0];
2160 ctx
->block
->condition
=
2161 ir3_get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2163 emit_cf_list(ctx
, &nif
->then_list
);
2164 emit_cf_list(ctx
, &nif
->else_list
);
2168 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2170 emit_cf_list(ctx
, &nloop
->body
);
2175 stack_push(struct ir3_context
*ctx
)
2178 ctx
->max_stack
= MAX2(ctx
->max_stack
, ctx
->stack
);
2182 stack_pop(struct ir3_context
*ctx
)
2184 compile_assert(ctx
, ctx
->stack
> 0);
2189 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2191 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2192 switch (node
->type
) {
2193 case nir_cf_node_block
:
2194 emit_block(ctx
, nir_cf_node_as_block(node
));
2196 case nir_cf_node_if
:
2198 emit_if(ctx
, nir_cf_node_as_if(node
));
2201 case nir_cf_node_loop
:
2203 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2206 case nir_cf_node_function
:
2207 ir3_context_error(ctx
, "TODO\n");
2213 /* emit stream-out code. At this point, the current block is the original
2214 * (nir) end block, and nir ensures that all flow control paths terminate
2215 * into the end block. We re-purpose the original end block to generate
2216 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2217 * block holding stream-out write instructions, followed by the new end
2221 * p0.x = (vtxcnt < maxvtxcnt)
2222 * // succs: blockStreamOut, blockNewEnd
2225 * ... stream-out instructions ...
2226 * // succs: blockNewEnd
2232 emit_stream_out(struct ir3_context
*ctx
)
2234 struct ir3
*ir
= ctx
->ir
;
2235 struct ir3_stream_output_info
*strmout
=
2236 &ctx
->so
->shader
->stream_output
;
2237 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2238 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2239 struct ir3_instruction
*bases
[IR3_MAX_SO_BUFFERS
];
2241 /* create vtxcnt input in input block at top of shader,
2242 * so that it is seen as live over the entire duration
2245 vtxcnt
= create_input(ctx
, 0);
2246 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2248 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2250 /* at this point, we are at the original 'end' block,
2251 * re-purpose this block to stream-out condition, then
2252 * append stream-out block and new-end block
2254 orig_end_block
= ctx
->block
;
2256 // TODO these blocks need to update predecessors..
2257 // maybe w/ store_global intrinsic, we could do this
2258 // stuff in nir->nir pass
2260 stream_out_block
= ir3_block_create(ir
);
2261 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2263 new_end_block
= ir3_block_create(ir
);
2264 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2266 orig_end_block
->successors
[0] = stream_out_block
;
2267 orig_end_block
->successors
[1] = new_end_block
;
2268 stream_out_block
->successors
[0] = new_end_block
;
2270 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2271 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2272 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2273 cond
->cat2
.condition
= IR3_COND_LT
;
2275 /* condition goes on previous block to the conditional,
2276 * since it is used to pick which of the two successor
2279 orig_end_block
->condition
= cond
;
2281 /* switch to stream_out_block to generate the stream-out
2284 ctx
->block
= stream_out_block
;
2286 /* Calculate base addresses based on vtxcnt. Instructions
2287 * generated for bases not used in following loop will be
2288 * stripped out in the backend.
2290 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2291 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
2292 unsigned stride
= strmout
->stride
[i
];
2293 struct ir3_instruction
*base
, *off
;
2295 base
= create_uniform(ctx
->block
, regid(const_state
->offsets
.tfbo
, i
));
2297 /* 24-bit should be enough: */
2298 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2299 create_immed(ctx
->block
, stride
* 4), 0);
2301 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2304 /* Generate the per-output store instructions: */
2305 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2306 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2307 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2308 struct ir3_instruction
*base
, *out
, *stg
;
2310 base
= bases
[strmout
->output
[i
].output_buffer
];
2311 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2313 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2314 create_immed(ctx
->block
, 1), 0);
2315 stg
->cat6
.type
= TYPE_U32
;
2316 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2318 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2322 /* and finally switch to the new_end_block: */
2323 ctx
->block
= new_end_block
;
2327 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2329 nir_metadata_require(impl
, nir_metadata_block_index
);
2331 compile_assert(ctx
, ctx
->stack
== 0);
2333 emit_cf_list(ctx
, &impl
->body
);
2334 emit_block(ctx
, impl
->end_block
);
2336 compile_assert(ctx
, ctx
->stack
== 0);
2338 /* at this point, we should have a single empty block,
2339 * into which we emit the 'end' instruction.
2341 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2343 /* If stream-out (aka transform-feedback) enabled, emit the
2344 * stream-out instructions, followed by a new empty block (into
2345 * which the 'end' instruction lands).
2347 * NOTE: it is done in this order, rather than inserting before
2348 * we emit end_block, because NIR guarantees that all blocks
2349 * flow into end_block, and that end_block has no successors.
2350 * So by re-purposing end_block as the first block of stream-
2351 * out, we guarantee that all exit paths flow into the stream-
2354 if ((ctx
->compiler
->gpu_id
< 500) &&
2355 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2356 !ctx
->so
->binning_pass
) {
2357 debug_assert(ctx
->so
->type
== MESA_SHADER_VERTEX
);
2358 emit_stream_out(ctx
);
2361 ir3_END(ctx
->block
);
2365 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2367 struct ir3_shader_variant
*so
= ctx
->so
;
2368 unsigned ncomp
= glsl_get_components(in
->type
);
2369 unsigned n
= in
->data
.driver_location
;
2370 unsigned frac
= in
->data
.location_frac
;
2371 unsigned slot
= in
->data
.location
;
2373 /* skip unread inputs, we could end up with (for example), unsplit
2374 * matrix/etc inputs in the case they are not read, so just silently
2380 so
->inputs
[n
].slot
= slot
;
2381 so
->inputs
[n
].compmask
= (1 << (ncomp
+ frac
)) - 1;
2382 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2383 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2384 so
->inputs
[n
].ncomp
= ncomp
;
2386 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2388 /* if any varyings have 'sample' qualifer, that triggers us
2389 * to run in per-sample mode:
2391 so
->per_samp
|= in
->data
.sample
;
2393 for (int i
= 0; i
< ncomp
; i
++) {
2394 struct ir3_instruction
*instr
= NULL
;
2395 unsigned idx
= (n
* 4) + i
+ frac
;
2397 if (slot
== VARYING_SLOT_POS
) {
2398 ir3_context_error(ctx
, "fragcoord should be a sysval!\n");
2399 } else if (slot
== VARYING_SLOT_PNTC
) {
2400 /* see for example st_nir_fixup_varying_slots().. this is
2401 * maybe a bit mesa/st specific. But we need things to line
2402 * up for this in fdN_program:
2403 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2404 * if (emit->sprite_coord_enable & texmask) {
2408 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2409 so
->inputs
[n
].bary
= true;
2410 instr
= create_frag_input(ctx
, false, idx
);
2412 /* detect the special case for front/back colors where
2413 * we need to do flat vs smooth shading depending on
2416 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2418 case VARYING_SLOT_COL0
:
2419 case VARYING_SLOT_COL1
:
2420 case VARYING_SLOT_BFC0
:
2421 case VARYING_SLOT_BFC1
:
2422 so
->inputs
[n
].rasterflat
= true;
2429 if (ctx
->compiler
->flat_bypass
) {
2430 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2431 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2432 so
->inputs
[n
].use_ldlv
= true;
2435 so
->inputs
[n
].bary
= true;
2437 instr
= create_frag_input(ctx
, so
->inputs
[n
].use_ldlv
, idx
);
2440 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2442 ctx
->ir
->inputs
[idx
] = instr
;
2444 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
2445 for (int i
= 0; i
< ncomp
; i
++) {
2446 unsigned idx
= (n
* 4) + i
+ frac
;
2447 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2448 ctx
->ir
->inputs
[idx
] = create_input(ctx
, idx
);
2451 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2454 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== MESA_SHADER_VERTEX
)) {
2455 so
->total_in
+= ncomp
;
2459 /* Initially we assign non-packed inloc's for varyings, as we don't really
2460 * know up-front which components will be unused. After all the compilation
2461 * stages we scan the shader to see which components are actually used, and
2462 * re-pack the inlocs to eliminate unneeded varyings.
2465 pack_inlocs(struct ir3_context
*ctx
)
2467 struct ir3_shader_variant
*so
= ctx
->so
;
2468 uint8_t used_components
[so
->inputs_count
];
2470 memset(used_components
, 0, sizeof(used_components
));
2473 * First Step: scan shader to find which bary.f/ldlv remain:
2476 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2477 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
2478 if (is_input(instr
)) {
2479 unsigned inloc
= instr
->regs
[1]->iim_val
;
2480 unsigned i
= inloc
/ 4;
2481 unsigned j
= inloc
% 4;
2483 compile_assert(ctx
, instr
->regs
[1]->flags
& IR3_REG_IMMED
);
2484 compile_assert(ctx
, i
< so
->inputs_count
);
2486 used_components
[i
] |= 1 << j
;
2492 * Second Step: reassign varying inloc/slots:
2495 unsigned actual_in
= 0;
2498 for (unsigned i
= 0; i
< so
->inputs_count
; i
++) {
2499 unsigned compmask
= 0, maxcomp
= 0;
2501 so
->inputs
[i
].ncomp
= 0;
2502 so
->inputs
[i
].inloc
= inloc
;
2503 so
->inputs
[i
].bary
= false;
2505 for (unsigned j
= 0; j
< 4; j
++) {
2506 if (!(used_components
[i
] & (1 << j
)))
2509 compmask
|= (1 << j
);
2511 so
->inputs
[i
].ncomp
++;
2514 /* at this point, since used_components[i] mask is only
2515 * considering varyings (ie. not sysvals) we know this
2518 so
->inputs
[i
].bary
= true;
2521 if (so
->inputs
[i
].bary
) {
2523 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
2529 * Third Step: reassign packed inloc's:
2532 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2533 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
2534 if (is_input(instr
)) {
2535 unsigned inloc
= instr
->regs
[1]->iim_val
;
2536 unsigned i
= inloc
/ 4;
2537 unsigned j
= inloc
% 4;
2539 instr
->regs
[1]->iim_val
= so
->inputs
[i
].inloc
+ j
;
2546 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
2548 struct ir3_shader_variant
*so
= ctx
->so
;
2549 unsigned ncomp
= glsl_get_components(out
->type
);
2550 unsigned n
= out
->data
.driver_location
;
2551 unsigned frac
= out
->data
.location_frac
;
2552 unsigned slot
= out
->data
.location
;
2555 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2557 case FRAG_RESULT_DEPTH
:
2558 comp
= 2; /* tgsi will write to .z component */
2559 so
->writes_pos
= true;
2561 case FRAG_RESULT_COLOR
:
2564 case FRAG_RESULT_SAMPLE_MASK
:
2565 so
->writes_smask
= true;
2568 if (slot
>= FRAG_RESULT_DATA0
)
2570 ir3_context_error(ctx
, "unknown FS output name: %s\n",
2571 gl_frag_result_name(slot
));
2573 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
2575 case VARYING_SLOT_POS
:
2576 so
->writes_pos
= true;
2578 case VARYING_SLOT_PSIZ
:
2579 so
->writes_psize
= true;
2581 case VARYING_SLOT_COL0
:
2582 case VARYING_SLOT_COL1
:
2583 case VARYING_SLOT_BFC0
:
2584 case VARYING_SLOT_BFC1
:
2585 case VARYING_SLOT_FOGC
:
2586 case VARYING_SLOT_CLIP_DIST0
:
2587 case VARYING_SLOT_CLIP_DIST1
:
2588 case VARYING_SLOT_CLIP_VERTEX
:
2591 if (slot
>= VARYING_SLOT_VAR0
)
2593 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2595 ir3_context_error(ctx
, "unknown VS output name: %s\n",
2596 gl_varying_slot_name(slot
));
2599 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2602 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2604 so
->outputs
[n
].slot
= slot
;
2605 so
->outputs
[n
].regid
= regid(n
, comp
);
2606 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2608 for (int i
= 0; i
< ncomp
; i
++) {
2609 unsigned idx
= (n
* 4) + i
+ frac
;
2610 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
2611 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2614 /* if varying packing doesn't happen, we could end up in a situation
2615 * with "holes" in the output, and since the per-generation code that
2616 * sets up varying linkage registers doesn't expect to have more than
2617 * one varying per vec4 slot, pad the holes.
2619 * Note that this should probably generate a performance warning of
2622 for (int i
= 0; i
< frac
; i
++) {
2623 unsigned idx
= (n
* 4) + i
;
2624 if (!ctx
->ir
->outputs
[idx
]) {
2625 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2631 max_drvloc(struct exec_list
*vars
)
2634 nir_foreach_variable(var
, vars
) {
2635 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
2640 static const unsigned max_sysvals
[] = {
2641 [MESA_SHADER_FRAGMENT
] = 24, // TODO
2642 [MESA_SHADER_VERTEX
] = 16,
2643 [MESA_SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
2644 [MESA_SHADER_KERNEL
] = 16, // TODO how many do we actually need?
2648 emit_instructions(struct ir3_context
*ctx
)
2650 unsigned ninputs
, noutputs
;
2651 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
2653 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
2654 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
2656 /* we need to leave room for sysvals:
2658 ninputs
+= max_sysvals
[ctx
->so
->type
];
2660 ctx
->ir
= ir3_create(ctx
->compiler
, ctx
->so
->type
, ninputs
, noutputs
);
2662 /* Create inputs in first block: */
2663 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2664 ctx
->in_block
= ctx
->block
;
2665 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2667 ninputs
-= max_sysvals
[ctx
->so
->type
];
2669 /* for fragment shader, the vcoord input register is used as the
2670 * base for bary.f varying fetch instrs:
2672 * TODO defer creating ctx->ij_pixel and corresponding sysvals
2673 * until emit_intrinsic when we know they are actually needed.
2674 * For now, we defer creating ctx->ij_centroid, etc, since we
2675 * only need ij_pixel for "old style" varying inputs (ie.
2678 struct ir3_instruction
*vcoord
= NULL
;
2679 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2680 struct ir3_instruction
*xy
[2];
2682 vcoord
= create_input_compmask(ctx
, 0, 0x3);
2683 ir3_split_dest(ctx
->block
, xy
, vcoord
, 0, 2);
2685 ctx
->ij_pixel
= ir3_create_collect(ctx
, xy
, 2);
2689 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
2690 setup_input(ctx
, var
);
2693 /* Defer add_sysval_input() stuff until after setup_inputs(),
2694 * because sysvals need to be appended after varyings:
2697 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_BARYCENTRIC_PIXEL
,
2701 /* Setup outputs: */
2702 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
2703 setup_output(ctx
, var
);
2706 /* Find # of samplers: */
2707 nir_foreach_variable(var
, &ctx
->s
->uniforms
) {
2708 ctx
->so
->num_samp
+= glsl_type_get_sampler_count(var
->type
);
2709 /* just assume that we'll be reading from images.. if it
2710 * is write-only we don't have to count it, but not sure
2711 * if there is a good way to know?
2713 ctx
->so
->num_samp
+= glsl_type_get_image_count(var
->type
);
2716 /* NOTE: need to do something more clever when we support >1 fxn */
2717 nir_foreach_register(reg
, &fxn
->registers
) {
2718 ir3_declare_array(ctx
, reg
);
2720 /* And emit the body: */
2722 emit_function(ctx
, fxn
);
2725 /* from NIR perspective, we actually have varying inputs. But the varying
2726 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2727 * only actual inputs are the sysvals.
2730 fixup_frag_inputs(struct ir3_context
*ctx
)
2732 struct ir3_shader_variant
*so
= ctx
->so
;
2733 struct ir3
*ir
= ctx
->ir
;
2736 /* sysvals should appear at the end of the inputs, drop everything else: */
2737 while ((i
< so
->inputs_count
) && !so
->inputs
[i
].sysval
)
2740 /* at IR level, inputs are always blocks of 4 scalars: */
2743 ir
->inputs
= &ir
->inputs
[i
];
2747 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2748 * need to assign the tex state indexes for these after we know the
2752 fixup_astc_srgb(struct ir3_context
*ctx
)
2754 struct ir3_shader_variant
*so
= ctx
->so
;
2755 /* indexed by original tex idx, value is newly assigned alpha sampler
2756 * state tex idx. Zero is invalid since there is at least one sampler
2759 unsigned alt_tex_state
[16] = {0};
2760 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
2763 so
->astc_srgb
.base
= tex_idx
;
2765 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
2766 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
2768 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
2770 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
2771 /* assign new alternate/alpha tex state slot: */
2772 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
2773 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
2774 so
->astc_srgb
.count
++;
2777 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
2782 fixup_binning_pass(struct ir3_context
*ctx
)
2784 struct ir3_shader_variant
*so
= ctx
->so
;
2785 struct ir3
*ir
= ctx
->ir
;
2788 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2789 unsigned slot
= so
->outputs
[i
].slot
;
2791 /* throw away everything but first position/psize */
2792 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2794 so
->outputs
[j
] = so
->outputs
[i
];
2795 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2796 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2797 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2798 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2803 so
->outputs_count
= j
;
2804 ir
->noutputs
= j
* 4;
2808 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2809 struct ir3_shader_variant
*so
)
2811 struct ir3_context
*ctx
;
2813 struct ir3_instruction
**inputs
;
2815 int ret
= 0, max_bary
;
2819 ctx
= ir3_context_init(compiler
, so
);
2821 DBG("INIT failed!");
2826 emit_instructions(ctx
);
2829 DBG("EMIT failed!");
2834 ir
= so
->ir
= ctx
->ir
;
2836 /* keep track of the inputs from TGSI perspective.. */
2837 inputs
= ir
->inputs
;
2839 /* but fixup actual inputs for frag shader: */
2840 if (so
->type
== MESA_SHADER_FRAGMENT
)
2841 fixup_frag_inputs(ctx
);
2843 /* at this point, for binning pass, throw away unneeded outputs: */
2844 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
< 600))
2845 fixup_binning_pass(ctx
);
2847 /* if we want half-precision outputs, mark the output registers
2850 if (so
->key
.half_precision
) {
2851 for (i
= 0; i
< ir
->noutputs
; i
++) {
2852 struct ir3_instruction
*out
= ir
->outputs
[i
];
2857 /* if frag shader writes z, that needs to be full precision: */
2858 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
2861 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2862 /* output could be a fanout (ie. texture fetch output)
2863 * in which case we need to propagate the half-reg flag
2864 * up to the definer so that RA sees it:
2866 if (out
->opc
== OPC_META_FO
) {
2867 out
= out
->regs
[1]->instr
;
2868 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2871 if (out
->opc
== OPC_MOV
) {
2872 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2877 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2878 printf("BEFORE CP:\n");
2884 /* at this point, for binning pass, throw away unneeded outputs:
2885 * Note that for a6xx and later, we do this after ir3_cp to ensure
2886 * that the uniform/constant layout for BS and VS matches, so that
2887 * we can re-use same VS_CONST state group.
2889 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
>= 600))
2890 fixup_binning_pass(ctx
);
2892 /* Insert mov if there's same instruction for each output.
2893 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
2895 for (int i
= ir
->noutputs
- 1; i
>= 0; i
--) {
2896 if (!ir
->outputs
[i
])
2898 for (unsigned j
= 0; j
< i
; j
++) {
2899 if (ir
->outputs
[i
] == ir
->outputs
[j
]) {
2901 ir3_MOV(ir
->outputs
[i
]->block
, ir
->outputs
[i
], TYPE_F32
);
2906 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2907 printf("BEFORE GROUPING:\n");
2911 ir3_sched_add_deps(ir
);
2913 /* Group left/right neighbors, inserting mov's where needed to
2918 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2919 printf("AFTER GROUPING:\n");
2925 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2926 printf("AFTER DEPTH:\n");
2930 /* do Sethi–Ullman numbering before scheduling: */
2933 ret
= ir3_sched(ir
);
2935 DBG("SCHED failed!");
2939 if (compiler
->gpu_id
>= 600) {
2940 ir3_a6xx_fixup_atomic_dests(ir
, so
);
2943 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2944 printf("AFTER SCHED:\n");
2948 ret
= ir3_ra(ir
, so
->type
, so
->frag_coord
, so
->frag_face
);
2954 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2955 printf("AFTER RA:\n");
2959 if (so
->type
== MESA_SHADER_FRAGMENT
)
2962 /* fixup input/outputs: */
2963 for (i
= 0; i
< so
->outputs_count
; i
++) {
2964 /* sometimes we get outputs that don't write the .x coord, like:
2966 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
2968 * Presumably the result of varying packing and then eliminating
2969 * some unneeded varyings? Just skip head to the first valid
2970 * component of the output.
2972 for (unsigned j
= 0; j
< 4; j
++) {
2973 struct ir3_instruction
*instr
= ir
->outputs
[(i
*4) + j
];
2975 so
->outputs
[i
].regid
= instr
->regs
[0]->num
;
2976 so
->outputs
[i
].half
= !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
2982 /* Note that some or all channels of an input may be unused: */
2983 for (i
= 0; i
< so
->inputs_count
; i
++) {
2984 unsigned j
, reg
= regid(63,0);
2986 for (j
= 0; j
< 4; j
++) {
2987 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
2989 if (in
&& !(in
->flags
& IR3_INSTR_UNUSED
)) {
2990 reg
= in
->regs
[0]->num
- j
;
2992 compile_assert(ctx
, in
->regs
[0]->flags
& IR3_REG_HALF
);
2994 half
= !!(in
->regs
[0]->flags
& IR3_REG_HALF
);
2998 so
->inputs
[i
].regid
= reg
;
2999 so
->inputs
[i
].half
= half
;
3003 fixup_astc_srgb(ctx
);
3005 /* We need to do legalize after (for frag shader's) the "bary.f"
3006 * offsets (inloc) have been assigned.
3008 ir3_legalize(ir
, &so
->has_ssbo
, &so
->need_pixlod
, &max_bary
);
3010 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3011 printf("AFTER LEGALIZE:\n");
3015 so
->branchstack
= ctx
->max_stack
;
3017 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3018 if (so
->type
== MESA_SHADER_FRAGMENT
)
3019 so
->total_in
= max_bary
+ 1;
3021 so
->max_sun
= ir
->max_sun
;
3026 ir3_destroy(so
->ir
);
3029 ir3_context_free(ctx
);