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[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 ir3_reg_create(mov, 0, 0);
55 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
56 src->instr = collect;
57 src->size = arrsz;
58 src->array.offset = n;
59
60 ir3_instr_set_address(mov, address);
61
62 return mov;
63 }
64
65 static struct ir3_instruction *
66 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
67 {
68 struct ir3_instruction *in;
69
70 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
71 in->inout.block = ctx->in_block;
72 ir3_reg_create(in, n, 0);
73
74 in->regs[0]->wrmask = compmask;
75
76 return in;
77 }
78
79 static struct ir3_instruction *
80 create_input(struct ir3_context *ctx, unsigned n)
81 {
82 return create_input_compmask(ctx, n, 0x1);
83 }
84
85 static struct ir3_instruction *
86 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
87 {
88 struct ir3_block *block = ctx->block;
89 struct ir3_instruction *instr;
90 /* packed inloc is fixed up later: */
91 struct ir3_instruction *inloc = create_immed(block, n);
92
93 if (use_ldlv) {
94 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
95 instr->cat6.type = TYPE_U32;
96 instr->cat6.iim_val = 1;
97 } else {
98 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
99 instr->regs[2]->wrmask = 0x3;
100 }
101
102 return instr;
103 }
104
105 static struct ir3_instruction *
106 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
107 {
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
111 unsigned n = const_state->offsets.driver_param;
112 unsigned r = regid(n + dp / 4, dp % 4);
113 return create_uniform(ctx->block, r);
114 }
115
116 /*
117 * Adreno uses uint rather than having dedicated bool type,
118 * which (potentially) requires some conversion, in particular
119 * when using output of an bool instr to int input, or visa
120 * versa.
121 *
122 * | Adreno | NIR |
123 * -------+---------+-------+-
124 * true | 1 | ~0 |
125 * false | 0 | 0 |
126 *
127 * To convert from an adreno bool (uint) to nir, use:
128 *
129 * absneg.s dst, (neg)src
130 *
131 * To convert back in the other direction:
132 *
133 * absneg.s dst, (abs)arc
134 *
135 * The CP step can clean up the absneg.s that cancel each other
136 * out, and with a slight bit of extra cleverness (to recognize
137 * the instructions which produce either a 0 or 1) can eliminate
138 * the absneg.s's completely when an instruction that wants
139 * 0/1 consumes the result. For example, when a nir 'bcsel'
140 * consumes the result of 'feq'. So we should be able to get by
141 * without a boolean resolve step, and without incuring any
142 * extra penalty in instruction count.
143 */
144
145 /* NIR bool -> native (adreno): */
146 static struct ir3_instruction *
147 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
150 }
151
152 /* native (adreno) -> NIR bool: */
153 static struct ir3_instruction *
154 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
155 {
156 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
157 }
158
159 /*
160 * alu/sfu instructions:
161 */
162
163 static struct ir3_instruction *
164 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
165 unsigned src_bitsize, nir_op op)
166 {
167 type_t src_type, dst_type;
168
169 switch (op) {
170 case nir_op_f2f32:
171 case nir_op_f2f16_rtne:
172 case nir_op_f2f16_rtz:
173 case nir_op_f2f16:
174 case nir_op_f2i32:
175 case nir_op_f2i16:
176 case nir_op_f2i8:
177 case nir_op_f2u32:
178 case nir_op_f2u16:
179 case nir_op_f2u8:
180 switch (src_bitsize) {
181 case 32:
182 src_type = TYPE_F32;
183 break;
184 case 16:
185 src_type = TYPE_F16;
186 break;
187 default:
188 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
189 }
190 break;
191
192 case nir_op_i2f32:
193 case nir_op_i2f16:
194 case nir_op_i2i32:
195 case nir_op_i2i16:
196 case nir_op_i2i8:
197 switch (src_bitsize) {
198 case 32:
199 src_type = TYPE_S32;
200 break;
201 case 16:
202 src_type = TYPE_S16;
203 break;
204 case 8:
205 src_type = TYPE_S8;
206 break;
207 default:
208 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
209 }
210 break;
211
212 case nir_op_u2f32:
213 case nir_op_u2f16:
214 case nir_op_u2u32:
215 case nir_op_u2u16:
216 case nir_op_u2u8:
217 switch (src_bitsize) {
218 case 32:
219 src_type = TYPE_U32;
220 break;
221 case 16:
222 src_type = TYPE_U16;
223 break;
224 case 8:
225 src_type = TYPE_U8;
226 break;
227 default:
228 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
229 }
230 break;
231
232 default:
233 ir3_context_error(ctx, "invalid conversion op: %u", op);
234 }
235
236 switch (op) {
237 case nir_op_f2f32:
238 case nir_op_i2f32:
239 case nir_op_u2f32:
240 dst_type = TYPE_F32;
241 break;
242
243 case nir_op_f2f16_rtne:
244 case nir_op_f2f16_rtz:
245 case nir_op_f2f16:
246 /* TODO how to handle rounding mode? */
247 case nir_op_i2f16:
248 case nir_op_u2f16:
249 dst_type = TYPE_F16;
250 break;
251
252 case nir_op_f2i32:
253 case nir_op_i2i32:
254 dst_type = TYPE_S32;
255 break;
256
257 case nir_op_f2i16:
258 case nir_op_i2i16:
259 dst_type = TYPE_S16;
260 break;
261
262 case nir_op_f2i8:
263 case nir_op_i2i8:
264 dst_type = TYPE_S8;
265 break;
266
267 case nir_op_f2u32:
268 case nir_op_u2u32:
269 dst_type = TYPE_U32;
270 break;
271
272 case nir_op_f2u16:
273 case nir_op_u2u16:
274 dst_type = TYPE_U16;
275 break;
276
277 case nir_op_f2u8:
278 case nir_op_u2u8:
279 dst_type = TYPE_U8;
280 break;
281
282 default:
283 ir3_context_error(ctx, "invalid conversion op: %u", op);
284 }
285
286 return ir3_COV(ctx->block, src, src_type, dst_type);
287 }
288
289 static void
290 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
291 {
292 const nir_op_info *info = &nir_op_infos[alu->op];
293 struct ir3_instruction **dst, *src[info->num_inputs];
294 unsigned bs[info->num_inputs]; /* bit size */
295 struct ir3_block *b = ctx->block;
296 unsigned dst_sz, wrmask;
297 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
298 TYPE_U16 : TYPE_U32;
299
300 if (alu->dest.dest.is_ssa) {
301 dst_sz = alu->dest.dest.ssa.num_components;
302 wrmask = (1 << dst_sz) - 1;
303 } else {
304 dst_sz = alu->dest.dest.reg.reg->num_components;
305 wrmask = alu->dest.write_mask;
306 }
307
308 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
309
310 /* Vectors are special in that they have non-scalarized writemasks,
311 * and just take the first swizzle channel for each argument in
312 * order into each writemask channel.
313 */
314 if ((alu->op == nir_op_vec2) ||
315 (alu->op == nir_op_vec3) ||
316 (alu->op == nir_op_vec4)) {
317
318 for (int i = 0; i < info->num_inputs; i++) {
319 nir_alu_src *asrc = &alu->src[i];
320
321 compile_assert(ctx, !asrc->abs);
322 compile_assert(ctx, !asrc->negate);
323
324 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
325 if (!src[i])
326 src[i] = create_immed_typed(ctx->block, 0, dst_type);
327 dst[i] = ir3_MOV(b, src[i], dst_type);
328 }
329
330 ir3_put_dst(ctx, &alu->dest.dest);
331 return;
332 }
333
334 /* We also get mov's with more than one component for mov's so
335 * handle those specially:
336 */
337 if (alu->op == nir_op_mov) {
338 nir_alu_src *asrc = &alu->src[0];
339 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
340
341 for (unsigned i = 0; i < dst_sz; i++) {
342 if (wrmask & (1 << i)) {
343 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
344 } else {
345 dst[i] = NULL;
346 }
347 }
348
349 ir3_put_dst(ctx, &alu->dest.dest);
350 return;
351 }
352
353 /* General case: We can just grab the one used channel per src. */
354 for (int i = 0; i < info->num_inputs; i++) {
355 unsigned chan = ffs(alu->dest.write_mask) - 1;
356 nir_alu_src *asrc = &alu->src[i];
357
358 compile_assert(ctx, !asrc->abs);
359 compile_assert(ctx, !asrc->negate);
360
361 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
362 bs[i] = nir_src_bit_size(asrc->src);
363
364 compile_assert(ctx, src[i]);
365 }
366
367 switch (alu->op) {
368 case nir_op_f2f32:
369 case nir_op_f2f16_rtne:
370 case nir_op_f2f16_rtz:
371 case nir_op_f2f16:
372 case nir_op_f2i32:
373 case nir_op_f2i16:
374 case nir_op_f2i8:
375 case nir_op_f2u32:
376 case nir_op_f2u16:
377 case nir_op_f2u8:
378 case nir_op_i2f32:
379 case nir_op_i2f16:
380 case nir_op_i2i32:
381 case nir_op_i2i16:
382 case nir_op_i2i8:
383 case nir_op_u2f32:
384 case nir_op_u2f16:
385 case nir_op_u2u32:
386 case nir_op_u2u16:
387 case nir_op_u2u8:
388 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
389 break;
390 case nir_op_f2b32:
391 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
392 dst[0]->cat2.condition = IR3_COND_NE;
393 dst[0] = ir3_n2b(b, dst[0]);
394 break;
395 case nir_op_b2f16:
396 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
397 break;
398 case nir_op_b2f32:
399 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
400 break;
401 case nir_op_b2i8:
402 case nir_op_b2i16:
403 case nir_op_b2i32:
404 dst[0] = ir3_b2n(b, src[0]);
405 break;
406 case nir_op_i2b32:
407 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
408 dst[0]->cat2.condition = IR3_COND_NE;
409 dst[0] = ir3_n2b(b, dst[0]);
410 break;
411
412 case nir_op_fneg:
413 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
414 break;
415 case nir_op_fabs:
416 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
417 break;
418 case nir_op_fmax:
419 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
420 break;
421 case nir_op_fmin:
422 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
423 break;
424 case nir_op_fsat:
425 /* if there is just a single use of the src, and it supports
426 * (sat) bit, we can just fold the (sat) flag back to the
427 * src instruction and create a mov. This is easier for cp
428 * to eliminate.
429 *
430 * TODO probably opc_cat==4 is ok too
431 */
432 if (alu->src[0].src.is_ssa &&
433 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
434 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
435 src[0]->flags |= IR3_INSTR_SAT;
436 dst[0] = ir3_MOV(b, src[0], dst_type);
437 } else {
438 /* otherwise generate a max.f that saturates.. blob does
439 * similar (generating a cat2 mov using max.f)
440 */
441 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
442 dst[0]->flags |= IR3_INSTR_SAT;
443 }
444 break;
445 case nir_op_fmul:
446 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
447 break;
448 case nir_op_fadd:
449 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
450 break;
451 case nir_op_fsub:
452 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
453 break;
454 case nir_op_ffma:
455 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
456 break;
457 case nir_op_fddx:
458 case nir_op_fddx_coarse:
459 dst[0] = ir3_DSX(b, src[0], 0);
460 dst[0]->cat5.type = TYPE_F32;
461 break;
462 case nir_op_fddy:
463 case nir_op_fddy_coarse:
464 dst[0] = ir3_DSY(b, src[0], 0);
465 dst[0]->cat5.type = TYPE_F32;
466 break;
467 break;
468 case nir_op_flt32:
469 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
470 dst[0]->cat2.condition = IR3_COND_LT;
471 dst[0] = ir3_n2b(b, dst[0]);
472 break;
473 case nir_op_fge32:
474 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
475 dst[0]->cat2.condition = IR3_COND_GE;
476 dst[0] = ir3_n2b(b, dst[0]);
477 break;
478 case nir_op_feq32:
479 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
480 dst[0]->cat2.condition = IR3_COND_EQ;
481 dst[0] = ir3_n2b(b, dst[0]);
482 break;
483 case nir_op_fne32:
484 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
485 dst[0]->cat2.condition = IR3_COND_NE;
486 dst[0] = ir3_n2b(b, dst[0]);
487 break;
488 case nir_op_fceil:
489 dst[0] = ir3_CEIL_F(b, src[0], 0);
490 break;
491 case nir_op_ffloor:
492 dst[0] = ir3_FLOOR_F(b, src[0], 0);
493 break;
494 case nir_op_ftrunc:
495 dst[0] = ir3_TRUNC_F(b, src[0], 0);
496 break;
497 case nir_op_fround_even:
498 dst[0] = ir3_RNDNE_F(b, src[0], 0);
499 break;
500 case nir_op_fsign:
501 dst[0] = ir3_SIGN_F(b, src[0], 0);
502 break;
503
504 case nir_op_fsin:
505 dst[0] = ir3_SIN(b, src[0], 0);
506 break;
507 case nir_op_fcos:
508 dst[0] = ir3_COS(b, src[0], 0);
509 break;
510 case nir_op_frsq:
511 dst[0] = ir3_RSQ(b, src[0], 0);
512 break;
513 case nir_op_frcp:
514 dst[0] = ir3_RCP(b, src[0], 0);
515 break;
516 case nir_op_flog2:
517 dst[0] = ir3_LOG2(b, src[0], 0);
518 break;
519 case nir_op_fexp2:
520 dst[0] = ir3_EXP2(b, src[0], 0);
521 break;
522 case nir_op_fsqrt:
523 dst[0] = ir3_SQRT(b, src[0], 0);
524 break;
525
526 case nir_op_iabs:
527 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
528 break;
529 case nir_op_iadd:
530 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
531 break;
532 case nir_op_iand:
533 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
534 break;
535 case nir_op_imax:
536 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
537 break;
538 case nir_op_umax:
539 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
540 break;
541 case nir_op_imin:
542 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
543 break;
544 case nir_op_umin:
545 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
546 break;
547 case nir_op_umul_low:
548 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
549 break;
550 case nir_op_imadsh_mix16:
551 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
552 break;
553 case nir_op_ineg:
554 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
555 break;
556 case nir_op_inot:
557 dst[0] = ir3_NOT_B(b, src[0], 0);
558 break;
559 case nir_op_ior:
560 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
561 break;
562 case nir_op_ishl:
563 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
564 break;
565 case nir_op_ishr:
566 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
567 break;
568 case nir_op_isub:
569 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
570 break;
571 case nir_op_ixor:
572 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
573 break;
574 case nir_op_ushr:
575 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
576 break;
577 case nir_op_ilt32:
578 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
579 dst[0]->cat2.condition = IR3_COND_LT;
580 dst[0] = ir3_n2b(b, dst[0]);
581 break;
582 case nir_op_ige32:
583 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
584 dst[0]->cat2.condition = IR3_COND_GE;
585 dst[0] = ir3_n2b(b, dst[0]);
586 break;
587 case nir_op_ieq32:
588 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
589 dst[0]->cat2.condition = IR3_COND_EQ;
590 dst[0] = ir3_n2b(b, dst[0]);
591 break;
592 case nir_op_ine32:
593 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
594 dst[0]->cat2.condition = IR3_COND_NE;
595 dst[0] = ir3_n2b(b, dst[0]);
596 break;
597 case nir_op_ult32:
598 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
599 dst[0]->cat2.condition = IR3_COND_LT;
600 dst[0] = ir3_n2b(b, dst[0]);
601 break;
602 case nir_op_uge32:
603 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
604 dst[0]->cat2.condition = IR3_COND_GE;
605 dst[0] = ir3_n2b(b, dst[0]);
606 break;
607
608 case nir_op_b32csel: {
609 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
610 compile_assert(ctx, bs[1] == bs[2]);
611 /* the boolean condition is 32b even if src[1] and src[2] are
612 * half-precision, but sel.b16 wants all three src's to be the
613 * same type.
614 */
615 if (bs[1] < 32)
616 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
617 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
618 break;
619 }
620 case nir_op_bit_count: {
621 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
622 // double check on earlier gen's. Once half-precision support is
623 // in place, this should probably move to a NIR lowering pass:
624 struct ir3_instruction *hi, *lo;
625
626 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
627 TYPE_U32, TYPE_U16);
628 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
629
630 hi = ir3_CBITS_B(b, hi, 0);
631 lo = ir3_CBITS_B(b, lo, 0);
632
633 // TODO maybe the builders should default to making dst half-precision
634 // if the src's were half precision, to make this less awkward.. otoh
635 // we should probably just do this lowering in NIR.
636 hi->regs[0]->flags |= IR3_REG_HALF;
637 lo->regs[0]->flags |= IR3_REG_HALF;
638
639 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
640 dst[0]->regs[0]->flags |= IR3_REG_HALF;
641 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
642 break;
643 }
644 case nir_op_ifind_msb: {
645 struct ir3_instruction *cmp;
646 dst[0] = ir3_CLZ_S(b, src[0], 0);
647 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
648 cmp->cat2.condition = IR3_COND_GE;
649 dst[0] = ir3_SEL_B32(b,
650 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
651 cmp, 0, dst[0], 0);
652 break;
653 }
654 case nir_op_ufind_msb:
655 dst[0] = ir3_CLZ_B(b, src[0], 0);
656 dst[0] = ir3_SEL_B32(b,
657 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
658 src[0], 0, dst[0], 0);
659 break;
660 case nir_op_find_lsb:
661 dst[0] = ir3_BFREV_B(b, src[0], 0);
662 dst[0] = ir3_CLZ_B(b, dst[0], 0);
663 break;
664 case nir_op_bitfield_reverse:
665 dst[0] = ir3_BFREV_B(b, src[0], 0);
666 break;
667
668 default:
669 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
670 nir_op_infos[alu->op].name);
671 break;
672 }
673
674 ir3_put_dst(ctx, &alu->dest.dest);
675 }
676
677 /* handles direct/indirect UBO reads: */
678 static void
679 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
680 struct ir3_instruction **dst)
681 {
682 struct ir3_block *b = ctx->block;
683 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
684 /* UBO addresses are the first driver params, but subtract 2 here to
685 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
686 * is the uniforms: */
687 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
688 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
689 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
690
691 int off = 0;
692
693 /* First src is ubo index, which could either be an immed or not: */
694 src0 = ir3_get_src(ctx, &intr->src[0])[0];
695 if (is_same_type_mov(src0) &&
696 (src0->regs[1]->flags & IR3_REG_IMMED)) {
697 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
698 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
699 } else {
700 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
701 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
702
703 /* NOTE: since relative addressing is used, make sure constlen is
704 * at least big enough to cover all the UBO addresses, since the
705 * assembler won't know what the max address reg is.
706 */
707 ctx->so->constlen = MAX2(ctx->so->constlen,
708 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
709 }
710
711 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
712 addr = base_lo;
713
714 if (nir_src_is_const(intr->src[1])) {
715 off += nir_src_as_uint(intr->src[1]);
716 } else {
717 /* For load_ubo_indirect, second src is indirect offset: */
718 src1 = ir3_get_src(ctx, &intr->src[1])[0];
719
720 /* and add offset to addr: */
721 addr = ir3_ADD_S(b, addr, 0, src1, 0);
722 }
723
724 /* if offset is to large to encode in the ldg, split it out: */
725 if ((off + (intr->num_components * 4)) > 1024) {
726 /* split out the minimal amount to improve the odds that
727 * cp can fit the immediate in the add.s instruction:
728 */
729 unsigned off2 = off + (intr->num_components * 4) - 1024;
730 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
731 off -= off2;
732 }
733
734 if (ptrsz == 2) {
735 struct ir3_instruction *carry;
736
737 /* handle 32b rollover, ie:
738 * if (addr < base_lo)
739 * base_hi++
740 */
741 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
742 carry->cat2.condition = IR3_COND_LT;
743 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
744
745 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
746 }
747
748 for (int i = 0; i < intr->num_components; i++) {
749 struct ir3_instruction *load =
750 ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
751 load->cat6.type = TYPE_U32;
752 load->cat6.src_offset = off + i * 4; /* byte offset */
753 dst[i] = load;
754 }
755 }
756
757 /* src[] = { block_index } */
758 static void
759 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
760 struct ir3_instruction **dst)
761 {
762 /* SSBO size stored as a const starting at ssbo_sizes: */
763 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
764 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
765 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
766 const_state->ssbo_size.off[blk_idx];
767
768 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
769
770 dst[0] = create_uniform(ctx->block, idx);
771 }
772
773 /* src[] = { offset }. const_index[] = { base } */
774 static void
775 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
776 struct ir3_instruction **dst)
777 {
778 struct ir3_block *b = ctx->block;
779 struct ir3_instruction *ldl, *offset;
780 unsigned base;
781
782 offset = ir3_get_src(ctx, &intr->src[0])[0];
783 base = nir_intrinsic_base(intr);
784
785 ldl = ir3_LDL(b, offset, 0, create_immed(b, intr->num_components), 0);
786 ldl->cat6.src_offset = base;
787 ldl->cat6.type = utype_dst(intr->dest);
788 ldl->regs[0]->wrmask = MASK(intr->num_components);
789
790 ldl->barrier_class = IR3_BARRIER_SHARED_R;
791 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
792
793 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
794 }
795
796 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
797 static void
798 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
799 {
800 struct ir3_block *b = ctx->block;
801 struct ir3_instruction *stl, *offset;
802 struct ir3_instruction * const *value;
803 unsigned base, wrmask;
804
805 value = ir3_get_src(ctx, &intr->src[0]);
806 offset = ir3_get_src(ctx, &intr->src[1])[0];
807
808 base = nir_intrinsic_base(intr);
809 wrmask = nir_intrinsic_write_mask(intr);
810
811 /* Combine groups of consecutive enabled channels in one write
812 * message. We use ffs to find the first enabled channel and then ffs on
813 * the bit-inverse, down-shifted writemask to determine the length of
814 * the block of enabled bits.
815 *
816 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
817 */
818 while (wrmask) {
819 unsigned first_component = ffs(wrmask) - 1;
820 unsigned length = ffs(~(wrmask >> first_component)) - 1;
821
822 stl = ir3_STL(b, offset, 0,
823 ir3_create_collect(ctx, &value[first_component], length), 0,
824 create_immed(b, length), 0);
825 stl->cat6.dst_offset = first_component + base;
826 stl->cat6.type = utype_src(intr->src[0]);
827 stl->barrier_class = IR3_BARRIER_SHARED_W;
828 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
829
830 array_insert(b, b->keeps, stl);
831
832 /* Clear the bits in the writemask that we just wrote, then try
833 * again to see if more channels are left.
834 */
835 wrmask &= (15 << (first_component + length));
836 }
837 }
838
839 /*
840 * CS shared variable atomic intrinsics
841 *
842 * All of the shared variable atomic memory operations read a value from
843 * memory, compute a new value using one of the operations below, write the
844 * new value to memory, and return the original value read.
845 *
846 * All operations take 2 sources except CompSwap that takes 3. These
847 * sources represent:
848 *
849 * 0: The offset into the shared variable storage region that the atomic
850 * operation will operate on.
851 * 1: The data parameter to the atomic function (i.e. the value to add
852 * in shared_atomic_add, etc).
853 * 2: For CompSwap only: the second data parameter.
854 */
855 static struct ir3_instruction *
856 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
857 {
858 struct ir3_block *b = ctx->block;
859 struct ir3_instruction *atomic, *src0, *src1;
860 type_t type = TYPE_U32;
861
862 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
863 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
864
865 switch (intr->intrinsic) {
866 case nir_intrinsic_shared_atomic_add:
867 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
868 break;
869 case nir_intrinsic_shared_atomic_imin:
870 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
871 type = TYPE_S32;
872 break;
873 case nir_intrinsic_shared_atomic_umin:
874 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
875 break;
876 case nir_intrinsic_shared_atomic_imax:
877 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
878 type = TYPE_S32;
879 break;
880 case nir_intrinsic_shared_atomic_umax:
881 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
882 break;
883 case nir_intrinsic_shared_atomic_and:
884 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
885 break;
886 case nir_intrinsic_shared_atomic_or:
887 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
888 break;
889 case nir_intrinsic_shared_atomic_xor:
890 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
891 break;
892 case nir_intrinsic_shared_atomic_exchange:
893 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
894 break;
895 case nir_intrinsic_shared_atomic_comp_swap:
896 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
897 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
898 ir3_get_src(ctx, &intr->src[2])[0],
899 src1,
900 }, 2);
901 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
902 break;
903 default:
904 unreachable("boo");
905 }
906
907 atomic->cat6.iim_val = 1;
908 atomic->cat6.d = 1;
909 atomic->cat6.type = type;
910 atomic->barrier_class = IR3_BARRIER_SHARED_W;
911 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
912
913 /* even if nothing consume the result, we can't DCE the instruction: */
914 array_insert(b, b->keeps, atomic);
915
916 return atomic;
917 }
918
919 /* TODO handle actual indirect/dynamic case.. which is going to be weird
920 * to handle with the image_mapping table..
921 */
922 static struct ir3_instruction *
923 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
924 {
925 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
926 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
927 struct ir3_instruction *texture, *sampler;
928
929 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
930 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
931
932 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
933 sampler,
934 texture,
935 }, 2);
936 }
937
938 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
939 static void
940 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
941 struct ir3_instruction **dst)
942 {
943 struct ir3_block *b = ctx->block;
944 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
945 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
946 struct ir3_instruction *sam;
947 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
948 struct ir3_instruction *coords[4];
949 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
950 type_t type = ir3_get_image_type(var);
951
952 /* hmm, this seems a bit odd, but it is what blob does and (at least
953 * a5xx) just faults on bogus addresses otherwise:
954 */
955 if (flags & IR3_INSTR_3D) {
956 flags &= ~IR3_INSTR_3D;
957 flags |= IR3_INSTR_A;
958 }
959
960 for (unsigned i = 0; i < ncoords; i++)
961 coords[i] = src0[i];
962
963 if (ncoords == 1)
964 coords[ncoords++] = create_immed(b, 0);
965
966 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
967 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
968
969 sam->barrier_class = IR3_BARRIER_IMAGE_R;
970 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
971
972 ir3_split_dest(b, dst, sam, 0, 4);
973 }
974
975 static void
976 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
977 struct ir3_instruction **dst)
978 {
979 struct ir3_block *b = ctx->block;
980 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
981 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
982 struct ir3_instruction *sam, *lod;
983 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
984
985 lod = create_immed(b, 0);
986 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
987 samp_tex, lod, NULL);
988
989 /* Array size actually ends up in .w rather than .z. This doesn't
990 * matter for miplevel 0, but for higher mips the value in z is
991 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
992 * returned, which means that we have to add 1 to it for arrays for
993 * a3xx.
994 *
995 * Note use a temporary dst and then copy, since the size of the dst
996 * array that is passed in is based on nir's understanding of the
997 * result size, not the hardware's
998 */
999 struct ir3_instruction *tmp[4];
1000
1001 ir3_split_dest(b, tmp, sam, 0, 4);
1002
1003 /* get_size instruction returns size in bytes instead of texels
1004 * for imageBuffer, so we need to divide it by the pixel size
1005 * of the image format.
1006 *
1007 * TODO: This is at least true on a5xx. Check other gens.
1008 */
1009 enum glsl_sampler_dim dim =
1010 glsl_get_sampler_dim(glsl_without_array(var->type));
1011 if (dim == GLSL_SAMPLER_DIM_BUF) {
1012 /* Since all the possible values the divisor can take are
1013 * power-of-two (4, 8, or 16), the division is implemented
1014 * as a shift-right.
1015 * During shader setup, the log2 of the image format's
1016 * bytes-per-pixel should have been emitted in 2nd slot of
1017 * image_dims. See ir3_shader::emit_image_dims().
1018 */
1019 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1020 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1021 const_state->image_dims.off[var->data.driver_location];
1022 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1023
1024 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1025 }
1026
1027 for (unsigned i = 0; i < ncoords; i++)
1028 dst[i] = tmp[i];
1029
1030 if (flags & IR3_INSTR_A) {
1031 if (ctx->compiler->levels_add_one) {
1032 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1033 } else {
1034 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1035 }
1036 }
1037 }
1038
1039 static void
1040 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1041 {
1042 struct ir3_block *b = ctx->block;
1043 struct ir3_instruction *barrier;
1044
1045 switch (intr->intrinsic) {
1046 case nir_intrinsic_barrier:
1047 barrier = ir3_BAR(b);
1048 barrier->cat7.g = true;
1049 barrier->cat7.l = true;
1050 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1051 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1052 break;
1053 case nir_intrinsic_memory_barrier:
1054 barrier = ir3_FENCE(b);
1055 barrier->cat7.g = true;
1056 barrier->cat7.r = true;
1057 barrier->cat7.w = true;
1058 barrier->cat7.l = true;
1059 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1060 IR3_BARRIER_BUFFER_W;
1061 barrier->barrier_conflict =
1062 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1063 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1064 break;
1065 case nir_intrinsic_memory_barrier_atomic_counter:
1066 case nir_intrinsic_memory_barrier_buffer:
1067 barrier = ir3_FENCE(b);
1068 barrier->cat7.g = true;
1069 barrier->cat7.r = true;
1070 barrier->cat7.w = true;
1071 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1072 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1073 IR3_BARRIER_BUFFER_W;
1074 break;
1075 case nir_intrinsic_memory_barrier_image:
1076 // TODO double check if this should have .g set
1077 barrier = ir3_FENCE(b);
1078 barrier->cat7.g = true;
1079 barrier->cat7.r = true;
1080 barrier->cat7.w = true;
1081 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1082 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1083 IR3_BARRIER_IMAGE_W;
1084 break;
1085 case nir_intrinsic_memory_barrier_shared:
1086 barrier = ir3_FENCE(b);
1087 barrier->cat7.g = true;
1088 barrier->cat7.l = true;
1089 barrier->cat7.r = true;
1090 barrier->cat7.w = true;
1091 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1092 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1093 IR3_BARRIER_SHARED_W;
1094 break;
1095 case nir_intrinsic_group_memory_barrier:
1096 barrier = ir3_FENCE(b);
1097 barrier->cat7.g = true;
1098 barrier->cat7.l = true;
1099 barrier->cat7.r = true;
1100 barrier->cat7.w = true;
1101 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1102 IR3_BARRIER_IMAGE_W |
1103 IR3_BARRIER_BUFFER_W;
1104 barrier->barrier_conflict =
1105 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1106 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1107 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1108 break;
1109 default:
1110 unreachable("boo");
1111 }
1112
1113 /* make sure barrier doesn't get DCE'd */
1114 array_insert(b, b->keeps, barrier);
1115 }
1116
1117 static void add_sysval_input_compmask(struct ir3_context *ctx,
1118 gl_system_value slot, unsigned compmask,
1119 struct ir3_instruction *instr)
1120 {
1121 struct ir3_shader_variant *so = ctx->so;
1122 unsigned r = regid(so->inputs_count, 0);
1123 unsigned n = so->inputs_count++;
1124
1125 so->inputs[n].sysval = true;
1126 so->inputs[n].slot = slot;
1127 so->inputs[n].compmask = compmask;
1128 so->inputs[n].regid = r;
1129 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1130 so->total_in++;
1131
1132 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1133 ctx->ir->inputs[r] = instr;
1134 }
1135
1136 static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1137 struct ir3_instruction *instr)
1138 {
1139 add_sysval_input_compmask(ctx, slot, 0x1, instr);
1140 }
1141
1142 static struct ir3_instruction *
1143 get_barycentric_centroid(struct ir3_context *ctx)
1144 {
1145 if (!ctx->ij_centroid) {
1146 struct ir3_instruction *xy[2];
1147 struct ir3_instruction *ij;
1148
1149 ij = create_input_compmask(ctx, 0, 0x3);
1150 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1151
1152 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1153
1154 add_sysval_input_compmask(ctx,
1155 SYSTEM_VALUE_BARYCENTRIC_CENTROID,
1156 0x3, ij);
1157 }
1158
1159 return ctx->ij_centroid;
1160 }
1161
1162 static struct ir3_instruction *
1163 get_barycentric_sample(struct ir3_context *ctx)
1164 {
1165 if (!ctx->ij_sample) {
1166 struct ir3_instruction *xy[2];
1167 struct ir3_instruction *ij;
1168
1169 ij = create_input_compmask(ctx, 0, 0x3);
1170 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1171
1172 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1173
1174 add_sysval_input_compmask(ctx,
1175 SYSTEM_VALUE_BARYCENTRIC_SAMPLE,
1176 0x3, ij);
1177 }
1178
1179 return ctx->ij_sample;
1180 }
1181
1182 static struct ir3_instruction *
1183 get_barycentric_pixel(struct ir3_context *ctx)
1184 {
1185 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1186 * this to create ij_pixel only on demand:
1187 */
1188 return ctx->ij_pixel;
1189 }
1190
1191 static struct ir3_instruction *
1192 get_frag_coord(struct ir3_context *ctx)
1193 {
1194 if (!ctx->frag_coord) {
1195 struct ir3_block *b = ctx->block;
1196 struct ir3_instruction *xyzw[4];
1197 struct ir3_instruction *hw_frag_coord;
1198
1199 hw_frag_coord = create_input_compmask(ctx, 0, 0xf);
1200 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1201
1202 /* for frag_coord.xy, we get unsigned values.. we need
1203 * to subtract (integer) 8 and divide by 16 (right-
1204 * shift by 4) then convert to float:
1205 *
1206 * sub.s tmp, src, 8
1207 * shr.b tmp, tmp, 4
1208 * mov.u32f32 dst, tmp
1209 *
1210 */
1211 for (int i = 0; i < 2; i++) {
1212 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1213 create_immed(b, 8), 0);
1214 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1215 create_immed(b, 4), 0);
1216 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1217 }
1218
1219 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1220
1221 add_sysval_input_compmask(ctx,
1222 SYSTEM_VALUE_FRAG_COORD,
1223 0xf, hw_frag_coord);
1224
1225 ctx->so->frag_coord = true;
1226 }
1227
1228 return ctx->frag_coord;
1229 }
1230
1231 static void
1232 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1233 {
1234 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1235 struct ir3_instruction **dst;
1236 struct ir3_instruction * const *src;
1237 struct ir3_block *b = ctx->block;
1238 int idx, comp;
1239
1240 if (info->has_dest) {
1241 unsigned n = nir_intrinsic_dest_components(intr);
1242 dst = ir3_get_dst(ctx, &intr->dest, n);
1243 } else {
1244 dst = NULL;
1245 }
1246
1247 switch (intr->intrinsic) {
1248 case nir_intrinsic_load_uniform:
1249 idx = nir_intrinsic_base(intr);
1250 if (nir_src_is_const(intr->src[0])) {
1251 idx += nir_src_as_uint(intr->src[0]);
1252 for (int i = 0; i < intr->num_components; i++) {
1253 dst[i] = create_uniform_typed(b, idx + i,
1254 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1255 }
1256 } else {
1257 src = ir3_get_src(ctx, &intr->src[0]);
1258 for (int i = 0; i < intr->num_components; i++) {
1259 dst[i] = create_uniform_indirect(b, idx + i,
1260 ir3_get_addr(ctx, src[0], 1));
1261 }
1262 /* NOTE: if relative addressing is used, we set
1263 * constlen in the compiler (to worst-case value)
1264 * since we don't know in the assembler what the max
1265 * addr reg value can be:
1266 */
1267 ctx->so->constlen = MAX2(ctx->so->constlen,
1268 ctx->so->shader->ubo_state.size / 16);
1269 }
1270 break;
1271 case nir_intrinsic_load_ubo:
1272 emit_intrinsic_load_ubo(ctx, intr, dst);
1273 break;
1274 case nir_intrinsic_load_frag_coord:
1275 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1276 break;
1277 case nir_intrinsic_load_sample_pos_from_id: {
1278 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1279 * but that doesn't seem necessary.
1280 */
1281 struct ir3_instruction *offset =
1282 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1283 offset->regs[0]->wrmask = 0x3;
1284 offset->cat5.type = TYPE_F32;
1285
1286 ir3_split_dest(b, dst, offset, 0, 2);
1287
1288 break;
1289 }
1290 case nir_intrinsic_load_size_ir3:
1291 if (!ctx->ij_size) {
1292 ctx->ij_size = create_input(ctx, 0);
1293
1294 add_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SIZE,
1295 ctx->ij_size);
1296 }
1297 dst[0] = ctx->ij_size;
1298 break;
1299 case nir_intrinsic_load_barycentric_centroid:
1300 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1301 break;
1302 case nir_intrinsic_load_barycentric_sample:
1303 if (ctx->so->key.msaa) {
1304 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1305 } else {
1306 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1307 }
1308 break;
1309 case nir_intrinsic_load_barycentric_pixel:
1310 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1311 break;
1312 case nir_intrinsic_load_interpolated_input:
1313 idx = nir_intrinsic_base(intr);
1314 comp = nir_intrinsic_component(intr);
1315 src = ir3_get_src(ctx, &intr->src[0]);
1316 if (nir_src_is_const(intr->src[1])) {
1317 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1318 idx += nir_src_as_uint(intr->src[1]);
1319 for (int i = 0; i < intr->num_components; i++) {
1320 unsigned inloc = idx * 4 + i + comp;
1321 if (ctx->so->inputs[idx].bary &&
1322 !ctx->so->inputs[idx].use_ldlv) {
1323 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1324 } else {
1325 /* for non-varyings use the pre-setup input, since
1326 * that is easier than mapping things back to a
1327 * nir_variable to figure out what it is.
1328 */
1329 dst[i] = ctx->ir->inputs[inloc];
1330 }
1331 }
1332 } else {
1333 ir3_context_error(ctx, "unhandled");
1334 }
1335 break;
1336 case nir_intrinsic_load_input:
1337 idx = nir_intrinsic_base(intr);
1338 comp = nir_intrinsic_component(intr);
1339 if (nir_src_is_const(intr->src[0])) {
1340 idx += nir_src_as_uint(intr->src[0]);
1341 for (int i = 0; i < intr->num_components; i++) {
1342 unsigned n = idx * 4 + i + comp;
1343 dst[i] = ctx->ir->inputs[n];
1344 compile_assert(ctx, ctx->ir->inputs[n]);
1345 }
1346 } else {
1347 src = ir3_get_src(ctx, &intr->src[0]);
1348 struct ir3_instruction *collect =
1349 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1350 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1351 for (int i = 0; i < intr->num_components; i++) {
1352 unsigned n = idx * 4 + i + comp;
1353 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1354 n, addr, collect);
1355 }
1356 }
1357 break;
1358 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1359 * pass and replaced by an ir3-specifc version that adds the
1360 * dword-offset in the last source.
1361 */
1362 case nir_intrinsic_load_ssbo_ir3:
1363 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1364 break;
1365 case nir_intrinsic_store_ssbo_ir3:
1366 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1367 !ctx->s->info.fs.early_fragment_tests)
1368 ctx->so->no_earlyz = true;
1369 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1370 break;
1371 case nir_intrinsic_get_buffer_size:
1372 emit_intrinsic_ssbo_size(ctx, intr, dst);
1373 break;
1374 case nir_intrinsic_ssbo_atomic_add_ir3:
1375 case nir_intrinsic_ssbo_atomic_imin_ir3:
1376 case nir_intrinsic_ssbo_atomic_umin_ir3:
1377 case nir_intrinsic_ssbo_atomic_imax_ir3:
1378 case nir_intrinsic_ssbo_atomic_umax_ir3:
1379 case nir_intrinsic_ssbo_atomic_and_ir3:
1380 case nir_intrinsic_ssbo_atomic_or_ir3:
1381 case nir_intrinsic_ssbo_atomic_xor_ir3:
1382 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1383 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1384 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1385 !ctx->s->info.fs.early_fragment_tests)
1386 ctx->so->no_earlyz = true;
1387 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1388 break;
1389 case nir_intrinsic_load_shared:
1390 emit_intrinsic_load_shared(ctx, intr, dst);
1391 break;
1392 case nir_intrinsic_store_shared:
1393 emit_intrinsic_store_shared(ctx, intr);
1394 break;
1395 case nir_intrinsic_shared_atomic_add:
1396 case nir_intrinsic_shared_atomic_imin:
1397 case nir_intrinsic_shared_atomic_umin:
1398 case nir_intrinsic_shared_atomic_imax:
1399 case nir_intrinsic_shared_atomic_umax:
1400 case nir_intrinsic_shared_atomic_and:
1401 case nir_intrinsic_shared_atomic_or:
1402 case nir_intrinsic_shared_atomic_xor:
1403 case nir_intrinsic_shared_atomic_exchange:
1404 case nir_intrinsic_shared_atomic_comp_swap:
1405 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1406 break;
1407 case nir_intrinsic_image_deref_load:
1408 emit_intrinsic_load_image(ctx, intr, dst);
1409 break;
1410 case nir_intrinsic_image_deref_store:
1411 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1412 !ctx->s->info.fs.early_fragment_tests)
1413 ctx->so->no_earlyz = true;
1414 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1415 break;
1416 case nir_intrinsic_image_deref_size:
1417 emit_intrinsic_image_size(ctx, intr, dst);
1418 break;
1419 case nir_intrinsic_image_deref_atomic_add:
1420 case nir_intrinsic_image_deref_atomic_imin:
1421 case nir_intrinsic_image_deref_atomic_umin:
1422 case nir_intrinsic_image_deref_atomic_imax:
1423 case nir_intrinsic_image_deref_atomic_umax:
1424 case nir_intrinsic_image_deref_atomic_and:
1425 case nir_intrinsic_image_deref_atomic_or:
1426 case nir_intrinsic_image_deref_atomic_xor:
1427 case nir_intrinsic_image_deref_atomic_exchange:
1428 case nir_intrinsic_image_deref_atomic_comp_swap:
1429 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1430 !ctx->s->info.fs.early_fragment_tests)
1431 ctx->so->no_earlyz = true;
1432 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1433 break;
1434 case nir_intrinsic_barrier:
1435 case nir_intrinsic_memory_barrier:
1436 case nir_intrinsic_group_memory_barrier:
1437 case nir_intrinsic_memory_barrier_atomic_counter:
1438 case nir_intrinsic_memory_barrier_buffer:
1439 case nir_intrinsic_memory_barrier_image:
1440 case nir_intrinsic_memory_barrier_shared:
1441 emit_intrinsic_barrier(ctx, intr);
1442 /* note that blk ptr no longer valid, make that obvious: */
1443 b = NULL;
1444 break;
1445 case nir_intrinsic_store_output:
1446 idx = nir_intrinsic_base(intr);
1447 comp = nir_intrinsic_component(intr);
1448 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1449 idx += nir_src_as_uint(intr->src[1]);
1450
1451 src = ir3_get_src(ctx, &intr->src[0]);
1452 for (int i = 0; i < intr->num_components; i++) {
1453 unsigned n = idx * 4 + i + comp;
1454 ctx->ir->outputs[n] = src[i];
1455 }
1456 break;
1457 case nir_intrinsic_load_base_vertex:
1458 case nir_intrinsic_load_first_vertex:
1459 if (!ctx->basevertex) {
1460 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1461 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex);
1462 }
1463 dst[0] = ctx->basevertex;
1464 break;
1465 case nir_intrinsic_load_vertex_id_zero_base:
1466 case nir_intrinsic_load_vertex_id:
1467 if (!ctx->vertex_id) {
1468 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1469 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1470 ctx->vertex_id = create_input(ctx, 0);
1471 add_sysval_input(ctx, sv, ctx->vertex_id);
1472 }
1473 dst[0] = ctx->vertex_id;
1474 break;
1475 case nir_intrinsic_load_instance_id:
1476 if (!ctx->instance_id) {
1477 ctx->instance_id = create_input(ctx, 0);
1478 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID,
1479 ctx->instance_id);
1480 }
1481 dst[0] = ctx->instance_id;
1482 break;
1483 case nir_intrinsic_load_sample_id:
1484 ctx->so->per_samp = true;
1485 /* fall-thru */
1486 case nir_intrinsic_load_sample_id_no_per_sample:
1487 if (!ctx->samp_id) {
1488 ctx->samp_id = create_input(ctx, 0);
1489 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1490 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID,
1491 ctx->samp_id);
1492 }
1493 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1494 break;
1495 case nir_intrinsic_load_sample_mask_in:
1496 if (!ctx->samp_mask_in) {
1497 ctx->samp_mask_in = create_input(ctx, 0);
1498 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN,
1499 ctx->samp_mask_in);
1500 }
1501 dst[0] = ctx->samp_mask_in;
1502 break;
1503 case nir_intrinsic_load_user_clip_plane:
1504 idx = nir_intrinsic_ucp_id(intr);
1505 for (int i = 0; i < intr->num_components; i++) {
1506 unsigned n = idx * 4 + i;
1507 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1508 }
1509 break;
1510 case nir_intrinsic_load_front_face:
1511 if (!ctx->frag_face) {
1512 ctx->so->frag_face = true;
1513 ctx->frag_face = create_input(ctx, 0);
1514 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face);
1515 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1516 }
1517 /* for fragface, we get -1 for back and 0 for front. However this is
1518 * the inverse of what nir expects (where ~0 is true).
1519 */
1520 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1521 dst[0] = ir3_NOT_B(b, dst[0], 0);
1522 break;
1523 case nir_intrinsic_load_local_invocation_id:
1524 if (!ctx->local_invocation_id) {
1525 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7);
1526 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID,
1527 0x7, ctx->local_invocation_id);
1528 }
1529 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1530 break;
1531 case nir_intrinsic_load_work_group_id:
1532 if (!ctx->work_group_id) {
1533 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7);
1534 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID,
1535 0x7, ctx->work_group_id);
1536 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1537 }
1538 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1539 break;
1540 case nir_intrinsic_load_num_work_groups:
1541 for (int i = 0; i < intr->num_components; i++) {
1542 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1543 }
1544 break;
1545 case nir_intrinsic_load_local_group_size:
1546 for (int i = 0; i < intr->num_components; i++) {
1547 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1548 }
1549 break;
1550 case nir_intrinsic_discard_if:
1551 case nir_intrinsic_discard: {
1552 struct ir3_instruction *cond, *kill;
1553
1554 if (intr->intrinsic == nir_intrinsic_discard_if) {
1555 /* conditional discard: */
1556 src = ir3_get_src(ctx, &intr->src[0]);
1557 cond = ir3_b2n(b, src[0]);
1558 } else {
1559 /* unconditional discard: */
1560 cond = create_immed(b, 1);
1561 }
1562
1563 /* NOTE: only cmps.*.* can write p0.x: */
1564 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1565 cond->cat2.condition = IR3_COND_NE;
1566
1567 /* condition always goes in predicate register: */
1568 cond->regs[0]->num = regid(REG_P0, 0);
1569
1570 kill = ir3_KILL(b, cond, 0);
1571 array_insert(ctx->ir, ctx->ir->predicates, kill);
1572
1573 array_insert(b, b->keeps, kill);
1574 ctx->so->no_earlyz = true;
1575
1576 break;
1577 }
1578 default:
1579 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1580 nir_intrinsic_infos[intr->intrinsic].name);
1581 break;
1582 }
1583
1584 if (info->has_dest)
1585 ir3_put_dst(ctx, &intr->dest);
1586 }
1587
1588 static void
1589 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1590 {
1591 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1592 instr->def.num_components);
1593
1594 if (instr->def.bit_size < 32) {
1595 for (int i = 0; i < instr->def.num_components; i++)
1596 dst[i] = create_immed_typed(ctx->block,
1597 instr->value[i].u16,
1598 TYPE_U16);
1599 } else {
1600 for (int i = 0; i < instr->def.num_components; i++)
1601 dst[i] = create_immed_typed(ctx->block,
1602 instr->value[i].u32,
1603 TYPE_U32);
1604 }
1605
1606 }
1607
1608 static void
1609 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1610 {
1611 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1612 undef->def.num_components);
1613 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1614
1615 /* backend doesn't want undefined instructions, so just plug
1616 * in 0.0..
1617 */
1618 for (int i = 0; i < undef->def.num_components; i++)
1619 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1620 }
1621
1622 /*
1623 * texture fetch/sample instructions:
1624 */
1625
1626 static void
1627 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1628 {
1629 unsigned coords, flags = 0;
1630
1631 /* note: would use tex->coord_components.. except txs.. also,
1632 * since array index goes after shadow ref, we don't want to
1633 * count it:
1634 */
1635 switch (tex->sampler_dim) {
1636 case GLSL_SAMPLER_DIM_1D:
1637 case GLSL_SAMPLER_DIM_BUF:
1638 coords = 1;
1639 break;
1640 case GLSL_SAMPLER_DIM_2D:
1641 case GLSL_SAMPLER_DIM_RECT:
1642 case GLSL_SAMPLER_DIM_EXTERNAL:
1643 case GLSL_SAMPLER_DIM_MS:
1644 coords = 2;
1645 break;
1646 case GLSL_SAMPLER_DIM_3D:
1647 case GLSL_SAMPLER_DIM_CUBE:
1648 coords = 3;
1649 flags |= IR3_INSTR_3D;
1650 break;
1651 default:
1652 unreachable("bad sampler_dim");
1653 }
1654
1655 if (tex->is_shadow && tex->op != nir_texop_lod)
1656 flags |= IR3_INSTR_S;
1657
1658 if (tex->is_array && tex->op != nir_texop_lod)
1659 flags |= IR3_INSTR_A;
1660
1661 *flagsp = flags;
1662 *coordsp = coords;
1663 }
1664
1665 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1666 * or immediate (in which case it will get lowered later to a non .s2en
1667 * version of the tex instruction which encode tex/samp as immediates:
1668 */
1669 static struct ir3_instruction *
1670 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1671 {
1672 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1673 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1674 struct ir3_instruction *texture, *sampler;
1675
1676 if (texture_idx >= 0) {
1677 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1678 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1679 } else {
1680 /* TODO what to do for dynamic case? I guess we only need the
1681 * max index for astc srgb workaround so maybe not a problem
1682 * to worry about if we don't enable indirect samplers for
1683 * a4xx?
1684 */
1685 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1686 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1687 }
1688
1689 if (sampler_idx >= 0) {
1690 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1691 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1692 } else {
1693 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1694 }
1695
1696 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1697 sampler,
1698 texture,
1699 }, 2);
1700 }
1701
1702 static void
1703 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1704 {
1705 struct ir3_block *b = ctx->block;
1706 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1707 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1708 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1709 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1710 unsigned i, coords, flags, ncomp;
1711 unsigned nsrc0 = 0, nsrc1 = 0;
1712 type_t type;
1713 opc_t opc = 0;
1714
1715 ncomp = nir_dest_num_components(tex->dest);
1716
1717 coord = off = ddx = ddy = NULL;
1718 lod = proj = compare = sample_index = NULL;
1719
1720 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1721
1722 for (unsigned i = 0; i < tex->num_srcs; i++) {
1723 switch (tex->src[i].src_type) {
1724 case nir_tex_src_coord:
1725 coord = ir3_get_src(ctx, &tex->src[i].src);
1726 break;
1727 case nir_tex_src_bias:
1728 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1729 has_bias = true;
1730 break;
1731 case nir_tex_src_lod:
1732 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1733 has_lod = true;
1734 break;
1735 case nir_tex_src_comparator: /* shadow comparator */
1736 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1737 break;
1738 case nir_tex_src_projector:
1739 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1740 has_proj = true;
1741 break;
1742 case nir_tex_src_offset:
1743 off = ir3_get_src(ctx, &tex->src[i].src);
1744 has_off = true;
1745 break;
1746 case nir_tex_src_ddx:
1747 ddx = ir3_get_src(ctx, &tex->src[i].src);
1748 break;
1749 case nir_tex_src_ddy:
1750 ddy = ir3_get_src(ctx, &tex->src[i].src);
1751 break;
1752 case nir_tex_src_ms_index:
1753 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1754 break;
1755 case nir_tex_src_texture_offset:
1756 case nir_tex_src_sampler_offset:
1757 /* handled in get_tex_samp_src() */
1758 break;
1759 default:
1760 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1761 tex->src[i].src_type);
1762 return;
1763 }
1764 }
1765
1766 switch (tex->op) {
1767 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1768 case nir_texop_txb: opc = OPC_SAMB; break;
1769 case nir_texop_txl: opc = OPC_SAML; break;
1770 case nir_texop_txd: opc = OPC_SAMGQ; break;
1771 case nir_texop_txf: opc = OPC_ISAML; break;
1772 case nir_texop_lod: opc = OPC_GETLOD; break;
1773 case nir_texop_tg4:
1774 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1775 * what blob does, seems gather is broken?), and a3xx did
1776 * not support it (but probably could also emulate).
1777 */
1778 switch (tex->component) {
1779 case 0: opc = OPC_GATHER4R; break;
1780 case 1: opc = OPC_GATHER4G; break;
1781 case 2: opc = OPC_GATHER4B; break;
1782 case 3: opc = OPC_GATHER4A; break;
1783 }
1784 break;
1785 case nir_texop_txf_ms_fb:
1786 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
1787 default:
1788 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1789 return;
1790 }
1791
1792 tex_info(tex, &flags, &coords);
1793
1794 /*
1795 * lay out the first argument in the proper order:
1796 * - actual coordinates first
1797 * - shadow reference
1798 * - array index
1799 * - projection w
1800 * - starting at offset 4, dpdx.xy, dpdy.xy
1801 *
1802 * bias/lod go into the second arg
1803 */
1804
1805 /* insert tex coords: */
1806 for (i = 0; i < coords; i++)
1807 src0[i] = coord[i];
1808
1809 nsrc0 = i;
1810
1811 /* scale up integer coords for TXF based on the LOD */
1812 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
1813 assert(has_lod);
1814 for (i = 0; i < coords; i++)
1815 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
1816 }
1817
1818 if (coords == 1) {
1819 /* hw doesn't do 1d, so we treat it as 2d with
1820 * height of 1, and patch up the y coord.
1821 */
1822 if (is_isam(opc)) {
1823 src0[nsrc0++] = create_immed(b, 0);
1824 } else {
1825 src0[nsrc0++] = create_immed(b, fui(0.5));
1826 }
1827 }
1828
1829 if (tex->is_shadow && tex->op != nir_texop_lod)
1830 src0[nsrc0++] = compare;
1831
1832 if (tex->is_array && tex->op != nir_texop_lod) {
1833 struct ir3_instruction *idx = coord[coords];
1834
1835 /* the array coord for cube arrays needs 0.5 added to it */
1836 if (ctx->compiler->array_index_add_half && !is_isam(opc))
1837 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
1838
1839 src0[nsrc0++] = idx;
1840 }
1841
1842 if (has_proj) {
1843 src0[nsrc0++] = proj;
1844 flags |= IR3_INSTR_P;
1845 }
1846
1847 /* pad to 4, then ddx/ddy: */
1848 if (tex->op == nir_texop_txd) {
1849 while (nsrc0 < 4)
1850 src0[nsrc0++] = create_immed(b, fui(0.0));
1851 for (i = 0; i < coords; i++)
1852 src0[nsrc0++] = ddx[i];
1853 if (coords < 2)
1854 src0[nsrc0++] = create_immed(b, fui(0.0));
1855 for (i = 0; i < coords; i++)
1856 src0[nsrc0++] = ddy[i];
1857 if (coords < 2)
1858 src0[nsrc0++] = create_immed(b, fui(0.0));
1859 }
1860
1861 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1862 * with scaled x coord according to requested sample:
1863 */
1864 if (opc == OPC_ISAMM) {
1865 if (ctx->compiler->txf_ms_with_isaml) {
1866 /* the samples are laid out in x dimension as
1867 * 0 1 2 3
1868 * x_ms = (x << ms) + sample_index;
1869 */
1870 struct ir3_instruction *ms;
1871 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
1872
1873 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
1874 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
1875
1876 opc = OPC_ISAML;
1877 } else {
1878 src0[nsrc0++] = sample_index;
1879 }
1880 }
1881
1882 /*
1883 * second argument (if applicable):
1884 * - offsets
1885 * - lod
1886 * - bias
1887 */
1888 if (has_off | has_lod | has_bias) {
1889 if (has_off) {
1890 unsigned off_coords = coords;
1891 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
1892 off_coords--;
1893 for (i = 0; i < off_coords; i++)
1894 src1[nsrc1++] = off[i];
1895 if (off_coords < 2)
1896 src1[nsrc1++] = create_immed(b, fui(0.0));
1897 flags |= IR3_INSTR_O;
1898 }
1899
1900 if (has_lod | has_bias)
1901 src1[nsrc1++] = lod;
1902 }
1903
1904 switch (tex->dest_type) {
1905 case nir_type_invalid:
1906 case nir_type_float:
1907 type = TYPE_F32;
1908 break;
1909 case nir_type_int:
1910 type = TYPE_S32;
1911 break;
1912 case nir_type_uint:
1913 case nir_type_bool:
1914 type = TYPE_U32;
1915 break;
1916 default:
1917 unreachable("bad dest_type");
1918 }
1919
1920 if (opc == OPC_GETLOD)
1921 type = TYPE_U32;
1922
1923 struct ir3_instruction *samp_tex;
1924
1925 if (tex->op == nir_texop_txf_ms_fb) {
1926 /* only expect a single txf_ms_fb per shader: */
1927 compile_assert(ctx, !ctx->so->fb_read);
1928 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
1929
1930 ctx->so->fb_read = true;
1931 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1932 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
1933 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
1934 }, 2);
1935
1936 ctx->so->num_samp++;
1937 } else {
1938 samp_tex = get_tex_samp_tex_src(ctx, tex);
1939 }
1940
1941 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
1942 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
1943
1944 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
1945 samp_tex, col0, col1);
1946
1947 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
1948 /* only need first 3 components: */
1949 sam->regs[0]->wrmask = 0x7;
1950 ir3_split_dest(b, dst, sam, 0, 3);
1951
1952 /* we need to sample the alpha separately with a non-ASTC
1953 * texture state:
1954 */
1955 sam = ir3_SAM(b, opc, type, 0b1000, flags,
1956 samp_tex, col0, col1);
1957
1958 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
1959
1960 /* fixup .w component: */
1961 ir3_split_dest(b, &dst[3], sam, 3, 1);
1962 } else {
1963 /* normal (non-workaround) case: */
1964 ir3_split_dest(b, dst, sam, 0, ncomp);
1965 }
1966
1967 /* GETLOD returns results in 4.8 fixed point */
1968 if (opc == OPC_GETLOD) {
1969 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
1970
1971 compile_assert(ctx, tex->dest_type == nir_type_float);
1972 for (i = 0; i < 2; i++) {
1973 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_U32, TYPE_F32), 0,
1974 factor, 0);
1975 }
1976 }
1977
1978 ir3_put_dst(ctx, &tex->dest);
1979 }
1980
1981 static void
1982 emit_tex_query_levels(struct ir3_context *ctx, nir_tex_instr *tex)
1983 {
1984 struct ir3_block *b = ctx->block;
1985 struct ir3_instruction **dst, *sam;
1986
1987 dst = ir3_get_dst(ctx, &tex->dest, 1);
1988
1989 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 0b0100, 0,
1990 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
1991
1992 /* even though there is only one component, since it ends
1993 * up in .z rather than .x, we need a split_dest()
1994 */
1995 ir3_split_dest(b, dst, sam, 0, 3);
1996
1997 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1998 * the value in TEX_CONST_0 is zero-based.
1999 */
2000 if (ctx->compiler->levels_add_one)
2001 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2002
2003 ir3_put_dst(ctx, &tex->dest);
2004 }
2005
2006 static void
2007 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2008 {
2009 struct ir3_block *b = ctx->block;
2010 struct ir3_instruction **dst, *sam;
2011 struct ir3_instruction *lod;
2012 unsigned flags, coords;
2013
2014 tex_info(tex, &flags, &coords);
2015
2016 /* Actually we want the number of dimensions, not coordinates. This
2017 * distinction only matters for cubes.
2018 */
2019 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2020 coords = 2;
2021
2022 dst = ir3_get_dst(ctx, &tex->dest, 4);
2023
2024 compile_assert(ctx, tex->num_srcs == 1);
2025 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2026
2027 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2028
2029 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
2030 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2031
2032 ir3_split_dest(b, dst, sam, 0, 4);
2033
2034 /* Array size actually ends up in .w rather than .z. This doesn't
2035 * matter for miplevel 0, but for higher mips the value in z is
2036 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2037 * returned, which means that we have to add 1 to it for arrays.
2038 */
2039 if (tex->is_array) {
2040 if (ctx->compiler->levels_add_one) {
2041 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2042 } else {
2043 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2044 }
2045 }
2046
2047 ir3_put_dst(ctx, &tex->dest);
2048 }
2049
2050 static void
2051 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2052 {
2053 switch (jump->type) {
2054 case nir_jump_break:
2055 case nir_jump_continue:
2056 case nir_jump_return:
2057 /* I *think* we can simply just ignore this, and use the
2058 * successor block link to figure out where we need to
2059 * jump to for break/continue
2060 */
2061 break;
2062 default:
2063 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2064 break;
2065 }
2066 }
2067
2068 static void
2069 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2070 {
2071 switch (instr->type) {
2072 case nir_instr_type_alu:
2073 emit_alu(ctx, nir_instr_as_alu(instr));
2074 break;
2075 case nir_instr_type_deref:
2076 /* ignored, handled as part of the intrinsic they are src to */
2077 break;
2078 case nir_instr_type_intrinsic:
2079 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2080 break;
2081 case nir_instr_type_load_const:
2082 emit_load_const(ctx, nir_instr_as_load_const(instr));
2083 break;
2084 case nir_instr_type_ssa_undef:
2085 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2086 break;
2087 case nir_instr_type_tex: {
2088 nir_tex_instr *tex = nir_instr_as_tex(instr);
2089 /* couple tex instructions get special-cased:
2090 */
2091 switch (tex->op) {
2092 case nir_texop_txs:
2093 emit_tex_txs(ctx, tex);
2094 break;
2095 case nir_texop_query_levels:
2096 emit_tex_query_levels(ctx, tex);
2097 break;
2098 default:
2099 emit_tex(ctx, tex);
2100 break;
2101 }
2102 break;
2103 }
2104 case nir_instr_type_jump:
2105 emit_jump(ctx, nir_instr_as_jump(instr));
2106 break;
2107 case nir_instr_type_phi:
2108 /* we have converted phi webs to regs in NIR by now */
2109 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2110 break;
2111 case nir_instr_type_call:
2112 case nir_instr_type_parallel_copy:
2113 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2114 break;
2115 }
2116 }
2117
2118 static struct ir3_block *
2119 get_block(struct ir3_context *ctx, const nir_block *nblock)
2120 {
2121 struct ir3_block *block;
2122 struct hash_entry *hentry;
2123
2124 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2125 if (hentry)
2126 return hentry->data;
2127
2128 block = ir3_block_create(ctx->ir);
2129 block->nblock = nblock;
2130 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2131
2132 block->predecessors = _mesa_pointer_set_create(block);
2133 set_foreach(nblock->predecessors, sentry) {
2134 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2135 }
2136
2137 return block;
2138 }
2139
2140 static void
2141 emit_block(struct ir3_context *ctx, nir_block *nblock)
2142 {
2143 struct ir3_block *block = get_block(ctx, nblock);
2144
2145 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2146 if (nblock->successors[i]) {
2147 block->successors[i] =
2148 get_block(ctx, nblock->successors[i]);
2149 }
2150 }
2151
2152 ctx->block = block;
2153 list_addtail(&block->node, &ctx->ir->block_list);
2154
2155 /* re-emit addr register in each block if needed: */
2156 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2157 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2158 ctx->addr_ht[i] = NULL;
2159 }
2160
2161 nir_foreach_instr(instr, nblock) {
2162 ctx->cur_instr = instr;
2163 emit_instr(ctx, instr);
2164 ctx->cur_instr = NULL;
2165 if (ctx->error)
2166 return;
2167 }
2168 }
2169
2170 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2171
2172 static void
2173 emit_if(struct ir3_context *ctx, nir_if *nif)
2174 {
2175 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2176
2177 ctx->block->condition =
2178 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2179
2180 emit_cf_list(ctx, &nif->then_list);
2181 emit_cf_list(ctx, &nif->else_list);
2182 }
2183
2184 static void
2185 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2186 {
2187 emit_cf_list(ctx, &nloop->body);
2188 ctx->so->loops++;
2189 }
2190
2191 static void
2192 stack_push(struct ir3_context *ctx)
2193 {
2194 ctx->stack++;
2195 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2196 }
2197
2198 static void
2199 stack_pop(struct ir3_context *ctx)
2200 {
2201 compile_assert(ctx, ctx->stack > 0);
2202 ctx->stack--;
2203 }
2204
2205 static void
2206 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2207 {
2208 foreach_list_typed(nir_cf_node, node, node, list) {
2209 switch (node->type) {
2210 case nir_cf_node_block:
2211 emit_block(ctx, nir_cf_node_as_block(node));
2212 break;
2213 case nir_cf_node_if:
2214 stack_push(ctx);
2215 emit_if(ctx, nir_cf_node_as_if(node));
2216 stack_pop(ctx);
2217 break;
2218 case nir_cf_node_loop:
2219 stack_push(ctx);
2220 emit_loop(ctx, nir_cf_node_as_loop(node));
2221 stack_pop(ctx);
2222 break;
2223 case nir_cf_node_function:
2224 ir3_context_error(ctx, "TODO\n");
2225 break;
2226 }
2227 }
2228 }
2229
2230 /* emit stream-out code. At this point, the current block is the original
2231 * (nir) end block, and nir ensures that all flow control paths terminate
2232 * into the end block. We re-purpose the original end block to generate
2233 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2234 * block holding stream-out write instructions, followed by the new end
2235 * block:
2236 *
2237 * blockOrigEnd {
2238 * p0.x = (vtxcnt < maxvtxcnt)
2239 * // succs: blockStreamOut, blockNewEnd
2240 * }
2241 * blockStreamOut {
2242 * ... stream-out instructions ...
2243 * // succs: blockNewEnd
2244 * }
2245 * blockNewEnd {
2246 * }
2247 */
2248 static void
2249 emit_stream_out(struct ir3_context *ctx)
2250 {
2251 struct ir3 *ir = ctx->ir;
2252 struct ir3_stream_output_info *strmout =
2253 &ctx->so->shader->stream_output;
2254 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2255 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2256 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2257
2258 /* create vtxcnt input in input block at top of shader,
2259 * so that it is seen as live over the entire duration
2260 * of the shader:
2261 */
2262 vtxcnt = create_input(ctx, 0);
2263 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt);
2264
2265 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2266
2267 /* at this point, we are at the original 'end' block,
2268 * re-purpose this block to stream-out condition, then
2269 * append stream-out block and new-end block
2270 */
2271 orig_end_block = ctx->block;
2272
2273 // TODO these blocks need to update predecessors..
2274 // maybe w/ store_global intrinsic, we could do this
2275 // stuff in nir->nir pass
2276
2277 stream_out_block = ir3_block_create(ir);
2278 list_addtail(&stream_out_block->node, &ir->block_list);
2279
2280 new_end_block = ir3_block_create(ir);
2281 list_addtail(&new_end_block->node, &ir->block_list);
2282
2283 orig_end_block->successors[0] = stream_out_block;
2284 orig_end_block->successors[1] = new_end_block;
2285 stream_out_block->successors[0] = new_end_block;
2286
2287 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2288 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2289 cond->regs[0]->num = regid(REG_P0, 0);
2290 cond->cat2.condition = IR3_COND_LT;
2291
2292 /* condition goes on previous block to the conditional,
2293 * since it is used to pick which of the two successor
2294 * paths to take:
2295 */
2296 orig_end_block->condition = cond;
2297
2298 /* switch to stream_out_block to generate the stream-out
2299 * instructions:
2300 */
2301 ctx->block = stream_out_block;
2302
2303 /* Calculate base addresses based on vtxcnt. Instructions
2304 * generated for bases not used in following loop will be
2305 * stripped out in the backend.
2306 */
2307 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2308 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2309 unsigned stride = strmout->stride[i];
2310 struct ir3_instruction *base, *off;
2311
2312 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2313
2314 /* 24-bit should be enough: */
2315 off = ir3_MUL_U(ctx->block, vtxcnt, 0,
2316 create_immed(ctx->block, stride * 4), 0);
2317
2318 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2319 }
2320
2321 /* Generate the per-output store instructions: */
2322 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2323 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2324 unsigned c = j + strmout->output[i].start_component;
2325 struct ir3_instruction *base, *out, *stg;
2326
2327 base = bases[strmout->output[i].output_buffer];
2328 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2329
2330 stg = ir3_STG(ctx->block, base, 0, out, 0,
2331 create_immed(ctx->block, 1), 0);
2332 stg->cat6.type = TYPE_U32;
2333 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2334
2335 array_insert(ctx->block, ctx->block->keeps, stg);
2336 }
2337 }
2338
2339 /* and finally switch to the new_end_block: */
2340 ctx->block = new_end_block;
2341 }
2342
2343 static void
2344 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2345 {
2346 nir_metadata_require(impl, nir_metadata_block_index);
2347
2348 compile_assert(ctx, ctx->stack == 0);
2349
2350 emit_cf_list(ctx, &impl->body);
2351 emit_block(ctx, impl->end_block);
2352
2353 compile_assert(ctx, ctx->stack == 0);
2354
2355 /* at this point, we should have a single empty block,
2356 * into which we emit the 'end' instruction.
2357 */
2358 compile_assert(ctx, list_empty(&ctx->block->instr_list));
2359
2360 /* If stream-out (aka transform-feedback) enabled, emit the
2361 * stream-out instructions, followed by a new empty block (into
2362 * which the 'end' instruction lands).
2363 *
2364 * NOTE: it is done in this order, rather than inserting before
2365 * we emit end_block, because NIR guarantees that all blocks
2366 * flow into end_block, and that end_block has no successors.
2367 * So by re-purposing end_block as the first block of stream-
2368 * out, we guarantee that all exit paths flow into the stream-
2369 * out instructions.
2370 */
2371 if ((ctx->compiler->gpu_id < 500) &&
2372 (ctx->so->shader->stream_output.num_outputs > 0) &&
2373 !ctx->so->binning_pass) {
2374 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2375 emit_stream_out(ctx);
2376 }
2377
2378 ir3_END(ctx->block);
2379 }
2380
2381 static void
2382 setup_input(struct ir3_context *ctx, nir_variable *in)
2383 {
2384 struct ir3_shader_variant *so = ctx->so;
2385 unsigned ncomp = glsl_get_components(in->type);
2386 unsigned n = in->data.driver_location;
2387 unsigned frac = in->data.location_frac;
2388 unsigned slot = in->data.location;
2389
2390 /* skip unread inputs, we could end up with (for example), unsplit
2391 * matrix/etc inputs in the case they are not read, so just silently
2392 * skip these.
2393 */
2394 if (ncomp > 4)
2395 return;
2396
2397 so->inputs[n].slot = slot;
2398 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2399 so->inputs_count = MAX2(so->inputs_count, n + 1);
2400 so->inputs[n].interpolate = in->data.interpolation;
2401
2402 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2403
2404 /* if any varyings have 'sample' qualifer, that triggers us
2405 * to run in per-sample mode:
2406 */
2407 so->per_samp |= in->data.sample;
2408
2409 for (int i = 0; i < ncomp; i++) {
2410 struct ir3_instruction *instr = NULL;
2411 unsigned idx = (n * 4) + i + frac;
2412
2413 if (slot == VARYING_SLOT_POS) {
2414 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2415 } else if (slot == VARYING_SLOT_PNTC) {
2416 /* see for example st_nir_fixup_varying_slots().. this is
2417 * maybe a bit mesa/st specific. But we need things to line
2418 * up for this in fdN_program:
2419 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2420 * if (emit->sprite_coord_enable & texmask) {
2421 * ...
2422 * }
2423 */
2424 so->inputs[n].slot = VARYING_SLOT_VAR8;
2425 so->inputs[n].bary = true;
2426 instr = create_frag_input(ctx, false, idx);
2427 } else {
2428 /* detect the special case for front/back colors where
2429 * we need to do flat vs smooth shading depending on
2430 * rast state:
2431 */
2432 if (in->data.interpolation == INTERP_MODE_NONE) {
2433 switch (slot) {
2434 case VARYING_SLOT_COL0:
2435 case VARYING_SLOT_COL1:
2436 case VARYING_SLOT_BFC0:
2437 case VARYING_SLOT_BFC1:
2438 so->inputs[n].rasterflat = true;
2439 break;
2440 default:
2441 break;
2442 }
2443 }
2444
2445 if (ctx->compiler->flat_bypass) {
2446 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2447 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2448 so->inputs[n].use_ldlv = true;
2449 }
2450
2451 so->inputs[n].bary = true;
2452
2453 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2454 }
2455
2456 compile_assert(ctx, idx < ctx->ir->ninputs);
2457
2458 ctx->ir->inputs[idx] = instr;
2459 }
2460 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2461 for (int i = 0; i < ncomp; i++) {
2462 unsigned idx = (n * 4) + i + frac;
2463 compile_assert(ctx, idx < ctx->ir->ninputs);
2464 ctx->ir->inputs[idx] = create_input(ctx, idx);
2465 }
2466 } else {
2467 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2468 }
2469
2470 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2471 so->total_in += ncomp;
2472 }
2473 }
2474
2475 /* Initially we assign non-packed inloc's for varyings, as we don't really
2476 * know up-front which components will be unused. After all the compilation
2477 * stages we scan the shader to see which components are actually used, and
2478 * re-pack the inlocs to eliminate unneeded varyings.
2479 */
2480 static void
2481 pack_inlocs(struct ir3_context *ctx)
2482 {
2483 struct ir3_shader_variant *so = ctx->so;
2484 uint8_t used_components[so->inputs_count];
2485
2486 memset(used_components, 0, sizeof(used_components));
2487
2488 /*
2489 * First Step: scan shader to find which bary.f/ldlv remain:
2490 */
2491
2492 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2493 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2494 if (is_input(instr)) {
2495 unsigned inloc = instr->regs[1]->iim_val;
2496 unsigned i = inloc / 4;
2497 unsigned j = inloc % 4;
2498
2499 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2500 compile_assert(ctx, i < so->inputs_count);
2501
2502 used_components[i] |= 1 << j;
2503 }
2504 }
2505 }
2506
2507 /*
2508 * Second Step: reassign varying inloc/slots:
2509 */
2510
2511 unsigned actual_in = 0;
2512 unsigned inloc = 0;
2513
2514 for (unsigned i = 0; i < so->inputs_count; i++) {
2515 unsigned compmask = 0, maxcomp = 0;
2516
2517 so->inputs[i].inloc = inloc;
2518 so->inputs[i].bary = false;
2519
2520 for (unsigned j = 0; j < 4; j++) {
2521 if (!(used_components[i] & (1 << j)))
2522 continue;
2523
2524 compmask |= (1 << j);
2525 actual_in++;
2526 maxcomp = j + 1;
2527
2528 /* at this point, since used_components[i] mask is only
2529 * considering varyings (ie. not sysvals) we know this
2530 * is a varying:
2531 */
2532 so->inputs[i].bary = true;
2533 }
2534
2535 if (so->inputs[i].bary) {
2536 so->varying_in++;
2537 so->inputs[i].compmask = (1 << maxcomp) - 1;
2538 inloc += maxcomp;
2539 }
2540 }
2541
2542 /*
2543 * Third Step: reassign packed inloc's:
2544 */
2545
2546 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2547 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2548 if (is_input(instr)) {
2549 unsigned inloc = instr->regs[1]->iim_val;
2550 unsigned i = inloc / 4;
2551 unsigned j = inloc % 4;
2552
2553 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2554 }
2555 }
2556 }
2557 }
2558
2559 static void
2560 setup_output(struct ir3_context *ctx, nir_variable *out)
2561 {
2562 struct ir3_shader_variant *so = ctx->so;
2563 unsigned ncomp = glsl_get_components(out->type);
2564 unsigned n = out->data.driver_location;
2565 unsigned frac = out->data.location_frac;
2566 unsigned slot = out->data.location;
2567 unsigned comp = 0;
2568
2569 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2570 switch (slot) {
2571 case FRAG_RESULT_DEPTH:
2572 comp = 2; /* tgsi will write to .z component */
2573 so->writes_pos = true;
2574 break;
2575 case FRAG_RESULT_COLOR:
2576 so->color0_mrt = 1;
2577 break;
2578 case FRAG_RESULT_SAMPLE_MASK:
2579 so->writes_smask = true;
2580 break;
2581 default:
2582 if (slot >= FRAG_RESULT_DATA0)
2583 break;
2584 ir3_context_error(ctx, "unknown FS output name: %s\n",
2585 gl_frag_result_name(slot));
2586 }
2587 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2588 switch (slot) {
2589 case VARYING_SLOT_POS:
2590 so->writes_pos = true;
2591 break;
2592 case VARYING_SLOT_PSIZ:
2593 so->writes_psize = true;
2594 break;
2595 case VARYING_SLOT_COL0:
2596 case VARYING_SLOT_COL1:
2597 case VARYING_SLOT_BFC0:
2598 case VARYING_SLOT_BFC1:
2599 case VARYING_SLOT_FOGC:
2600 case VARYING_SLOT_CLIP_DIST0:
2601 case VARYING_SLOT_CLIP_DIST1:
2602 case VARYING_SLOT_CLIP_VERTEX:
2603 break;
2604 default:
2605 if (slot >= VARYING_SLOT_VAR0)
2606 break;
2607 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2608 break;
2609 ir3_context_error(ctx, "unknown VS output name: %s\n",
2610 gl_varying_slot_name(slot));
2611 }
2612 } else {
2613 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2614 }
2615
2616 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2617
2618 so->outputs[n].slot = slot;
2619 so->outputs[n].regid = regid(n, comp);
2620 so->outputs_count = MAX2(so->outputs_count, n + 1);
2621
2622 for (int i = 0; i < ncomp; i++) {
2623 unsigned idx = (n * 4) + i + frac;
2624 compile_assert(ctx, idx < ctx->ir->noutputs);
2625 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2626 }
2627
2628 /* if varying packing doesn't happen, we could end up in a situation
2629 * with "holes" in the output, and since the per-generation code that
2630 * sets up varying linkage registers doesn't expect to have more than
2631 * one varying per vec4 slot, pad the holes.
2632 *
2633 * Note that this should probably generate a performance warning of
2634 * some sort.
2635 */
2636 for (int i = 0; i < frac; i++) {
2637 unsigned idx = (n * 4) + i;
2638 if (!ctx->ir->outputs[idx]) {
2639 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2640 }
2641 }
2642 }
2643
2644 static int
2645 max_drvloc(struct exec_list *vars)
2646 {
2647 int drvloc = -1;
2648 nir_foreach_variable(var, vars) {
2649 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2650 }
2651 return drvloc;
2652 }
2653
2654 static const unsigned max_sysvals[] = {
2655 [MESA_SHADER_FRAGMENT] = 24, // TODO
2656 [MESA_SHADER_VERTEX] = 16,
2657 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2658 [MESA_SHADER_KERNEL] = 16, // TODO how many do we actually need?
2659 };
2660
2661 static void
2662 emit_instructions(struct ir3_context *ctx)
2663 {
2664 unsigned ninputs, noutputs;
2665 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2666
2667 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2668 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2669
2670 /* we need to leave room for sysvals:
2671 */
2672 ninputs += max_sysvals[ctx->so->type];
2673
2674 ctx->ir = ir3_create(ctx->compiler, ctx->so->type, ninputs, noutputs);
2675
2676 /* Create inputs in first block: */
2677 ctx->block = get_block(ctx, nir_start_block(fxn));
2678 ctx->in_block = ctx->block;
2679 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2680
2681 ninputs -= max_sysvals[ctx->so->type];
2682
2683 /* for fragment shader, the vcoord input register is used as the
2684 * base for bary.f varying fetch instrs:
2685 *
2686 * TODO defer creating ctx->ij_pixel and corresponding sysvals
2687 * until emit_intrinsic when we know they are actually needed.
2688 * For now, we defer creating ctx->ij_centroid, etc, since we
2689 * only need ij_pixel for "old style" varying inputs (ie.
2690 * tgsi_to_nir)
2691 */
2692 struct ir3_instruction *vcoord = NULL;
2693 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2694 struct ir3_instruction *xy[2];
2695
2696 vcoord = create_input_compmask(ctx, 0, 0x3);
2697 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2698
2699 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
2700 }
2701
2702 /* Setup inputs: */
2703 nir_foreach_variable(var, &ctx->s->inputs) {
2704 setup_input(ctx, var);
2705 }
2706
2707 /* Defer add_sysval_input() stuff until after setup_inputs(),
2708 * because sysvals need to be appended after varyings:
2709 */
2710 if (vcoord) {
2711 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL,
2712 0x3, vcoord);
2713 }
2714
2715 /* Setup outputs: */
2716 nir_foreach_variable(var, &ctx->s->outputs) {
2717 setup_output(ctx, var);
2718 }
2719
2720 /* Find # of samplers: */
2721 nir_foreach_variable(var, &ctx->s->uniforms) {
2722 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
2723 /* just assume that we'll be reading from images.. if it
2724 * is write-only we don't have to count it, but not sure
2725 * if there is a good way to know?
2726 */
2727 ctx->so->num_samp += glsl_type_get_image_count(var->type);
2728 }
2729
2730 /* NOTE: need to do something more clever when we support >1 fxn */
2731 nir_foreach_register(reg, &fxn->registers) {
2732 ir3_declare_array(ctx, reg);
2733 }
2734 /* And emit the body: */
2735 ctx->impl = fxn;
2736 emit_function(ctx, fxn);
2737 }
2738
2739 /* from NIR perspective, we actually have varying inputs. But the varying
2740 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2741 * only actual inputs are the sysvals.
2742 */
2743 static void
2744 fixup_frag_inputs(struct ir3_context *ctx)
2745 {
2746 struct ir3_shader_variant *so = ctx->so;
2747 struct ir3 *ir = ctx->ir;
2748 unsigned i = 0;
2749
2750 /* sysvals should appear at the end of the inputs, drop everything else: */
2751 while ((i < so->inputs_count) && !so->inputs[i].sysval)
2752 i++;
2753
2754 /* at IR level, inputs are always blocks of 4 scalars: */
2755 i *= 4;
2756
2757 ir->inputs = &ir->inputs[i];
2758 ir->ninputs -= i;
2759 }
2760
2761 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2762 * need to assign the tex state indexes for these after we know the
2763 * max tex index.
2764 */
2765 static void
2766 fixup_astc_srgb(struct ir3_context *ctx)
2767 {
2768 struct ir3_shader_variant *so = ctx->so;
2769 /* indexed by original tex idx, value is newly assigned alpha sampler
2770 * state tex idx. Zero is invalid since there is at least one sampler
2771 * if we get here.
2772 */
2773 unsigned alt_tex_state[16] = {0};
2774 unsigned tex_idx = ctx->max_texture_index + 1;
2775 unsigned idx = 0;
2776
2777 so->astc_srgb.base = tex_idx;
2778
2779 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
2780 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
2781
2782 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
2783
2784 if (alt_tex_state[sam->cat5.tex] == 0) {
2785 /* assign new alternate/alpha tex state slot: */
2786 alt_tex_state[sam->cat5.tex] = tex_idx++;
2787 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
2788 so->astc_srgb.count++;
2789 }
2790
2791 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
2792 }
2793 }
2794
2795 static void
2796 fixup_binning_pass(struct ir3_context *ctx)
2797 {
2798 struct ir3_shader_variant *so = ctx->so;
2799 struct ir3 *ir = ctx->ir;
2800 unsigned i, j;
2801
2802 for (i = 0, j = 0; i < so->outputs_count; i++) {
2803 unsigned slot = so->outputs[i].slot;
2804
2805 /* throw away everything but first position/psize */
2806 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
2807 if (i != j) {
2808 so->outputs[j] = so->outputs[i];
2809 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
2810 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
2811 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
2812 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
2813 }
2814 j++;
2815 }
2816 }
2817 so->outputs_count = j;
2818 ir->noutputs = j * 4;
2819 }
2820
2821 int
2822 ir3_compile_shader_nir(struct ir3_compiler *compiler,
2823 struct ir3_shader_variant *so)
2824 {
2825 struct ir3_context *ctx;
2826 struct ir3 *ir;
2827 struct ir3_instruction **inputs;
2828 unsigned i;
2829 int ret = 0, max_bary;
2830
2831 assert(!so->ir);
2832
2833 ctx = ir3_context_init(compiler, so);
2834 if (!ctx) {
2835 DBG("INIT failed!");
2836 ret = -1;
2837 goto out;
2838 }
2839
2840 emit_instructions(ctx);
2841
2842 if (ctx->error) {
2843 DBG("EMIT failed!");
2844 ret = -1;
2845 goto out;
2846 }
2847
2848 ir = so->ir = ctx->ir;
2849
2850 /* keep track of the inputs from TGSI perspective.. */
2851 inputs = ir->inputs;
2852
2853 /* but fixup actual inputs for frag shader: */
2854 if (so->type == MESA_SHADER_FRAGMENT)
2855 fixup_frag_inputs(ctx);
2856
2857 /* at this point, for binning pass, throw away unneeded outputs: */
2858 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
2859 fixup_binning_pass(ctx);
2860
2861 /* if we want half-precision outputs, mark the output registers
2862 * as half:
2863 */
2864 if (so->key.half_precision) {
2865 for (i = 0; i < ir->noutputs; i++) {
2866 struct ir3_instruction *out = ir->outputs[i];
2867
2868 if (!out)
2869 continue;
2870
2871 /* if frag shader writes z, that needs to be full precision: */
2872 if (so->outputs[i/4].slot == FRAG_RESULT_DEPTH)
2873 continue;
2874
2875 out->regs[0]->flags |= IR3_REG_HALF;
2876 /* output could be a fanout (ie. texture fetch output)
2877 * in which case we need to propagate the half-reg flag
2878 * up to the definer so that RA sees it:
2879 */
2880 if (out->opc == OPC_META_FO) {
2881 out = out->regs[1]->instr;
2882 out->regs[0]->flags |= IR3_REG_HALF;
2883 }
2884
2885 if (out->opc == OPC_MOV) {
2886 out->cat1.dst_type = half_type(out->cat1.dst_type);
2887 }
2888 }
2889 }
2890
2891 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2892 printf("BEFORE CP:\n");
2893 ir3_print(ir);
2894 }
2895
2896 ir3_cp(ir, so);
2897
2898 /* at this point, for binning pass, throw away unneeded outputs:
2899 * Note that for a6xx and later, we do this after ir3_cp to ensure
2900 * that the uniform/constant layout for BS and VS matches, so that
2901 * we can re-use same VS_CONST state group.
2902 */
2903 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
2904 fixup_binning_pass(ctx);
2905
2906 /* for a6xx+, binning and draw pass VS use same VBO state, so we
2907 * need to make sure not to remove any inputs that are used by
2908 * the nonbinning VS.
2909 */
2910 if (ctx->compiler->gpu_id >= 600 && so->binning_pass) {
2911 debug_assert(so->type == MESA_SHADER_VERTEX);
2912 for (int i = 0; i < ir->ninputs; i++) {
2913 struct ir3_instruction *in = ir->inputs[i];
2914
2915 if (!in)
2916 continue;
2917
2918 unsigned n = i / 4;
2919 unsigned c = i % 4;
2920
2921 debug_assert(n < so->nonbinning->inputs_count);
2922
2923 if (so->nonbinning->inputs[n].sysval)
2924 continue;
2925
2926 /* be sure to keep inputs, even if only used in VS */
2927 if (so->nonbinning->inputs[n].compmask & (1 << c))
2928 array_insert(in->block, in->block->keeps, in);
2929 }
2930 }
2931
2932 /* Insert mov if there's same instruction for each output.
2933 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
2934 */
2935 for (int i = ir->noutputs - 1; i >= 0; i--) {
2936 if (!ir->outputs[i])
2937 continue;
2938 for (unsigned j = 0; j < i; j++) {
2939 if (ir->outputs[i] == ir->outputs[j]) {
2940 ir->outputs[i] =
2941 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
2942 }
2943 }
2944 }
2945
2946 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2947 printf("BEFORE GROUPING:\n");
2948 ir3_print(ir);
2949 }
2950
2951 ir3_sched_add_deps(ir);
2952
2953 /* Group left/right neighbors, inserting mov's where needed to
2954 * solve conflicts:
2955 */
2956 ir3_group(ir);
2957
2958 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2959 printf("AFTER GROUPING:\n");
2960 ir3_print(ir);
2961 }
2962
2963 ir3_depth(ir);
2964
2965 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2966 printf("AFTER DEPTH:\n");
2967 ir3_print(ir);
2968 }
2969
2970 /* do Sethi–Ullman numbering before scheduling: */
2971 ir3_sun(ir);
2972
2973 ret = ir3_sched(ir);
2974 if (ret) {
2975 DBG("SCHED failed!");
2976 goto out;
2977 }
2978
2979 if (compiler->gpu_id >= 600) {
2980 ir3_a6xx_fixup_atomic_dests(ir, so);
2981 }
2982
2983 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2984 printf("AFTER SCHED:\n");
2985 ir3_print(ir);
2986 }
2987
2988 ret = ir3_ra(so);
2989 if (ret) {
2990 DBG("RA failed!");
2991 goto out;
2992 }
2993
2994 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2995 printf("AFTER RA:\n");
2996 ir3_print(ir);
2997 }
2998
2999 if (so->type == MESA_SHADER_FRAGMENT)
3000 pack_inlocs(ctx);
3001
3002 /* fixup input/outputs: */
3003 for (i = 0; i < so->outputs_count; i++) {
3004 /* sometimes we get outputs that don't write the .x coord, like:
3005 *
3006 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
3007 *
3008 * Presumably the result of varying packing and then eliminating
3009 * some unneeded varyings? Just skip head to the first valid
3010 * component of the output.
3011 */
3012 for (unsigned j = 0; j < 4; j++) {
3013 struct ir3_instruction *instr = ir->outputs[(i*4) + j];
3014 if (instr) {
3015 so->outputs[i].regid = instr->regs[0]->num;
3016 so->outputs[i].half = !!(instr->regs[0]->flags & IR3_REG_HALF);
3017 break;
3018 }
3019 }
3020 }
3021
3022 /* Note that some or all channels of an input may be unused: */
3023 for (i = 0; i < so->inputs_count; i++) {
3024 unsigned j, reg = regid(63,0);
3025 bool half = false;
3026 for (j = 0; j < 4; j++) {
3027 struct ir3_instruction *in = inputs[(i*4) + j];
3028
3029 if (!in)
3030 continue;
3031
3032 if (in->flags & IR3_INSTR_UNUSED)
3033 continue;
3034
3035 reg = in->regs[0]->num - j;
3036 if (half) {
3037 compile_assert(ctx, in->regs[0]->flags & IR3_REG_HALF);
3038 } else {
3039 half = !!(in->regs[0]->flags & IR3_REG_HALF);
3040 }
3041 }
3042 so->inputs[i].regid = reg;
3043 so->inputs[i].half = half;
3044 }
3045
3046 if (ctx->astc_srgb)
3047 fixup_astc_srgb(ctx);
3048
3049 /* We need to do legalize after (for frag shader's) the "bary.f"
3050 * offsets (inloc) have been assigned.
3051 */
3052 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
3053
3054 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3055 printf("AFTER LEGALIZE:\n");
3056 ir3_print(ir);
3057 }
3058
3059 so->branchstack = ctx->max_stack;
3060
3061 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3062 if (so->type == MESA_SHADER_FRAGMENT)
3063 so->total_in = max_bary + 1;
3064
3065 so->max_sun = ir->max_sun;
3066
3067 out:
3068 if (ret) {
3069 if (so->ir)
3070 ir3_destroy(so->ir);
3071 so->ir = NULL;
3072 }
3073 ir3_context_free(ctx);
3074
3075 return ret;
3076 }