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freedreno/ir3: enable indirect tex/samp (sam.s2en)
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 ir3_reg_create(mov, 0, 0);
55 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
56 src->instr = collect;
57 src->size = arrsz;
58 src->array.offset = n;
59
60 ir3_instr_set_address(mov, address);
61
62 return mov;
63 }
64
65 static struct ir3_instruction *
66 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
67 {
68 struct ir3_instruction *in;
69
70 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
71 in->inout.block = ctx->in_block;
72 ir3_reg_create(in, n, 0);
73
74 in->regs[0]->wrmask = compmask;
75
76 return in;
77 }
78
79 static struct ir3_instruction *
80 create_input(struct ir3_context *ctx, unsigned n)
81 {
82 return create_input_compmask(ctx, n, 0x1);
83 }
84
85 static struct ir3_instruction *
86 create_frag_input(struct ir3_context *ctx, bool use_ldlv)
87 {
88 struct ir3_block *block = ctx->block;
89 struct ir3_instruction *instr;
90 /* actual inloc is assigned and fixed up later: */
91 struct ir3_instruction *inloc = create_immed(block, 0);
92
93 if (use_ldlv) {
94 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
95 instr->cat6.type = TYPE_U32;
96 instr->cat6.iim_val = 1;
97 } else {
98 instr = ir3_BARY_F(block, inloc, 0, ctx->frag_vcoord, 0);
99 instr->regs[2]->wrmask = 0x3;
100 }
101
102 return instr;
103 }
104
105 static struct ir3_instruction *
106 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
107 {
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 unsigned n = ctx->so->constbase.driver_param;
111 unsigned r = regid(n + dp / 4, dp % 4);
112 return create_uniform(ctx->block, r);
113 }
114
115 /*
116 * Adreno uses uint rather than having dedicated bool type,
117 * which (potentially) requires some conversion, in particular
118 * when using output of an bool instr to int input, or visa
119 * versa.
120 *
121 * | Adreno | NIR |
122 * -------+---------+-------+-
123 * true | 1 | ~0 |
124 * false | 0 | 0 |
125 *
126 * To convert from an adreno bool (uint) to nir, use:
127 *
128 * absneg.s dst, (neg)src
129 *
130 * To convert back in the other direction:
131 *
132 * absneg.s dst, (abs)arc
133 *
134 * The CP step can clean up the absneg.s that cancel each other
135 * out, and with a slight bit of extra cleverness (to recognize
136 * the instructions which produce either a 0 or 1) can eliminate
137 * the absneg.s's completely when an instruction that wants
138 * 0/1 consumes the result. For example, when a nir 'bcsel'
139 * consumes the result of 'feq'. So we should be able to get by
140 * without a boolean resolve step, and without incuring any
141 * extra penalty in instruction count.
142 */
143
144 /* NIR bool -> native (adreno): */
145 static struct ir3_instruction *
146 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
147 {
148 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
149 }
150
151 /* native (adreno) -> NIR bool: */
152 static struct ir3_instruction *
153 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
154 {
155 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
156 }
157
158 /*
159 * alu/sfu instructions:
160 */
161
162 static struct ir3_instruction *
163 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
164 unsigned src_bitsize, nir_op op)
165 {
166 type_t src_type, dst_type;
167
168 switch (op) {
169 case nir_op_f2f32:
170 case nir_op_f2f16_rtne:
171 case nir_op_f2f16_rtz:
172 case nir_op_f2f16:
173 case nir_op_f2i32:
174 case nir_op_f2i16:
175 case nir_op_f2i8:
176 case nir_op_f2u32:
177 case nir_op_f2u16:
178 case nir_op_f2u8:
179 switch (src_bitsize) {
180 case 32:
181 src_type = TYPE_F32;
182 break;
183 case 16:
184 src_type = TYPE_F16;
185 break;
186 default:
187 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
188 }
189 break;
190
191 case nir_op_i2f32:
192 case nir_op_i2f16:
193 case nir_op_i2i32:
194 case nir_op_i2i16:
195 case nir_op_i2i8:
196 switch (src_bitsize) {
197 case 32:
198 src_type = TYPE_S32;
199 break;
200 case 16:
201 src_type = TYPE_S16;
202 break;
203 case 8:
204 src_type = TYPE_S8;
205 break;
206 default:
207 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
208 }
209 break;
210
211 case nir_op_u2f32:
212 case nir_op_u2f16:
213 case nir_op_u2u32:
214 case nir_op_u2u16:
215 case nir_op_u2u8:
216 switch (src_bitsize) {
217 case 32:
218 src_type = TYPE_U32;
219 break;
220 case 16:
221 src_type = TYPE_U16;
222 break;
223 case 8:
224 src_type = TYPE_U8;
225 break;
226 default:
227 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
228 }
229 break;
230
231 default:
232 ir3_context_error(ctx, "invalid conversion op: %u", op);
233 }
234
235 switch (op) {
236 case nir_op_f2f32:
237 case nir_op_i2f32:
238 case nir_op_u2f32:
239 dst_type = TYPE_F32;
240 break;
241
242 case nir_op_f2f16_rtne:
243 case nir_op_f2f16_rtz:
244 case nir_op_f2f16:
245 /* TODO how to handle rounding mode? */
246 case nir_op_i2f16:
247 case nir_op_u2f16:
248 dst_type = TYPE_F16;
249 break;
250
251 case nir_op_f2i32:
252 case nir_op_i2i32:
253 dst_type = TYPE_S32;
254 break;
255
256 case nir_op_f2i16:
257 case nir_op_i2i16:
258 dst_type = TYPE_S16;
259 break;
260
261 case nir_op_f2i8:
262 case nir_op_i2i8:
263 dst_type = TYPE_S8;
264 break;
265
266 case nir_op_f2u32:
267 case nir_op_u2u32:
268 dst_type = TYPE_U32;
269 break;
270
271 case nir_op_f2u16:
272 case nir_op_u2u16:
273 dst_type = TYPE_U16;
274 break;
275
276 case nir_op_f2u8:
277 case nir_op_u2u8:
278 dst_type = TYPE_U8;
279 break;
280
281 default:
282 ir3_context_error(ctx, "invalid conversion op: %u", op);
283 }
284
285 return ir3_COV(ctx->block, src, src_type, dst_type);
286 }
287
288 static void
289 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
290 {
291 const nir_op_info *info = &nir_op_infos[alu->op];
292 struct ir3_instruction **dst, *src[info->num_inputs];
293 unsigned bs[info->num_inputs]; /* bit size */
294 struct ir3_block *b = ctx->block;
295 unsigned dst_sz, wrmask;
296
297 if (alu->dest.dest.is_ssa) {
298 dst_sz = alu->dest.dest.ssa.num_components;
299 wrmask = (1 << dst_sz) - 1;
300 } else {
301 dst_sz = alu->dest.dest.reg.reg->num_components;
302 wrmask = alu->dest.write_mask;
303 }
304
305 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
306
307 /* Vectors are special in that they have non-scalarized writemasks,
308 * and just take the first swizzle channel for each argument in
309 * order into each writemask channel.
310 */
311 if ((alu->op == nir_op_vec2) ||
312 (alu->op == nir_op_vec3) ||
313 (alu->op == nir_op_vec4)) {
314
315 for (int i = 0; i < info->num_inputs; i++) {
316 nir_alu_src *asrc = &alu->src[i];
317
318 compile_assert(ctx, !asrc->abs);
319 compile_assert(ctx, !asrc->negate);
320
321 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
322 if (!src[i])
323 src[i] = create_immed(ctx->block, 0);
324 dst[i] = ir3_MOV(b, src[i], TYPE_U32);
325 }
326
327 ir3_put_dst(ctx, &alu->dest.dest);
328 return;
329 }
330
331 /* We also get mov's with more than one component for mov's so
332 * handle those specially:
333 */
334 if ((alu->op == nir_op_imov) || (alu->op == nir_op_fmov)) {
335 type_t type = (alu->op == nir_op_imov) ? TYPE_U32 : TYPE_F32;
336 nir_alu_src *asrc = &alu->src[0];
337 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
338
339 for (unsigned i = 0; i < dst_sz; i++) {
340 if (wrmask & (1 << i)) {
341 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], type);
342 } else {
343 dst[i] = NULL;
344 }
345 }
346
347 ir3_put_dst(ctx, &alu->dest.dest);
348 return;
349 }
350
351 /* General case: We can just grab the one used channel per src. */
352 for (int i = 0; i < info->num_inputs; i++) {
353 unsigned chan = ffs(alu->dest.write_mask) - 1;
354 nir_alu_src *asrc = &alu->src[i];
355
356 compile_assert(ctx, !asrc->abs);
357 compile_assert(ctx, !asrc->negate);
358
359 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
360 bs[i] = nir_src_bit_size(asrc->src);
361
362 compile_assert(ctx, src[i]);
363 }
364
365 switch (alu->op) {
366 case nir_op_f2f32:
367 case nir_op_f2f16_rtne:
368 case nir_op_f2f16_rtz:
369 case nir_op_f2f16:
370 case nir_op_f2i32:
371 case nir_op_f2i16:
372 case nir_op_f2i8:
373 case nir_op_f2u32:
374 case nir_op_f2u16:
375 case nir_op_f2u8:
376 case nir_op_i2f32:
377 case nir_op_i2f16:
378 case nir_op_i2i32:
379 case nir_op_i2i16:
380 case nir_op_i2i8:
381 case nir_op_u2f32:
382 case nir_op_u2f16:
383 case nir_op_u2u32:
384 case nir_op_u2u16:
385 case nir_op_u2u8:
386 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
387 break;
388 case nir_op_f2b32:
389 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
390 dst[0]->cat2.condition = IR3_COND_NE;
391 dst[0] = ir3_n2b(b, dst[0]);
392 break;
393 case nir_op_b2f16:
394 case nir_op_b2f32:
395 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
396 break;
397 case nir_op_b2i8:
398 case nir_op_b2i16:
399 case nir_op_b2i32:
400 dst[0] = ir3_b2n(b, src[0]);
401 break;
402 case nir_op_i2b32:
403 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
404 dst[0]->cat2.condition = IR3_COND_NE;
405 dst[0] = ir3_n2b(b, dst[0]);
406 break;
407
408 case nir_op_fneg:
409 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
410 break;
411 case nir_op_fabs:
412 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
413 break;
414 case nir_op_fmax:
415 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
416 break;
417 case nir_op_fmin:
418 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
419 break;
420 case nir_op_fsat:
421 /* if there is just a single use of the src, and it supports
422 * (sat) bit, we can just fold the (sat) flag back to the
423 * src instruction and create a mov. This is easier for cp
424 * to eliminate.
425 *
426 * TODO probably opc_cat==4 is ok too
427 */
428 if (alu->src[0].src.is_ssa &&
429 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
430 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
431 src[0]->flags |= IR3_INSTR_SAT;
432 dst[0] = ir3_MOV(b, src[0], TYPE_U32);
433 } else {
434 /* otherwise generate a max.f that saturates.. blob does
435 * similar (generating a cat2 mov using max.f)
436 */
437 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
438 dst[0]->flags |= IR3_INSTR_SAT;
439 }
440 break;
441 case nir_op_fmul:
442 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
443 break;
444 case nir_op_fadd:
445 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
446 break;
447 case nir_op_fsub:
448 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
449 break;
450 case nir_op_ffma:
451 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
452 break;
453 case nir_op_fddx:
454 dst[0] = ir3_DSX(b, src[0], 0);
455 dst[0]->cat5.type = TYPE_F32;
456 break;
457 case nir_op_fddy:
458 dst[0] = ir3_DSY(b, src[0], 0);
459 dst[0]->cat5.type = TYPE_F32;
460 break;
461 break;
462 case nir_op_flt32:
463 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
464 dst[0]->cat2.condition = IR3_COND_LT;
465 dst[0] = ir3_n2b(b, dst[0]);
466 break;
467 case nir_op_fge32:
468 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
469 dst[0]->cat2.condition = IR3_COND_GE;
470 dst[0] = ir3_n2b(b, dst[0]);
471 break;
472 case nir_op_feq32:
473 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
474 dst[0]->cat2.condition = IR3_COND_EQ;
475 dst[0] = ir3_n2b(b, dst[0]);
476 break;
477 case nir_op_fne32:
478 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
479 dst[0]->cat2.condition = IR3_COND_NE;
480 dst[0] = ir3_n2b(b, dst[0]);
481 break;
482 case nir_op_fceil:
483 dst[0] = ir3_CEIL_F(b, src[0], 0);
484 break;
485 case nir_op_ffloor:
486 dst[0] = ir3_FLOOR_F(b, src[0], 0);
487 break;
488 case nir_op_ftrunc:
489 dst[0] = ir3_TRUNC_F(b, src[0], 0);
490 break;
491 case nir_op_fround_even:
492 dst[0] = ir3_RNDNE_F(b, src[0], 0);
493 break;
494 case nir_op_fsign:
495 dst[0] = ir3_SIGN_F(b, src[0], 0);
496 break;
497
498 case nir_op_fsin:
499 dst[0] = ir3_SIN(b, src[0], 0);
500 break;
501 case nir_op_fcos:
502 dst[0] = ir3_COS(b, src[0], 0);
503 break;
504 case nir_op_frsq:
505 dst[0] = ir3_RSQ(b, src[0], 0);
506 break;
507 case nir_op_frcp:
508 dst[0] = ir3_RCP(b, src[0], 0);
509 break;
510 case nir_op_flog2:
511 dst[0] = ir3_LOG2(b, src[0], 0);
512 break;
513 case nir_op_fexp2:
514 dst[0] = ir3_EXP2(b, src[0], 0);
515 break;
516 case nir_op_fsqrt:
517 dst[0] = ir3_SQRT(b, src[0], 0);
518 break;
519
520 case nir_op_iabs:
521 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
522 break;
523 case nir_op_iadd:
524 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
525 break;
526 case nir_op_iand:
527 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
528 break;
529 case nir_op_imax:
530 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
531 break;
532 case nir_op_umax:
533 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
534 break;
535 case nir_op_imin:
536 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
537 break;
538 case nir_op_umin:
539 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
540 break;
541 case nir_op_imul:
542 /*
543 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
544 * mull.u tmp0, a, b ; mul low, i.e. al * bl
545 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
546 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
547 */
548 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0,
549 ir3_MADSH_M16(b, src[0], 0, src[1], 0,
550 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0);
551 break;
552 case nir_op_ineg:
553 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
554 break;
555 case nir_op_inot:
556 dst[0] = ir3_NOT_B(b, src[0], 0);
557 break;
558 case nir_op_ior:
559 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
560 break;
561 case nir_op_ishl:
562 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
563 break;
564 case nir_op_ishr:
565 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
566 break;
567 case nir_op_isub:
568 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
569 break;
570 case nir_op_ixor:
571 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
572 break;
573 case nir_op_ushr:
574 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
575 break;
576 case nir_op_ilt32:
577 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
578 dst[0]->cat2.condition = IR3_COND_LT;
579 dst[0] = ir3_n2b(b, dst[0]);
580 break;
581 case nir_op_ige32:
582 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
583 dst[0]->cat2.condition = IR3_COND_GE;
584 dst[0] = ir3_n2b(b, dst[0]);
585 break;
586 case nir_op_ieq32:
587 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
588 dst[0]->cat2.condition = IR3_COND_EQ;
589 dst[0] = ir3_n2b(b, dst[0]);
590 break;
591 case nir_op_ine32:
592 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
593 dst[0]->cat2.condition = IR3_COND_NE;
594 dst[0] = ir3_n2b(b, dst[0]);
595 break;
596 case nir_op_ult32:
597 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
598 dst[0]->cat2.condition = IR3_COND_LT;
599 dst[0] = ir3_n2b(b, dst[0]);
600 break;
601 case nir_op_uge32:
602 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
603 dst[0]->cat2.condition = IR3_COND_GE;
604 dst[0] = ir3_n2b(b, dst[0]);
605 break;
606
607 case nir_op_b32csel: {
608 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
609 compile_assert(ctx, bs[1] == bs[2]);
610 /* the boolean condition is 32b even if src[1] and src[2] are
611 * half-precision, but sel.b16 wants all three src's to be the
612 * same type.
613 */
614 if (bs[1] < 32)
615 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
616 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
617 break;
618 }
619 case nir_op_bit_count:
620 dst[0] = ir3_CBITS_B(b, src[0], 0);
621 break;
622 case nir_op_ifind_msb: {
623 struct ir3_instruction *cmp;
624 dst[0] = ir3_CLZ_S(b, src[0], 0);
625 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
626 cmp->cat2.condition = IR3_COND_GE;
627 dst[0] = ir3_SEL_B32(b,
628 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
629 cmp, 0, dst[0], 0);
630 break;
631 }
632 case nir_op_ufind_msb:
633 dst[0] = ir3_CLZ_B(b, src[0], 0);
634 dst[0] = ir3_SEL_B32(b,
635 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
636 src[0], 0, dst[0], 0);
637 break;
638 case nir_op_find_lsb:
639 dst[0] = ir3_BFREV_B(b, src[0], 0);
640 dst[0] = ir3_CLZ_B(b, dst[0], 0);
641 break;
642 case nir_op_bitfield_reverse:
643 dst[0] = ir3_BFREV_B(b, src[0], 0);
644 break;
645
646 default:
647 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
648 nir_op_infos[alu->op].name);
649 break;
650 }
651
652 ir3_put_dst(ctx, &alu->dest.dest);
653 }
654
655 /* handles direct/indirect UBO reads: */
656 static void
657 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
658 struct ir3_instruction **dst)
659 {
660 struct ir3_block *b = ctx->block;
661 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
662 nir_const_value *const_offset;
663 /* UBO addresses are the first driver params: */
664 unsigned ubo = regid(ctx->so->constbase.ubo, 0);
665 const unsigned ptrsz = ir3_pointer_size(ctx);
666
667 int off = 0;
668
669 /* First src is ubo index, which could either be an immed or not: */
670 src0 = ir3_get_src(ctx, &intr->src[0])[0];
671 if (is_same_type_mov(src0) &&
672 (src0->regs[1]->flags & IR3_REG_IMMED)) {
673 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
674 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
675 } else {
676 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, 4));
677 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, 4));
678 }
679
680 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
681 addr = base_lo;
682
683 const_offset = nir_src_as_const_value(intr->src[1]);
684 if (const_offset) {
685 off += const_offset->u32[0];
686 } else {
687 /* For load_ubo_indirect, second src is indirect offset: */
688 src1 = ir3_get_src(ctx, &intr->src[1])[0];
689
690 /* and add offset to addr: */
691 addr = ir3_ADD_S(b, addr, 0, src1, 0);
692 }
693
694 /* if offset is to large to encode in the ldg, split it out: */
695 if ((off + (intr->num_components * 4)) > 1024) {
696 /* split out the minimal amount to improve the odds that
697 * cp can fit the immediate in the add.s instruction:
698 */
699 unsigned off2 = off + (intr->num_components * 4) - 1024;
700 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
701 off -= off2;
702 }
703
704 if (ptrsz == 2) {
705 struct ir3_instruction *carry;
706
707 /* handle 32b rollover, ie:
708 * if (addr < base_lo)
709 * base_hi++
710 */
711 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
712 carry->cat2.condition = IR3_COND_LT;
713 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
714
715 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
716 }
717
718 for (int i = 0; i < intr->num_components; i++) {
719 struct ir3_instruction *load =
720 ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
721 load->cat6.type = TYPE_U32;
722 load->cat6.src_offset = off + i * 4; /* byte offset */
723 dst[i] = load;
724 }
725 }
726
727 /* src[] = { block_index } */
728 static void
729 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
730 struct ir3_instruction **dst)
731 {
732 /* SSBO size stored as a const starting at ssbo_sizes: */
733 unsigned blk_idx = nir_src_as_const_value(intr->src[0])->u32[0];
734 unsigned idx = regid(ctx->so->constbase.ssbo_sizes, 0) +
735 ctx->so->const_layout.ssbo_size.off[blk_idx];
736
737 debug_assert(ctx->so->const_layout.ssbo_size.mask & (1 << blk_idx));
738
739 dst[0] = create_uniform(ctx->block, idx);
740 }
741
742 /* src[] = { offset }. const_index[] = { base } */
743 static void
744 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
745 struct ir3_instruction **dst)
746 {
747 struct ir3_block *b = ctx->block;
748 struct ir3_instruction *ldl, *offset;
749 unsigned base;
750
751 offset = ir3_get_src(ctx, &intr->src[0])[0];
752 base = nir_intrinsic_base(intr);
753
754 ldl = ir3_LDL(b, offset, 0, create_immed(b, intr->num_components), 0);
755 ldl->cat6.src_offset = base;
756 ldl->cat6.type = utype_dst(intr->dest);
757 ldl->regs[0]->wrmask = MASK(intr->num_components);
758
759 ldl->barrier_class = IR3_BARRIER_SHARED_R;
760 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
761
762 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
763 }
764
765 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
766 static void
767 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
768 {
769 struct ir3_block *b = ctx->block;
770 struct ir3_instruction *stl, *offset;
771 struct ir3_instruction * const *value;
772 unsigned base, wrmask;
773
774 value = ir3_get_src(ctx, &intr->src[0]);
775 offset = ir3_get_src(ctx, &intr->src[1])[0];
776
777 base = nir_intrinsic_base(intr);
778 wrmask = nir_intrinsic_write_mask(intr);
779
780 /* Combine groups of consecutive enabled channels in one write
781 * message. We use ffs to find the first enabled channel and then ffs on
782 * the bit-inverse, down-shifted writemask to determine the length of
783 * the block of enabled bits.
784 *
785 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
786 */
787 while (wrmask) {
788 unsigned first_component = ffs(wrmask) - 1;
789 unsigned length = ffs(~(wrmask >> first_component)) - 1;
790
791 stl = ir3_STL(b, offset, 0,
792 ir3_create_collect(ctx, &value[first_component], length), 0,
793 create_immed(b, length), 0);
794 stl->cat6.dst_offset = first_component + base;
795 stl->cat6.type = utype_src(intr->src[0]);
796 stl->barrier_class = IR3_BARRIER_SHARED_W;
797 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
798
799 array_insert(b, b->keeps, stl);
800
801 /* Clear the bits in the writemask that we just wrote, then try
802 * again to see if more channels are left.
803 */
804 wrmask &= (15 << (first_component + length));
805 }
806 }
807
808 /*
809 * CS shared variable atomic intrinsics
810 *
811 * All of the shared variable atomic memory operations read a value from
812 * memory, compute a new value using one of the operations below, write the
813 * new value to memory, and return the original value read.
814 *
815 * All operations take 2 sources except CompSwap that takes 3. These
816 * sources represent:
817 *
818 * 0: The offset into the shared variable storage region that the atomic
819 * operation will operate on.
820 * 1: The data parameter to the atomic function (i.e. the value to add
821 * in shared_atomic_add, etc).
822 * 2: For CompSwap only: the second data parameter.
823 */
824 static struct ir3_instruction *
825 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
826 {
827 struct ir3_block *b = ctx->block;
828 struct ir3_instruction *atomic, *src0, *src1;
829 type_t type = TYPE_U32;
830
831 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
832 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
833
834 switch (intr->intrinsic) {
835 case nir_intrinsic_shared_atomic_add:
836 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
837 break;
838 case nir_intrinsic_shared_atomic_imin:
839 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
840 type = TYPE_S32;
841 break;
842 case nir_intrinsic_shared_atomic_umin:
843 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
844 break;
845 case nir_intrinsic_shared_atomic_imax:
846 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
847 type = TYPE_S32;
848 break;
849 case nir_intrinsic_shared_atomic_umax:
850 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
851 break;
852 case nir_intrinsic_shared_atomic_and:
853 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
854 break;
855 case nir_intrinsic_shared_atomic_or:
856 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
857 break;
858 case nir_intrinsic_shared_atomic_xor:
859 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
860 break;
861 case nir_intrinsic_shared_atomic_exchange:
862 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
863 break;
864 case nir_intrinsic_shared_atomic_comp_swap:
865 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
866 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
867 ir3_get_src(ctx, &intr->src[2])[0],
868 src1,
869 }, 2);
870 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
871 break;
872 default:
873 unreachable("boo");
874 }
875
876 atomic->cat6.iim_val = 1;
877 atomic->cat6.d = 1;
878 atomic->cat6.type = type;
879 atomic->barrier_class = IR3_BARRIER_SHARED_W;
880 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
881
882 /* even if nothing consume the result, we can't DCE the instruction: */
883 array_insert(b, b->keeps, atomic);
884
885 return atomic;
886 }
887
888 /* TODO handle actual indirect/dynamic case.. which is going to be weird
889 * to handle with the image_mapping table..
890 */
891 static struct ir3_instruction *
892 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
893 {
894 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
895 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
896 struct ir3_instruction *texture, *sampler;
897
898 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
899 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
900
901 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
902 sampler,
903 texture,
904 }, 2);
905 }
906
907 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
908 static void
909 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
910 struct ir3_instruction **dst)
911 {
912 struct ir3_block *b = ctx->block;
913 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
914 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
915 struct ir3_instruction *sam;
916 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
917 struct ir3_instruction *coords[4];
918 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
919 type_t type = ir3_get_image_type(var);
920
921 /* hmm, this seems a bit odd, but it is what blob does and (at least
922 * a5xx) just faults on bogus addresses otherwise:
923 */
924 if (flags & IR3_INSTR_3D) {
925 flags &= ~IR3_INSTR_3D;
926 flags |= IR3_INSTR_A;
927 }
928
929 for (unsigned i = 0; i < ncoords; i++)
930 coords[i] = src0[i];
931
932 if (ncoords == 1)
933 coords[ncoords++] = create_immed(b, 0);
934
935 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
936 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
937
938 sam->barrier_class = IR3_BARRIER_IMAGE_R;
939 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
940
941 ir3_split_dest(b, dst, sam, 0, 4);
942 }
943
944 static void
945 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
946 struct ir3_instruction **dst)
947 {
948 struct ir3_block *b = ctx->block;
949 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
950 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
951 struct ir3_instruction *sam, *lod;
952 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
953
954 lod = create_immed(b, 0);
955 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
956 samp_tex, lod, NULL);
957
958 /* Array size actually ends up in .w rather than .z. This doesn't
959 * matter for miplevel 0, but for higher mips the value in z is
960 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
961 * returned, which means that we have to add 1 to it for arrays for
962 * a3xx.
963 *
964 * Note use a temporary dst and then copy, since the size of the dst
965 * array that is passed in is based on nir's understanding of the
966 * result size, not the hardware's
967 */
968 struct ir3_instruction *tmp[4];
969
970 ir3_split_dest(b, tmp, sam, 0, 4);
971
972 /* get_size instruction returns size in bytes instead of texels
973 * for imageBuffer, so we need to divide it by the pixel size
974 * of the image format.
975 *
976 * TODO: This is at least true on a5xx. Check other gens.
977 */
978 enum glsl_sampler_dim dim =
979 glsl_get_sampler_dim(glsl_without_array(var->type));
980 if (dim == GLSL_SAMPLER_DIM_BUF) {
981 /* Since all the possible values the divisor can take are
982 * power-of-two (4, 8, or 16), the division is implemented
983 * as a shift-right.
984 * During shader setup, the log2 of the image format's
985 * bytes-per-pixel should have been emitted in 2nd slot of
986 * image_dims. See ir3_shader::emit_image_dims().
987 */
988 unsigned cb = regid(ctx->so->constbase.image_dims, 0) +
989 ctx->so->const_layout.image_dims.off[var->data.driver_location];
990 struct ir3_instruction *aux = create_uniform(b, cb + 1);
991
992 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
993 }
994
995 for (unsigned i = 0; i < ncoords; i++)
996 dst[i] = tmp[i];
997
998 if (flags & IR3_INSTR_A) {
999 if (ctx->compiler->levels_add_one) {
1000 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1001 } else {
1002 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1003 }
1004 }
1005 }
1006
1007 static void
1008 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1009 {
1010 struct ir3_block *b = ctx->block;
1011 struct ir3_instruction *barrier;
1012
1013 switch (intr->intrinsic) {
1014 case nir_intrinsic_barrier:
1015 barrier = ir3_BAR(b);
1016 barrier->cat7.g = true;
1017 barrier->cat7.l = true;
1018 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1019 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1020 break;
1021 case nir_intrinsic_memory_barrier:
1022 barrier = ir3_FENCE(b);
1023 barrier->cat7.g = true;
1024 barrier->cat7.r = true;
1025 barrier->cat7.w = true;
1026 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1027 IR3_BARRIER_BUFFER_W;
1028 barrier->barrier_conflict =
1029 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1030 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1031 break;
1032 case nir_intrinsic_memory_barrier_atomic_counter:
1033 case nir_intrinsic_memory_barrier_buffer:
1034 barrier = ir3_FENCE(b);
1035 barrier->cat7.g = true;
1036 barrier->cat7.r = true;
1037 barrier->cat7.w = true;
1038 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1039 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1040 IR3_BARRIER_BUFFER_W;
1041 break;
1042 case nir_intrinsic_memory_barrier_image:
1043 // TODO double check if this should have .g set
1044 barrier = ir3_FENCE(b);
1045 barrier->cat7.g = true;
1046 barrier->cat7.r = true;
1047 barrier->cat7.w = true;
1048 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1049 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1050 IR3_BARRIER_IMAGE_W;
1051 break;
1052 case nir_intrinsic_memory_barrier_shared:
1053 barrier = ir3_FENCE(b);
1054 barrier->cat7.g = true;
1055 barrier->cat7.l = true;
1056 barrier->cat7.r = true;
1057 barrier->cat7.w = true;
1058 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1059 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1060 IR3_BARRIER_SHARED_W;
1061 break;
1062 case nir_intrinsic_group_memory_barrier:
1063 barrier = ir3_FENCE(b);
1064 barrier->cat7.g = true;
1065 barrier->cat7.l = true;
1066 barrier->cat7.r = true;
1067 barrier->cat7.w = true;
1068 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1069 IR3_BARRIER_IMAGE_W |
1070 IR3_BARRIER_BUFFER_W;
1071 barrier->barrier_conflict =
1072 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1073 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1074 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1075 break;
1076 default:
1077 unreachable("boo");
1078 }
1079
1080 /* make sure barrier doesn't get DCE'd */
1081 array_insert(b, b->keeps, barrier);
1082 }
1083
1084 static void add_sysval_input_compmask(struct ir3_context *ctx,
1085 gl_system_value slot, unsigned compmask,
1086 struct ir3_instruction *instr)
1087 {
1088 struct ir3_shader_variant *so = ctx->so;
1089 unsigned r = regid(so->inputs_count, 0);
1090 unsigned n = so->inputs_count++;
1091
1092 so->inputs[n].sysval = true;
1093 so->inputs[n].slot = slot;
1094 so->inputs[n].compmask = compmask;
1095 so->inputs[n].regid = r;
1096 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1097 so->total_in++;
1098
1099 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1100 ctx->ir->inputs[r] = instr;
1101 }
1102
1103 static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1104 struct ir3_instruction *instr)
1105 {
1106 add_sysval_input_compmask(ctx, slot, 0x1, instr);
1107 }
1108
1109 static void
1110 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1111 {
1112 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1113 struct ir3_instruction **dst;
1114 struct ir3_instruction * const *src;
1115 struct ir3_block *b = ctx->block;
1116 nir_const_value *const_offset;
1117 int idx, comp;
1118
1119 if (info->has_dest) {
1120 unsigned n = nir_intrinsic_dest_components(intr);
1121 dst = ir3_get_dst(ctx, &intr->dest, n);
1122 } else {
1123 dst = NULL;
1124 }
1125
1126 switch (intr->intrinsic) {
1127 case nir_intrinsic_load_uniform:
1128 idx = nir_intrinsic_base(intr);
1129 const_offset = nir_src_as_const_value(intr->src[0]);
1130 if (const_offset) {
1131 idx += const_offset->u32[0];
1132 for (int i = 0; i < intr->num_components; i++) {
1133 unsigned n = idx * 4 + i;
1134 dst[i] = create_uniform(b, n);
1135 }
1136 } else {
1137 src = ir3_get_src(ctx, &intr->src[0]);
1138 for (int i = 0; i < intr->num_components; i++) {
1139 int n = idx * 4 + i;
1140 dst[i] = create_uniform_indirect(b, n,
1141 ir3_get_addr(ctx, src[0], 4));
1142 }
1143 /* NOTE: if relative addressing is used, we set
1144 * constlen in the compiler (to worst-case value)
1145 * since we don't know in the assembler what the max
1146 * addr reg value can be:
1147 */
1148 ctx->so->constlen = ctx->s->num_uniforms;
1149 }
1150 break;
1151 case nir_intrinsic_load_ubo:
1152 emit_intrinsic_load_ubo(ctx, intr, dst);
1153 break;
1154 case nir_intrinsic_load_input:
1155 idx = nir_intrinsic_base(intr);
1156 comp = nir_intrinsic_component(intr);
1157 const_offset = nir_src_as_const_value(intr->src[0]);
1158 if (const_offset) {
1159 idx += const_offset->u32[0];
1160 for (int i = 0; i < intr->num_components; i++) {
1161 unsigned n = idx * 4 + i + comp;
1162 dst[i] = ctx->ir->inputs[n];
1163 }
1164 } else {
1165 src = ir3_get_src(ctx, &intr->src[0]);
1166 struct ir3_instruction *collect =
1167 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1168 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1169 for (int i = 0; i < intr->num_components; i++) {
1170 unsigned n = idx * 4 + i + comp;
1171 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1172 n, addr, collect);
1173 }
1174 }
1175 break;
1176 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1177 * pass and replaced by an ir3-specifc version that adds the
1178 * dword-offset in the last source.
1179 */
1180 case nir_intrinsic_load_ssbo_ir3:
1181 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1182 break;
1183 case nir_intrinsic_store_ssbo_ir3:
1184 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1185 break;
1186 case nir_intrinsic_get_buffer_size:
1187 emit_intrinsic_ssbo_size(ctx, intr, dst);
1188 break;
1189 case nir_intrinsic_ssbo_atomic_add_ir3:
1190 case nir_intrinsic_ssbo_atomic_imin_ir3:
1191 case nir_intrinsic_ssbo_atomic_umin_ir3:
1192 case nir_intrinsic_ssbo_atomic_imax_ir3:
1193 case nir_intrinsic_ssbo_atomic_umax_ir3:
1194 case nir_intrinsic_ssbo_atomic_and_ir3:
1195 case nir_intrinsic_ssbo_atomic_or_ir3:
1196 case nir_intrinsic_ssbo_atomic_xor_ir3:
1197 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1198 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1199 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1200 break;
1201 case nir_intrinsic_load_shared:
1202 emit_intrinsic_load_shared(ctx, intr, dst);
1203 break;
1204 case nir_intrinsic_store_shared:
1205 emit_intrinsic_store_shared(ctx, intr);
1206 break;
1207 case nir_intrinsic_shared_atomic_add:
1208 case nir_intrinsic_shared_atomic_imin:
1209 case nir_intrinsic_shared_atomic_umin:
1210 case nir_intrinsic_shared_atomic_imax:
1211 case nir_intrinsic_shared_atomic_umax:
1212 case nir_intrinsic_shared_atomic_and:
1213 case nir_intrinsic_shared_atomic_or:
1214 case nir_intrinsic_shared_atomic_xor:
1215 case nir_intrinsic_shared_atomic_exchange:
1216 case nir_intrinsic_shared_atomic_comp_swap:
1217 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1218 break;
1219 case nir_intrinsic_image_deref_load:
1220 emit_intrinsic_load_image(ctx, intr, dst);
1221 break;
1222 case nir_intrinsic_image_deref_store:
1223 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1224 break;
1225 case nir_intrinsic_image_deref_size:
1226 emit_intrinsic_image_size(ctx, intr, dst);
1227 break;
1228 case nir_intrinsic_image_deref_atomic_add:
1229 case nir_intrinsic_image_deref_atomic_min:
1230 case nir_intrinsic_image_deref_atomic_max:
1231 case nir_intrinsic_image_deref_atomic_and:
1232 case nir_intrinsic_image_deref_atomic_or:
1233 case nir_intrinsic_image_deref_atomic_xor:
1234 case nir_intrinsic_image_deref_atomic_exchange:
1235 case nir_intrinsic_image_deref_atomic_comp_swap:
1236 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1237 break;
1238 case nir_intrinsic_barrier:
1239 case nir_intrinsic_memory_barrier:
1240 case nir_intrinsic_group_memory_barrier:
1241 case nir_intrinsic_memory_barrier_atomic_counter:
1242 case nir_intrinsic_memory_barrier_buffer:
1243 case nir_intrinsic_memory_barrier_image:
1244 case nir_intrinsic_memory_barrier_shared:
1245 emit_intrinsic_barrier(ctx, intr);
1246 /* note that blk ptr no longer valid, make that obvious: */
1247 b = NULL;
1248 break;
1249 case nir_intrinsic_store_output:
1250 idx = nir_intrinsic_base(intr);
1251 comp = nir_intrinsic_component(intr);
1252 const_offset = nir_src_as_const_value(intr->src[1]);
1253 compile_assert(ctx, const_offset != NULL);
1254 idx += const_offset->u32[0];
1255
1256 src = ir3_get_src(ctx, &intr->src[0]);
1257 for (int i = 0; i < intr->num_components; i++) {
1258 unsigned n = idx * 4 + i + comp;
1259 ctx->ir->outputs[n] = src[i];
1260 }
1261 break;
1262 case nir_intrinsic_load_base_vertex:
1263 case nir_intrinsic_load_first_vertex:
1264 if (!ctx->basevertex) {
1265 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1266 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex);
1267 }
1268 dst[0] = ctx->basevertex;
1269 break;
1270 case nir_intrinsic_load_vertex_id_zero_base:
1271 case nir_intrinsic_load_vertex_id:
1272 if (!ctx->vertex_id) {
1273 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1274 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1275 ctx->vertex_id = create_input(ctx, 0);
1276 add_sysval_input(ctx, sv, ctx->vertex_id);
1277 }
1278 dst[0] = ctx->vertex_id;
1279 break;
1280 case nir_intrinsic_load_instance_id:
1281 if (!ctx->instance_id) {
1282 ctx->instance_id = create_input(ctx, 0);
1283 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID,
1284 ctx->instance_id);
1285 }
1286 dst[0] = ctx->instance_id;
1287 break;
1288 case nir_intrinsic_load_sample_id:
1289 case nir_intrinsic_load_sample_id_no_per_sample:
1290 if (!ctx->samp_id) {
1291 ctx->samp_id = create_input(ctx, 0);
1292 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1293 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID,
1294 ctx->samp_id);
1295 }
1296 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1297 break;
1298 case nir_intrinsic_load_sample_mask_in:
1299 if (!ctx->samp_mask_in) {
1300 ctx->samp_mask_in = create_input(ctx, 0);
1301 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN,
1302 ctx->samp_mask_in);
1303 }
1304 dst[0] = ctx->samp_mask_in;
1305 break;
1306 case nir_intrinsic_load_user_clip_plane:
1307 idx = nir_intrinsic_ucp_id(intr);
1308 for (int i = 0; i < intr->num_components; i++) {
1309 unsigned n = idx * 4 + i;
1310 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1311 }
1312 break;
1313 case nir_intrinsic_load_front_face:
1314 if (!ctx->frag_face) {
1315 ctx->so->frag_face = true;
1316 ctx->frag_face = create_input(ctx, 0);
1317 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face);
1318 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1319 }
1320 /* for fragface, we get -1 for back and 0 for front. However this is
1321 * the inverse of what nir expects (where ~0 is true).
1322 */
1323 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1324 dst[0] = ir3_NOT_B(b, dst[0], 0);
1325 break;
1326 case nir_intrinsic_load_local_invocation_id:
1327 if (!ctx->local_invocation_id) {
1328 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7);
1329 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID,
1330 0x7, ctx->local_invocation_id);
1331 }
1332 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1333 break;
1334 case nir_intrinsic_load_work_group_id:
1335 if (!ctx->work_group_id) {
1336 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7);
1337 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID,
1338 0x7, ctx->work_group_id);
1339 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1340 }
1341 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1342 break;
1343 case nir_intrinsic_load_num_work_groups:
1344 for (int i = 0; i < intr->num_components; i++) {
1345 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1346 }
1347 break;
1348 case nir_intrinsic_load_local_group_size:
1349 for (int i = 0; i < intr->num_components; i++) {
1350 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1351 }
1352 break;
1353 case nir_intrinsic_discard_if:
1354 case nir_intrinsic_discard: {
1355 struct ir3_instruction *cond, *kill;
1356
1357 if (intr->intrinsic == nir_intrinsic_discard_if) {
1358 /* conditional discard: */
1359 src = ir3_get_src(ctx, &intr->src[0]);
1360 cond = ir3_b2n(b, src[0]);
1361 } else {
1362 /* unconditional discard: */
1363 cond = create_immed(b, 1);
1364 }
1365
1366 /* NOTE: only cmps.*.* can write p0.x: */
1367 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1368 cond->cat2.condition = IR3_COND_NE;
1369
1370 /* condition always goes in predicate register: */
1371 cond->regs[0]->num = regid(REG_P0, 0);
1372
1373 kill = ir3_KILL(b, cond, 0);
1374 array_insert(ctx->ir, ctx->ir->predicates, kill);
1375
1376 array_insert(b, b->keeps, kill);
1377 ctx->so->has_kill = true;
1378
1379 break;
1380 }
1381 default:
1382 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1383 nir_intrinsic_infos[intr->intrinsic].name);
1384 break;
1385 }
1386
1387 if (info->has_dest)
1388 ir3_put_dst(ctx, &intr->dest);
1389 }
1390
1391 static void
1392 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1393 {
1394 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1395 instr->def.num_components);
1396 type_t type = (instr->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1397
1398 for (int i = 0; i < instr->def.num_components; i++)
1399 dst[i] = create_immed_typed(ctx->block, instr->value.u32[i], type);
1400 }
1401
1402 static void
1403 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1404 {
1405 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1406 undef->def.num_components);
1407 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1408
1409 /* backend doesn't want undefined instructions, so just plug
1410 * in 0.0..
1411 */
1412 for (int i = 0; i < undef->def.num_components; i++)
1413 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1414 }
1415
1416 /*
1417 * texture fetch/sample instructions:
1418 */
1419
1420 static void
1421 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1422 {
1423 unsigned coords, flags = 0;
1424
1425 /* note: would use tex->coord_components.. except txs.. also,
1426 * since array index goes after shadow ref, we don't want to
1427 * count it:
1428 */
1429 switch (tex->sampler_dim) {
1430 case GLSL_SAMPLER_DIM_1D:
1431 case GLSL_SAMPLER_DIM_BUF:
1432 coords = 1;
1433 break;
1434 case GLSL_SAMPLER_DIM_2D:
1435 case GLSL_SAMPLER_DIM_RECT:
1436 case GLSL_SAMPLER_DIM_EXTERNAL:
1437 case GLSL_SAMPLER_DIM_MS:
1438 coords = 2;
1439 break;
1440 case GLSL_SAMPLER_DIM_3D:
1441 case GLSL_SAMPLER_DIM_CUBE:
1442 coords = 3;
1443 flags |= IR3_INSTR_3D;
1444 break;
1445 default:
1446 unreachable("bad sampler_dim");
1447 }
1448
1449 if (tex->is_shadow && tex->op != nir_texop_lod)
1450 flags |= IR3_INSTR_S;
1451
1452 if (tex->is_array && tex->op != nir_texop_lod)
1453 flags |= IR3_INSTR_A;
1454
1455 *flagsp = flags;
1456 *coordsp = coords;
1457 }
1458
1459 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1460 * or immediate (in which case it will get lowered later to a non .s2en
1461 * version of the tex instruction which encode tex/samp as immediates:
1462 */
1463 static struct ir3_instruction *
1464 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1465 {
1466 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1467 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1468 struct ir3_instruction *texture, *sampler;
1469
1470 if (texture_idx >= 0) {
1471 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1472 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1473 } else {
1474 /* TODO what to do for dynamic case? I guess we only need the
1475 * max index for astc srgb workaround so maybe not a problem
1476 * to worry about if we don't enable indirect samplers for
1477 * a4xx?
1478 */
1479 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1480 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1481 }
1482
1483 if (sampler_idx >= 0) {
1484 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1485 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1486 } else {
1487 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1488 }
1489
1490 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1491 sampler,
1492 texture,
1493 }, 2);
1494 }
1495
1496 static void
1497 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1498 {
1499 struct ir3_block *b = ctx->block;
1500 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1501 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1502 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1503 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1504 unsigned i, coords, flags, ncomp;
1505 unsigned nsrc0 = 0, nsrc1 = 0;
1506 type_t type;
1507 opc_t opc = 0;
1508
1509 ncomp = nir_dest_num_components(tex->dest);
1510
1511 coord = off = ddx = ddy = NULL;
1512 lod = proj = compare = sample_index = NULL;
1513
1514 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1515
1516 for (unsigned i = 0; i < tex->num_srcs; i++) {
1517 switch (tex->src[i].src_type) {
1518 case nir_tex_src_coord:
1519 coord = ir3_get_src(ctx, &tex->src[i].src);
1520 break;
1521 case nir_tex_src_bias:
1522 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1523 has_bias = true;
1524 break;
1525 case nir_tex_src_lod:
1526 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1527 has_lod = true;
1528 break;
1529 case nir_tex_src_comparator: /* shadow comparator */
1530 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1531 break;
1532 case nir_tex_src_projector:
1533 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1534 has_proj = true;
1535 break;
1536 case nir_tex_src_offset:
1537 off = ir3_get_src(ctx, &tex->src[i].src);
1538 has_off = true;
1539 break;
1540 case nir_tex_src_ddx:
1541 ddx = ir3_get_src(ctx, &tex->src[i].src);
1542 break;
1543 case nir_tex_src_ddy:
1544 ddy = ir3_get_src(ctx, &tex->src[i].src);
1545 break;
1546 case nir_tex_src_ms_index:
1547 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1548 break;
1549 case nir_tex_src_texture_offset:
1550 case nir_tex_src_sampler_offset:
1551 /* handled in get_tex_samp_src() */
1552 break;
1553 default:
1554 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1555 tex->src[i].src_type);
1556 return;
1557 }
1558 }
1559
1560 switch (tex->op) {
1561 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1562 case nir_texop_txb: opc = OPC_SAMB; break;
1563 case nir_texop_txl: opc = OPC_SAML; break;
1564 case nir_texop_txd: opc = OPC_SAMGQ; break;
1565 case nir_texop_txf: opc = OPC_ISAML; break;
1566 case nir_texop_lod: opc = OPC_GETLOD; break;
1567 case nir_texop_tg4:
1568 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1569 * what blob does, seems gather is broken?), and a3xx did
1570 * not support it (but probably could also emulate).
1571 */
1572 switch (tex->component) {
1573 case 0: opc = OPC_GATHER4R; break;
1574 case 1: opc = OPC_GATHER4G; break;
1575 case 2: opc = OPC_GATHER4B; break;
1576 case 3: opc = OPC_GATHER4A; break;
1577 }
1578 break;
1579 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
1580 case nir_texop_txs:
1581 case nir_texop_query_levels:
1582 case nir_texop_texture_samples:
1583 case nir_texop_samples_identical:
1584 case nir_texop_txf_ms_mcs:
1585 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1586 return;
1587 }
1588
1589 tex_info(tex, &flags, &coords);
1590
1591 /*
1592 * lay out the first argument in the proper order:
1593 * - actual coordinates first
1594 * - shadow reference
1595 * - array index
1596 * - projection w
1597 * - starting at offset 4, dpdx.xy, dpdy.xy
1598 *
1599 * bias/lod go into the second arg
1600 */
1601
1602 /* insert tex coords: */
1603 for (i = 0; i < coords; i++)
1604 src0[i] = coord[i];
1605
1606 nsrc0 = i;
1607
1608 /* scale up integer coords for TXF based on the LOD */
1609 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
1610 assert(has_lod);
1611 for (i = 0; i < coords; i++)
1612 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
1613 }
1614
1615 if (coords == 1) {
1616 /* hw doesn't do 1d, so we treat it as 2d with
1617 * height of 1, and patch up the y coord.
1618 */
1619 if (is_isam(opc)) {
1620 src0[nsrc0++] = create_immed(b, 0);
1621 } else {
1622 src0[nsrc0++] = create_immed(b, fui(0.5));
1623 }
1624 }
1625
1626 if (tex->is_shadow && tex->op != nir_texop_lod)
1627 src0[nsrc0++] = compare;
1628
1629 if (tex->is_array && tex->op != nir_texop_lod) {
1630 struct ir3_instruction *idx = coord[coords];
1631
1632 /* the array coord for cube arrays needs 0.5 added to it */
1633 if (ctx->compiler->array_index_add_half && !is_isam(opc))
1634 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
1635
1636 src0[nsrc0++] = idx;
1637 }
1638
1639 if (has_proj) {
1640 src0[nsrc0++] = proj;
1641 flags |= IR3_INSTR_P;
1642 }
1643
1644 /* pad to 4, then ddx/ddy: */
1645 if (tex->op == nir_texop_txd) {
1646 while (nsrc0 < 4)
1647 src0[nsrc0++] = create_immed(b, fui(0.0));
1648 for (i = 0; i < coords; i++)
1649 src0[nsrc0++] = ddx[i];
1650 if (coords < 2)
1651 src0[nsrc0++] = create_immed(b, fui(0.0));
1652 for (i = 0; i < coords; i++)
1653 src0[nsrc0++] = ddy[i];
1654 if (coords < 2)
1655 src0[nsrc0++] = create_immed(b, fui(0.0));
1656 }
1657
1658 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1659 * with scaled x coord according to requested sample:
1660 */
1661 if (tex->op == nir_texop_txf_ms) {
1662 if (ctx->compiler->txf_ms_with_isaml) {
1663 /* the samples are laid out in x dimension as
1664 * 0 1 2 3
1665 * x_ms = (x << ms) + sample_index;
1666 */
1667 struct ir3_instruction *ms;
1668 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
1669
1670 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
1671 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
1672
1673 opc = OPC_ISAML;
1674 } else {
1675 src0[nsrc0++] = sample_index;
1676 }
1677 }
1678
1679 /*
1680 * second argument (if applicable):
1681 * - offsets
1682 * - lod
1683 * - bias
1684 */
1685 if (has_off | has_lod | has_bias) {
1686 if (has_off) {
1687 unsigned off_coords = coords;
1688 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
1689 off_coords--;
1690 for (i = 0; i < off_coords; i++)
1691 src1[nsrc1++] = off[i];
1692 if (off_coords < 2)
1693 src1[nsrc1++] = create_immed(b, fui(0.0));
1694 flags |= IR3_INSTR_O;
1695 }
1696
1697 if (has_lod | has_bias)
1698 src1[nsrc1++] = lod;
1699 }
1700
1701 switch (tex->dest_type) {
1702 case nir_type_invalid:
1703 case nir_type_float:
1704 type = TYPE_F32;
1705 break;
1706 case nir_type_int:
1707 type = TYPE_S32;
1708 break;
1709 case nir_type_uint:
1710 case nir_type_bool:
1711 type = TYPE_U32;
1712 break;
1713 default:
1714 unreachable("bad dest_type");
1715 }
1716
1717 if (opc == OPC_GETLOD)
1718 type = TYPE_U32;
1719
1720 struct ir3_instruction *samp_tex = get_tex_samp_tex_src(ctx, tex);
1721 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
1722 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
1723
1724 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
1725 samp_tex, col0, col1);
1726
1727 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
1728 /* only need first 3 components: */
1729 sam->regs[0]->wrmask = 0x7;
1730 ir3_split_dest(b, dst, sam, 0, 3);
1731
1732 /* we need to sample the alpha separately with a non-ASTC
1733 * texture state:
1734 */
1735 sam = ir3_SAM(b, opc, type, 0b1000, flags,
1736 samp_tex, col0, col1);
1737
1738 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
1739
1740 /* fixup .w component: */
1741 ir3_split_dest(b, &dst[3], sam, 3, 1);
1742 } else {
1743 /* normal (non-workaround) case: */
1744 ir3_split_dest(b, dst, sam, 0, ncomp);
1745 }
1746
1747 /* GETLOD returns results in 4.8 fixed point */
1748 if (opc == OPC_GETLOD) {
1749 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
1750
1751 compile_assert(ctx, tex->dest_type == nir_type_float);
1752 for (i = 0; i < 2; i++) {
1753 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_U32, TYPE_F32), 0,
1754 factor, 0);
1755 }
1756 }
1757
1758 ir3_put_dst(ctx, &tex->dest);
1759 }
1760
1761 static void
1762 emit_tex_query_levels(struct ir3_context *ctx, nir_tex_instr *tex)
1763 {
1764 struct ir3_block *b = ctx->block;
1765 struct ir3_instruction **dst, *sam;
1766
1767 dst = ir3_get_dst(ctx, &tex->dest, 1);
1768
1769 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 0b0100, 0,
1770 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
1771
1772 /* even though there is only one component, since it ends
1773 * up in .z rather than .x, we need a split_dest()
1774 */
1775 ir3_split_dest(b, dst, sam, 0, 3);
1776
1777 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1778 * the value in TEX_CONST_0 is zero-based.
1779 */
1780 if (ctx->compiler->levels_add_one)
1781 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
1782
1783 ir3_put_dst(ctx, &tex->dest);
1784 }
1785
1786 static void
1787 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
1788 {
1789 struct ir3_block *b = ctx->block;
1790 struct ir3_instruction **dst, *sam;
1791 struct ir3_instruction *lod;
1792 unsigned flags, coords;
1793
1794 tex_info(tex, &flags, &coords);
1795
1796 /* Actually we want the number of dimensions, not coordinates. This
1797 * distinction only matters for cubes.
1798 */
1799 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
1800 coords = 2;
1801
1802 dst = ir3_get_dst(ctx, &tex->dest, 4);
1803
1804 compile_assert(ctx, tex->num_srcs == 1);
1805 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
1806
1807 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
1808
1809 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
1810 get_tex_samp_tex_src(ctx, tex), lod, NULL);
1811
1812 ir3_split_dest(b, dst, sam, 0, 4);
1813
1814 /* Array size actually ends up in .w rather than .z. This doesn't
1815 * matter for miplevel 0, but for higher mips the value in z is
1816 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1817 * returned, which means that we have to add 1 to it for arrays.
1818 */
1819 if (tex->is_array) {
1820 if (ctx->compiler->levels_add_one) {
1821 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
1822 } else {
1823 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
1824 }
1825 }
1826
1827 ir3_put_dst(ctx, &tex->dest);
1828 }
1829
1830 static void
1831 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
1832 {
1833 switch (jump->type) {
1834 case nir_jump_break:
1835 case nir_jump_continue:
1836 case nir_jump_return:
1837 /* I *think* we can simply just ignore this, and use the
1838 * successor block link to figure out where we need to
1839 * jump to for break/continue
1840 */
1841 break;
1842 default:
1843 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
1844 break;
1845 }
1846 }
1847
1848 static void
1849 emit_instr(struct ir3_context *ctx, nir_instr *instr)
1850 {
1851 switch (instr->type) {
1852 case nir_instr_type_alu:
1853 emit_alu(ctx, nir_instr_as_alu(instr));
1854 break;
1855 case nir_instr_type_deref:
1856 /* ignored, handled as part of the intrinsic they are src to */
1857 break;
1858 case nir_instr_type_intrinsic:
1859 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1860 break;
1861 case nir_instr_type_load_const:
1862 emit_load_const(ctx, nir_instr_as_load_const(instr));
1863 break;
1864 case nir_instr_type_ssa_undef:
1865 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
1866 break;
1867 case nir_instr_type_tex: {
1868 nir_tex_instr *tex = nir_instr_as_tex(instr);
1869 /* couple tex instructions get special-cased:
1870 */
1871 switch (tex->op) {
1872 case nir_texop_txs:
1873 emit_tex_txs(ctx, tex);
1874 break;
1875 case nir_texop_query_levels:
1876 emit_tex_query_levels(ctx, tex);
1877 break;
1878 default:
1879 emit_tex(ctx, tex);
1880 break;
1881 }
1882 break;
1883 }
1884 case nir_instr_type_jump:
1885 emit_jump(ctx, nir_instr_as_jump(instr));
1886 break;
1887 case nir_instr_type_phi:
1888 /* we have converted phi webs to regs in NIR by now */
1889 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
1890 break;
1891 case nir_instr_type_call:
1892 case nir_instr_type_parallel_copy:
1893 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
1894 break;
1895 }
1896 }
1897
1898 static struct ir3_block *
1899 get_block(struct ir3_context *ctx, const nir_block *nblock)
1900 {
1901 struct ir3_block *block;
1902 struct hash_entry *hentry;
1903 unsigned i;
1904
1905 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
1906 if (hentry)
1907 return hentry->data;
1908
1909 block = ir3_block_create(ctx->ir);
1910 block->nblock = nblock;
1911 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
1912
1913 block->predecessors_count = nblock->predecessors->entries;
1914 block->predecessors = ralloc_array_size(block,
1915 sizeof(block->predecessors[0]), block->predecessors_count);
1916 i = 0;
1917 set_foreach(nblock->predecessors, sentry) {
1918 block->predecessors[i++] = get_block(ctx, sentry->key);
1919 }
1920
1921 return block;
1922 }
1923
1924 static void
1925 emit_block(struct ir3_context *ctx, nir_block *nblock)
1926 {
1927 struct ir3_block *block = get_block(ctx, nblock);
1928
1929 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
1930 if (nblock->successors[i]) {
1931 block->successors[i] =
1932 get_block(ctx, nblock->successors[i]);
1933 }
1934 }
1935
1936 ctx->block = block;
1937 list_addtail(&block->node, &ctx->ir->block_list);
1938
1939 /* re-emit addr register in each block if needed: */
1940 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
1941 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
1942 ctx->addr_ht[i] = NULL;
1943 }
1944
1945 nir_foreach_instr(instr, nblock) {
1946 ctx->cur_instr = instr;
1947 emit_instr(ctx, instr);
1948 ctx->cur_instr = NULL;
1949 if (ctx->error)
1950 return;
1951 }
1952 }
1953
1954 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
1955
1956 static void
1957 emit_if(struct ir3_context *ctx, nir_if *nif)
1958 {
1959 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
1960
1961 ctx->block->condition =
1962 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
1963
1964 emit_cf_list(ctx, &nif->then_list);
1965 emit_cf_list(ctx, &nif->else_list);
1966 }
1967
1968 static void
1969 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
1970 {
1971 emit_cf_list(ctx, &nloop->body);
1972 }
1973
1974 static void
1975 stack_push(struct ir3_context *ctx)
1976 {
1977 ctx->stack++;
1978 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
1979 }
1980
1981 static void
1982 stack_pop(struct ir3_context *ctx)
1983 {
1984 compile_assert(ctx, ctx->stack > 0);
1985 ctx->stack--;
1986 }
1987
1988 static void
1989 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
1990 {
1991 foreach_list_typed(nir_cf_node, node, node, list) {
1992 switch (node->type) {
1993 case nir_cf_node_block:
1994 emit_block(ctx, nir_cf_node_as_block(node));
1995 break;
1996 case nir_cf_node_if:
1997 stack_push(ctx);
1998 emit_if(ctx, nir_cf_node_as_if(node));
1999 stack_pop(ctx);
2000 break;
2001 case nir_cf_node_loop:
2002 stack_push(ctx);
2003 emit_loop(ctx, nir_cf_node_as_loop(node));
2004 stack_pop(ctx);
2005 break;
2006 case nir_cf_node_function:
2007 ir3_context_error(ctx, "TODO\n");
2008 break;
2009 }
2010 }
2011 }
2012
2013 /* emit stream-out code. At this point, the current block is the original
2014 * (nir) end block, and nir ensures that all flow control paths terminate
2015 * into the end block. We re-purpose the original end block to generate
2016 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2017 * block holding stream-out write instructions, followed by the new end
2018 * block:
2019 *
2020 * blockOrigEnd {
2021 * p0.x = (vtxcnt < maxvtxcnt)
2022 * // succs: blockStreamOut, blockNewEnd
2023 * }
2024 * blockStreamOut {
2025 * ... stream-out instructions ...
2026 * // succs: blockNewEnd
2027 * }
2028 * blockNewEnd {
2029 * }
2030 */
2031 static void
2032 emit_stream_out(struct ir3_context *ctx)
2033 {
2034 struct ir3_shader_variant *v = ctx->so;
2035 struct ir3 *ir = ctx->ir;
2036 struct ir3_stream_output_info *strmout =
2037 &ctx->so->shader->stream_output;
2038 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2039 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2040 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2041
2042 /* create vtxcnt input in input block at top of shader,
2043 * so that it is seen as live over the entire duration
2044 * of the shader:
2045 */
2046 vtxcnt = create_input(ctx, 0);
2047 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt);
2048
2049 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2050
2051 /* at this point, we are at the original 'end' block,
2052 * re-purpose this block to stream-out condition, then
2053 * append stream-out block and new-end block
2054 */
2055 orig_end_block = ctx->block;
2056
2057 // TODO these blocks need to update predecessors..
2058 // maybe w/ store_global intrinsic, we could do this
2059 // stuff in nir->nir pass
2060
2061 stream_out_block = ir3_block_create(ir);
2062 list_addtail(&stream_out_block->node, &ir->block_list);
2063
2064 new_end_block = ir3_block_create(ir);
2065 list_addtail(&new_end_block->node, &ir->block_list);
2066
2067 orig_end_block->successors[0] = stream_out_block;
2068 orig_end_block->successors[1] = new_end_block;
2069 stream_out_block->successors[0] = new_end_block;
2070
2071 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2072 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2073 cond->regs[0]->num = regid(REG_P0, 0);
2074 cond->cat2.condition = IR3_COND_LT;
2075
2076 /* condition goes on previous block to the conditional,
2077 * since it is used to pick which of the two successor
2078 * paths to take:
2079 */
2080 orig_end_block->condition = cond;
2081
2082 /* switch to stream_out_block to generate the stream-out
2083 * instructions:
2084 */
2085 ctx->block = stream_out_block;
2086
2087 /* Calculate base addresses based on vtxcnt. Instructions
2088 * generated for bases not used in following loop will be
2089 * stripped out in the backend.
2090 */
2091 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2092 unsigned stride = strmout->stride[i];
2093 struct ir3_instruction *base, *off;
2094
2095 base = create_uniform(ctx->block, regid(v->constbase.tfbo, i));
2096
2097 /* 24-bit should be enough: */
2098 off = ir3_MUL_U(ctx->block, vtxcnt, 0,
2099 create_immed(ctx->block, stride * 4), 0);
2100
2101 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2102 }
2103
2104 /* Generate the per-output store instructions: */
2105 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2106 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2107 unsigned c = j + strmout->output[i].start_component;
2108 struct ir3_instruction *base, *out, *stg;
2109
2110 base = bases[strmout->output[i].output_buffer];
2111 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2112
2113 stg = ir3_STG(ctx->block, base, 0, out, 0,
2114 create_immed(ctx->block, 1), 0);
2115 stg->cat6.type = TYPE_U32;
2116 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2117
2118 array_insert(ctx->block, ctx->block->keeps, stg);
2119 }
2120 }
2121
2122 /* and finally switch to the new_end_block: */
2123 ctx->block = new_end_block;
2124 }
2125
2126 static void
2127 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2128 {
2129 nir_metadata_require(impl, nir_metadata_block_index);
2130
2131 compile_assert(ctx, ctx->stack == 0);
2132
2133 emit_cf_list(ctx, &impl->body);
2134 emit_block(ctx, impl->end_block);
2135
2136 compile_assert(ctx, ctx->stack == 0);
2137
2138 /* at this point, we should have a single empty block,
2139 * into which we emit the 'end' instruction.
2140 */
2141 compile_assert(ctx, list_empty(&ctx->block->instr_list));
2142
2143 /* If stream-out (aka transform-feedback) enabled, emit the
2144 * stream-out instructions, followed by a new empty block (into
2145 * which the 'end' instruction lands).
2146 *
2147 * NOTE: it is done in this order, rather than inserting before
2148 * we emit end_block, because NIR guarantees that all blocks
2149 * flow into end_block, and that end_block has no successors.
2150 * So by re-purposing end_block as the first block of stream-
2151 * out, we guarantee that all exit paths flow into the stream-
2152 * out instructions.
2153 */
2154 if ((ctx->compiler->gpu_id < 500) &&
2155 (ctx->so->shader->stream_output.num_outputs > 0) &&
2156 !ctx->so->binning_pass) {
2157 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2158 emit_stream_out(ctx);
2159 }
2160
2161 ir3_END(ctx->block);
2162 }
2163
2164 static struct ir3_instruction *
2165 create_frag_coord(struct ir3_context *ctx, unsigned comp)
2166 {
2167 struct ir3_block *block = ctx->block;
2168 struct ir3_instruction *instr;
2169
2170 if (!ctx->frag_coord) {
2171 ctx->frag_coord = create_input_compmask(ctx, 0, 0xf);
2172 /* defer add_sysval_input() until after all inputs created */
2173 }
2174
2175 ir3_split_dest(block, &instr, ctx->frag_coord, comp, 1);
2176
2177 switch (comp) {
2178 case 0: /* .x */
2179 case 1: /* .y */
2180 /* for frag_coord, we get unsigned values.. we need
2181 * to subtract (integer) 8 and divide by 16 (right-
2182 * shift by 4) then convert to float:
2183 *
2184 * sub.s tmp, src, 8
2185 * shr.b tmp, tmp, 4
2186 * mov.u32f32 dst, tmp
2187 *
2188 */
2189 instr = ir3_SUB_S(block, instr, 0,
2190 create_immed(block, 8), 0);
2191 instr = ir3_SHR_B(block, instr, 0,
2192 create_immed(block, 4), 0);
2193 instr = ir3_COV(block, instr, TYPE_U32, TYPE_F32);
2194
2195 return instr;
2196 case 2: /* .z */
2197 case 3: /* .w */
2198 default:
2199 /* seems that we can use these as-is: */
2200 return instr;
2201 }
2202 }
2203
2204 static void
2205 setup_input(struct ir3_context *ctx, nir_variable *in)
2206 {
2207 struct ir3_shader_variant *so = ctx->so;
2208 unsigned ncomp = glsl_get_components(in->type);
2209 unsigned n = in->data.driver_location;
2210 unsigned frac = in->data.location_frac;
2211 unsigned slot = in->data.location;
2212
2213 /* skip unread inputs, we could end up with (for example), unsplit
2214 * matrix/etc inputs in the case they are not read, so just silently
2215 * skip these.
2216 */
2217 if (ncomp > 4)
2218 return;
2219
2220 so->inputs[n].slot = slot;
2221 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2222 so->inputs_count = MAX2(so->inputs_count, n + 1);
2223 so->inputs[n].interpolate = in->data.interpolation;
2224
2225 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2226 for (int i = 0; i < ncomp; i++) {
2227 struct ir3_instruction *instr = NULL;
2228 unsigned idx = (n * 4) + i + frac;
2229
2230 if (slot == VARYING_SLOT_POS) {
2231 so->inputs[n].bary = false;
2232 so->frag_coord = true;
2233 instr = create_frag_coord(ctx, i);
2234 } else if (slot == VARYING_SLOT_PNTC) {
2235 /* see for example st_nir_fixup_varying_slots().. this is
2236 * maybe a bit mesa/st specific. But we need things to line
2237 * up for this in fdN_program:
2238 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2239 * if (emit->sprite_coord_enable & texmask) {
2240 * ...
2241 * }
2242 */
2243 so->inputs[n].slot = VARYING_SLOT_VAR8;
2244 so->inputs[n].bary = true;
2245 instr = create_frag_input(ctx, false);
2246 } else {
2247 bool use_ldlv = false;
2248
2249 /* detect the special case for front/back colors where
2250 * we need to do flat vs smooth shading depending on
2251 * rast state:
2252 */
2253 if (in->data.interpolation == INTERP_MODE_NONE) {
2254 switch (slot) {
2255 case VARYING_SLOT_COL0:
2256 case VARYING_SLOT_COL1:
2257 case VARYING_SLOT_BFC0:
2258 case VARYING_SLOT_BFC1:
2259 so->inputs[n].rasterflat = true;
2260 break;
2261 default:
2262 break;
2263 }
2264 }
2265
2266 if (ctx->compiler->flat_bypass) {
2267 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2268 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2269 use_ldlv = true;
2270 }
2271
2272 so->inputs[n].bary = true;
2273
2274 instr = create_frag_input(ctx, use_ldlv);
2275 }
2276
2277 compile_assert(ctx, idx < ctx->ir->ninputs);
2278
2279 ctx->ir->inputs[idx] = instr;
2280 }
2281 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2282 for (int i = 0; i < ncomp; i++) {
2283 unsigned idx = (n * 4) + i + frac;
2284 compile_assert(ctx, idx < ctx->ir->ninputs);
2285 ctx->ir->inputs[idx] = create_input(ctx, idx);
2286 }
2287 } else {
2288 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2289 }
2290
2291 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2292 so->total_in += ncomp;
2293 }
2294 }
2295
2296 static void
2297 setup_output(struct ir3_context *ctx, nir_variable *out)
2298 {
2299 struct ir3_shader_variant *so = ctx->so;
2300 unsigned ncomp = glsl_get_components(out->type);
2301 unsigned n = out->data.driver_location;
2302 unsigned frac = out->data.location_frac;
2303 unsigned slot = out->data.location;
2304 unsigned comp = 0;
2305
2306 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2307 switch (slot) {
2308 case FRAG_RESULT_DEPTH:
2309 comp = 2; /* tgsi will write to .z component */
2310 so->writes_pos = true;
2311 break;
2312 case FRAG_RESULT_COLOR:
2313 so->color0_mrt = 1;
2314 break;
2315 default:
2316 if (slot >= FRAG_RESULT_DATA0)
2317 break;
2318 ir3_context_error(ctx, "unknown FS output name: %s\n",
2319 gl_frag_result_name(slot));
2320 }
2321 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2322 switch (slot) {
2323 case VARYING_SLOT_POS:
2324 so->writes_pos = true;
2325 break;
2326 case VARYING_SLOT_PSIZ:
2327 so->writes_psize = true;
2328 break;
2329 case VARYING_SLOT_COL0:
2330 case VARYING_SLOT_COL1:
2331 case VARYING_SLOT_BFC0:
2332 case VARYING_SLOT_BFC1:
2333 case VARYING_SLOT_FOGC:
2334 case VARYING_SLOT_CLIP_DIST0:
2335 case VARYING_SLOT_CLIP_DIST1:
2336 case VARYING_SLOT_CLIP_VERTEX:
2337 break;
2338 default:
2339 if (slot >= VARYING_SLOT_VAR0)
2340 break;
2341 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2342 break;
2343 ir3_context_error(ctx, "unknown VS output name: %s\n",
2344 gl_varying_slot_name(slot));
2345 }
2346 } else {
2347 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2348 }
2349
2350 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2351
2352 so->outputs[n].slot = slot;
2353 so->outputs[n].regid = regid(n, comp);
2354 so->outputs_count = MAX2(so->outputs_count, n + 1);
2355
2356 for (int i = 0; i < ncomp; i++) {
2357 unsigned idx = (n * 4) + i + frac;
2358 compile_assert(ctx, idx < ctx->ir->noutputs);
2359 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2360 }
2361
2362 /* if varying packing doesn't happen, we could end up in a situation
2363 * with "holes" in the output, and since the per-generation code that
2364 * sets up varying linkage registers doesn't expect to have more than
2365 * one varying per vec4 slot, pad the holes.
2366 *
2367 * Note that this should probably generate a performance warning of
2368 * some sort.
2369 */
2370 for (int i = 0; i < frac; i++) {
2371 unsigned idx = (n * 4) + i;
2372 if (!ctx->ir->outputs[idx]) {
2373 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2374 }
2375 }
2376 }
2377
2378 static int
2379 max_drvloc(struct exec_list *vars)
2380 {
2381 int drvloc = -1;
2382 nir_foreach_variable(var, vars) {
2383 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2384 }
2385 return drvloc;
2386 }
2387
2388 static const unsigned max_sysvals[] = {
2389 [MESA_SHADER_FRAGMENT] = 24, // TODO
2390 [MESA_SHADER_VERTEX] = 16,
2391 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2392 [MESA_SHADER_KERNEL] = 16, // TODO how many do we actually need?
2393 };
2394
2395 static void
2396 emit_instructions(struct ir3_context *ctx)
2397 {
2398 unsigned ninputs, noutputs;
2399 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2400
2401 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2402 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2403
2404 /* we need to leave room for sysvals:
2405 */
2406 ninputs += max_sysvals[ctx->so->type];
2407
2408 ctx->ir = ir3_create(ctx->compiler, ninputs, noutputs);
2409
2410 /* Create inputs in first block: */
2411 ctx->block = get_block(ctx, nir_start_block(fxn));
2412 ctx->in_block = ctx->block;
2413 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2414
2415 ninputs -= max_sysvals[ctx->so->type];
2416
2417 /* for fragment shader, the vcoord input register is used as the
2418 * base for bary.f varying fetch instrs:
2419 */
2420 struct ir3_instruction *vcoord = NULL;
2421 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2422 struct ir3_instruction *xy[2];
2423
2424 vcoord = create_input_compmask(ctx, 0, 0x3);
2425 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2426
2427 ctx->frag_vcoord = ir3_create_collect(ctx, xy, 2);
2428 }
2429
2430 /* Setup inputs: */
2431 nir_foreach_variable(var, &ctx->s->inputs) {
2432 setup_input(ctx, var);
2433 }
2434
2435 /* Defer add_sysval_input() stuff until after setup_inputs(),
2436 * because sysvals need to be appended after varyings:
2437 */
2438 if (vcoord) {
2439 add_sysval_input_compmask(ctx, SYSTEM_VALUE_VARYING_COORD,
2440 0x3, vcoord);
2441 }
2442
2443 if (ctx->frag_coord) {
2444 add_sysval_input_compmask(ctx, SYSTEM_VALUE_FRAG_COORD,
2445 0xf, ctx->frag_coord);
2446 }
2447
2448 /* Setup outputs: */
2449 nir_foreach_variable(var, &ctx->s->outputs) {
2450 setup_output(ctx, var);
2451 }
2452
2453 /* Find # of samplers: */
2454 nir_foreach_variable(var, &ctx->s->uniforms) {
2455 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
2456 /* just assume that we'll be reading from images.. if it
2457 * is write-only we don't have to count it, but not sure
2458 * if there is a good way to know?
2459 */
2460 ctx->so->num_samp += glsl_type_get_image_count(var->type);
2461 }
2462
2463 /* Setup registers (which should only be arrays): */
2464 nir_foreach_register(reg, &ctx->s->registers) {
2465 ir3_declare_array(ctx, reg);
2466 }
2467
2468 /* NOTE: need to do something more clever when we support >1 fxn */
2469 nir_foreach_register(reg, &fxn->registers) {
2470 ir3_declare_array(ctx, reg);
2471 }
2472 /* And emit the body: */
2473 ctx->impl = fxn;
2474 emit_function(ctx, fxn);
2475 }
2476
2477 /* from NIR perspective, we actually have varying inputs. But the varying
2478 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2479 * only actual inputs are the sysvals.
2480 */
2481 static void
2482 fixup_frag_inputs(struct ir3_context *ctx)
2483 {
2484 struct ir3_shader_variant *so = ctx->so;
2485 struct ir3 *ir = ctx->ir;
2486 unsigned i = 0;
2487
2488 /* sysvals should appear at the end of the inputs, drop everything else: */
2489 while ((i < so->inputs_count) && !so->inputs[i].sysval)
2490 i++;
2491
2492 /* at IR level, inputs are always blocks of 4 scalars: */
2493 i *= 4;
2494
2495 ir->inputs = &ir->inputs[i];
2496 ir->ninputs -= i;
2497 }
2498
2499 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2500 * need to assign the tex state indexes for these after we know the
2501 * max tex index.
2502 */
2503 static void
2504 fixup_astc_srgb(struct ir3_context *ctx)
2505 {
2506 struct ir3_shader_variant *so = ctx->so;
2507 /* indexed by original tex idx, value is newly assigned alpha sampler
2508 * state tex idx. Zero is invalid since there is at least one sampler
2509 * if we get here.
2510 */
2511 unsigned alt_tex_state[16] = {0};
2512 unsigned tex_idx = ctx->max_texture_index + 1;
2513 unsigned idx = 0;
2514
2515 so->astc_srgb.base = tex_idx;
2516
2517 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
2518 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
2519
2520 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
2521
2522 if (alt_tex_state[sam->cat5.tex] == 0) {
2523 /* assign new alternate/alpha tex state slot: */
2524 alt_tex_state[sam->cat5.tex] = tex_idx++;
2525 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
2526 so->astc_srgb.count++;
2527 }
2528
2529 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
2530 }
2531 }
2532
2533 static void
2534 fixup_binning_pass(struct ir3_context *ctx)
2535 {
2536 struct ir3_shader_variant *so = ctx->so;
2537 struct ir3 *ir = ctx->ir;
2538 unsigned i, j;
2539
2540 for (i = 0, j = 0; i < so->outputs_count; i++) {
2541 unsigned slot = so->outputs[i].slot;
2542
2543 /* throw away everything but first position/psize */
2544 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
2545 if (i != j) {
2546 so->outputs[j] = so->outputs[i];
2547 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
2548 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
2549 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
2550 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
2551 }
2552 j++;
2553 }
2554 }
2555 so->outputs_count = j;
2556 ir->noutputs = j * 4;
2557 }
2558
2559 int
2560 ir3_compile_shader_nir(struct ir3_compiler *compiler,
2561 struct ir3_shader_variant *so)
2562 {
2563 struct ir3_context *ctx;
2564 struct ir3 *ir;
2565 struct ir3_instruction **inputs;
2566 unsigned i, actual_in, inloc;
2567 int ret = 0, max_bary;
2568
2569 assert(!so->ir);
2570
2571 ctx = ir3_context_init(compiler, so);
2572 if (!ctx) {
2573 DBG("INIT failed!");
2574 ret = -1;
2575 goto out;
2576 }
2577
2578 emit_instructions(ctx);
2579
2580 if (ctx->error) {
2581 DBG("EMIT failed!");
2582 ret = -1;
2583 goto out;
2584 }
2585
2586 ir = so->ir = ctx->ir;
2587
2588 /* keep track of the inputs from TGSI perspective.. */
2589 inputs = ir->inputs;
2590
2591 /* but fixup actual inputs for frag shader: */
2592 if (so->type == MESA_SHADER_FRAGMENT)
2593 fixup_frag_inputs(ctx);
2594
2595 /* at this point, for binning pass, throw away unneeded outputs: */
2596 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
2597 fixup_binning_pass(ctx);
2598
2599 /* if we want half-precision outputs, mark the output registers
2600 * as half:
2601 */
2602 if (so->key.half_precision) {
2603 for (i = 0; i < ir->noutputs; i++) {
2604 struct ir3_instruction *out = ir->outputs[i];
2605
2606 if (!out)
2607 continue;
2608
2609 /* if frag shader writes z, that needs to be full precision: */
2610 if (so->outputs[i/4].slot == FRAG_RESULT_DEPTH)
2611 continue;
2612
2613 out->regs[0]->flags |= IR3_REG_HALF;
2614 /* output could be a fanout (ie. texture fetch output)
2615 * in which case we need to propagate the half-reg flag
2616 * up to the definer so that RA sees it:
2617 */
2618 if (out->opc == OPC_META_FO) {
2619 out = out->regs[1]->instr;
2620 out->regs[0]->flags |= IR3_REG_HALF;
2621 }
2622
2623 if (out->opc == OPC_MOV) {
2624 out->cat1.dst_type = half_type(out->cat1.dst_type);
2625 }
2626 }
2627 }
2628
2629 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2630 printf("BEFORE CP:\n");
2631 ir3_print(ir);
2632 }
2633
2634 ir3_cp(ir, so);
2635
2636 /* at this point, for binning pass, throw away unneeded outputs:
2637 * Note that for a6xx and later, we do this after ir3_cp to ensure
2638 * that the uniform/constant layout for BS and VS matches, so that
2639 * we can re-use same VS_CONST state group.
2640 */
2641 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
2642 fixup_binning_pass(ctx);
2643
2644 /* Insert mov if there's same instruction for each output.
2645 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
2646 */
2647 for (int i = ir->noutputs - 1; i >= 0; i--) {
2648 if (!ir->outputs[i])
2649 continue;
2650 for (unsigned j = 0; j < i; j++) {
2651 if (ir->outputs[i] == ir->outputs[j]) {
2652 ir->outputs[i] =
2653 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
2654 }
2655 }
2656 }
2657
2658 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2659 printf("BEFORE GROUPING:\n");
2660 ir3_print(ir);
2661 }
2662
2663 ir3_sched_add_deps(ir);
2664
2665 /* Group left/right neighbors, inserting mov's where needed to
2666 * solve conflicts:
2667 */
2668 ir3_group(ir);
2669
2670 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2671 printf("AFTER GROUPING:\n");
2672 ir3_print(ir);
2673 }
2674
2675 ir3_depth(ir);
2676
2677 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2678 printf("AFTER DEPTH:\n");
2679 ir3_print(ir);
2680 }
2681
2682 /* do Sethi–Ullman numbering before scheduling: */
2683 ir3_sun(ir);
2684
2685 ret = ir3_sched(ir);
2686 if (ret) {
2687 DBG("SCHED failed!");
2688 goto out;
2689 }
2690
2691 if (compiler->gpu_id >= 600) {
2692 ir3_a6xx_fixup_atomic_dests(ir, so);
2693 }
2694
2695 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2696 printf("AFTER SCHED:\n");
2697 ir3_print(ir);
2698 }
2699
2700 ret = ir3_ra(ir, so->type, so->frag_coord, so->frag_face);
2701 if (ret) {
2702 DBG("RA failed!");
2703 goto out;
2704 }
2705
2706 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2707 printf("AFTER RA:\n");
2708 ir3_print(ir);
2709 }
2710
2711 /* fixup input/outputs: */
2712 for (i = 0; i < so->outputs_count; i++) {
2713 /* sometimes we get outputs that don't write the .x coord, like:
2714 *
2715 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
2716 *
2717 * Presumably the result of varying packing and then eliminating
2718 * some unneeded varyings? Just skip head to the first valid
2719 * component of the output.
2720 */
2721 for (unsigned j = 0; j < 4; j++) {
2722 struct ir3_instruction *instr = ir->outputs[(i*4) + j];
2723 if (instr) {
2724 so->outputs[i].regid = instr->regs[0]->num;
2725 break;
2726 }
2727 }
2728 }
2729
2730 /* Note that some or all channels of an input may be unused: */
2731 actual_in = 0;
2732 inloc = 0;
2733 for (i = 0; i < so->inputs_count; i++) {
2734 unsigned j, reg = regid(63,0), compmask = 0, maxcomp = 0;
2735 so->inputs[i].ncomp = 0;
2736 so->inputs[i].inloc = inloc;
2737 for (j = 0; j < 4; j++) {
2738 struct ir3_instruction *in = inputs[(i*4) + j];
2739 if (in && !(in->flags & IR3_INSTR_UNUSED)) {
2740 compmask |= (1 << j);
2741 reg = in->regs[0]->num - j;
2742 actual_in++;
2743 so->inputs[i].ncomp++;
2744 if ((so->type == MESA_SHADER_FRAGMENT) && so->inputs[i].bary) {
2745 /* assign inloc: */
2746 assert(in->regs[1]->flags & IR3_REG_IMMED);
2747 in->regs[1]->iim_val = inloc + j;
2748 maxcomp = j + 1;
2749 }
2750 }
2751 }
2752 if ((so->type == MESA_SHADER_FRAGMENT) && compmask && so->inputs[i].bary) {
2753 so->varying_in++;
2754 so->inputs[i].compmask = (1 << maxcomp) - 1;
2755 inloc += maxcomp;
2756 } else if (!so->inputs[i].sysval) {
2757 so->inputs[i].compmask = compmask;
2758 }
2759 so->inputs[i].regid = reg;
2760 }
2761
2762 if (ctx->astc_srgb)
2763 fixup_astc_srgb(ctx);
2764
2765 /* We need to do legalize after (for frag shader's) the "bary.f"
2766 * offsets (inloc) have been assigned.
2767 */
2768 ir3_legalize(ir, &so->has_ssbo, &max_bary);
2769
2770 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2771 printf("AFTER LEGALIZE:\n");
2772 ir3_print(ir);
2773 }
2774
2775 so->branchstack = ctx->max_stack;
2776
2777 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
2778 if (so->type == MESA_SHADER_VERTEX)
2779 so->total_in = actual_in;
2780 else
2781 so->total_in = max_bary + 1;
2782
2783 so->max_sun = ir->max_sun;
2784
2785 out:
2786 if (ret) {
2787 if (so->ir)
2788 ir3_destroy(so->ir);
2789 so->ir = NULL;
2790 }
2791 ir3_context_free(ctx);
2792
2793 return ret;
2794 }