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freedreno/ir3: fix bit_count
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 ir3_reg_create(mov, 0, 0);
55 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
56 src->instr = collect;
57 src->size = arrsz;
58 src->array.offset = n;
59
60 ir3_instr_set_address(mov, address);
61
62 return mov;
63 }
64
65 static struct ir3_instruction *
66 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
67 {
68 struct ir3_instruction *in;
69
70 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
71 in->inout.block = ctx->in_block;
72 ir3_reg_create(in, n, 0);
73
74 in->regs[0]->wrmask = compmask;
75
76 return in;
77 }
78
79 static struct ir3_instruction *
80 create_input(struct ir3_context *ctx, unsigned n)
81 {
82 return create_input_compmask(ctx, n, 0x1);
83 }
84
85 static struct ir3_instruction *
86 create_frag_input(struct ir3_context *ctx, bool use_ldlv)
87 {
88 struct ir3_block *block = ctx->block;
89 struct ir3_instruction *instr;
90 /* actual inloc is assigned and fixed up later: */
91 struct ir3_instruction *inloc = create_immed(block, 0);
92
93 if (use_ldlv) {
94 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
95 instr->cat6.type = TYPE_U32;
96 instr->cat6.iim_val = 1;
97 } else {
98 instr = ir3_BARY_F(block, inloc, 0, ctx->frag_vcoord, 0);
99 instr->regs[2]->wrmask = 0x3;
100 }
101
102 return instr;
103 }
104
105 static struct ir3_instruction *
106 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
107 {
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 unsigned n = ctx->so->constbase.driver_param;
111 unsigned r = regid(n + dp / 4, dp % 4);
112 return create_uniform(ctx->block, r);
113 }
114
115 /*
116 * Adreno uses uint rather than having dedicated bool type,
117 * which (potentially) requires some conversion, in particular
118 * when using output of an bool instr to int input, or visa
119 * versa.
120 *
121 * | Adreno | NIR |
122 * -------+---------+-------+-
123 * true | 1 | ~0 |
124 * false | 0 | 0 |
125 *
126 * To convert from an adreno bool (uint) to nir, use:
127 *
128 * absneg.s dst, (neg)src
129 *
130 * To convert back in the other direction:
131 *
132 * absneg.s dst, (abs)arc
133 *
134 * The CP step can clean up the absneg.s that cancel each other
135 * out, and with a slight bit of extra cleverness (to recognize
136 * the instructions which produce either a 0 or 1) can eliminate
137 * the absneg.s's completely when an instruction that wants
138 * 0/1 consumes the result. For example, when a nir 'bcsel'
139 * consumes the result of 'feq'. So we should be able to get by
140 * without a boolean resolve step, and without incuring any
141 * extra penalty in instruction count.
142 */
143
144 /* NIR bool -> native (adreno): */
145 static struct ir3_instruction *
146 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
147 {
148 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
149 }
150
151 /* native (adreno) -> NIR bool: */
152 static struct ir3_instruction *
153 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
154 {
155 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
156 }
157
158 /*
159 * alu/sfu instructions:
160 */
161
162 static struct ir3_instruction *
163 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
164 unsigned src_bitsize, nir_op op)
165 {
166 type_t src_type, dst_type;
167
168 switch (op) {
169 case nir_op_f2f32:
170 case nir_op_f2f16_rtne:
171 case nir_op_f2f16_rtz:
172 case nir_op_f2f16:
173 case nir_op_f2i32:
174 case nir_op_f2i16:
175 case nir_op_f2i8:
176 case nir_op_f2u32:
177 case nir_op_f2u16:
178 case nir_op_f2u8:
179 switch (src_bitsize) {
180 case 32:
181 src_type = TYPE_F32;
182 break;
183 case 16:
184 src_type = TYPE_F16;
185 break;
186 default:
187 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
188 }
189 break;
190
191 case nir_op_i2f32:
192 case nir_op_i2f16:
193 case nir_op_i2i32:
194 case nir_op_i2i16:
195 case nir_op_i2i8:
196 switch (src_bitsize) {
197 case 32:
198 src_type = TYPE_S32;
199 break;
200 case 16:
201 src_type = TYPE_S16;
202 break;
203 case 8:
204 src_type = TYPE_S8;
205 break;
206 default:
207 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
208 }
209 break;
210
211 case nir_op_u2f32:
212 case nir_op_u2f16:
213 case nir_op_u2u32:
214 case nir_op_u2u16:
215 case nir_op_u2u8:
216 switch (src_bitsize) {
217 case 32:
218 src_type = TYPE_U32;
219 break;
220 case 16:
221 src_type = TYPE_U16;
222 break;
223 case 8:
224 src_type = TYPE_U8;
225 break;
226 default:
227 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
228 }
229 break;
230
231 default:
232 ir3_context_error(ctx, "invalid conversion op: %u", op);
233 }
234
235 switch (op) {
236 case nir_op_f2f32:
237 case nir_op_i2f32:
238 case nir_op_u2f32:
239 dst_type = TYPE_F32;
240 break;
241
242 case nir_op_f2f16_rtne:
243 case nir_op_f2f16_rtz:
244 case nir_op_f2f16:
245 /* TODO how to handle rounding mode? */
246 case nir_op_i2f16:
247 case nir_op_u2f16:
248 dst_type = TYPE_F16;
249 break;
250
251 case nir_op_f2i32:
252 case nir_op_i2i32:
253 dst_type = TYPE_S32;
254 break;
255
256 case nir_op_f2i16:
257 case nir_op_i2i16:
258 dst_type = TYPE_S16;
259 break;
260
261 case nir_op_f2i8:
262 case nir_op_i2i8:
263 dst_type = TYPE_S8;
264 break;
265
266 case nir_op_f2u32:
267 case nir_op_u2u32:
268 dst_type = TYPE_U32;
269 break;
270
271 case nir_op_f2u16:
272 case nir_op_u2u16:
273 dst_type = TYPE_U16;
274 break;
275
276 case nir_op_f2u8:
277 case nir_op_u2u8:
278 dst_type = TYPE_U8;
279 break;
280
281 default:
282 ir3_context_error(ctx, "invalid conversion op: %u", op);
283 }
284
285 return ir3_COV(ctx->block, src, src_type, dst_type);
286 }
287
288 static void
289 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
290 {
291 const nir_op_info *info = &nir_op_infos[alu->op];
292 struct ir3_instruction **dst, *src[info->num_inputs];
293 unsigned bs[info->num_inputs]; /* bit size */
294 struct ir3_block *b = ctx->block;
295 unsigned dst_sz, wrmask;
296
297 if (alu->dest.dest.is_ssa) {
298 dst_sz = alu->dest.dest.ssa.num_components;
299 wrmask = (1 << dst_sz) - 1;
300 } else {
301 dst_sz = alu->dest.dest.reg.reg->num_components;
302 wrmask = alu->dest.write_mask;
303 }
304
305 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
306
307 /* Vectors are special in that they have non-scalarized writemasks,
308 * and just take the first swizzle channel for each argument in
309 * order into each writemask channel.
310 */
311 if ((alu->op == nir_op_vec2) ||
312 (alu->op == nir_op_vec3) ||
313 (alu->op == nir_op_vec4)) {
314
315 for (int i = 0; i < info->num_inputs; i++) {
316 nir_alu_src *asrc = &alu->src[i];
317
318 compile_assert(ctx, !asrc->abs);
319 compile_assert(ctx, !asrc->negate);
320
321 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
322 if (!src[i])
323 src[i] = create_immed(ctx->block, 0);
324 dst[i] = ir3_MOV(b, src[i], TYPE_U32);
325 }
326
327 ir3_put_dst(ctx, &alu->dest.dest);
328 return;
329 }
330
331 /* We also get mov's with more than one component for mov's so
332 * handle those specially:
333 */
334 if ((alu->op == nir_op_imov) || (alu->op == nir_op_fmov)) {
335 type_t type = (alu->op == nir_op_imov) ? TYPE_U32 : TYPE_F32;
336 nir_alu_src *asrc = &alu->src[0];
337 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
338
339 for (unsigned i = 0; i < dst_sz; i++) {
340 if (wrmask & (1 << i)) {
341 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], type);
342 } else {
343 dst[i] = NULL;
344 }
345 }
346
347 ir3_put_dst(ctx, &alu->dest.dest);
348 return;
349 }
350
351 /* General case: We can just grab the one used channel per src. */
352 for (int i = 0; i < info->num_inputs; i++) {
353 unsigned chan = ffs(alu->dest.write_mask) - 1;
354 nir_alu_src *asrc = &alu->src[i];
355
356 compile_assert(ctx, !asrc->abs);
357 compile_assert(ctx, !asrc->negate);
358
359 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
360 bs[i] = nir_src_bit_size(asrc->src);
361
362 compile_assert(ctx, src[i]);
363 }
364
365 switch (alu->op) {
366 case nir_op_f2f32:
367 case nir_op_f2f16_rtne:
368 case nir_op_f2f16_rtz:
369 case nir_op_f2f16:
370 case nir_op_f2i32:
371 case nir_op_f2i16:
372 case nir_op_f2i8:
373 case nir_op_f2u32:
374 case nir_op_f2u16:
375 case nir_op_f2u8:
376 case nir_op_i2f32:
377 case nir_op_i2f16:
378 case nir_op_i2i32:
379 case nir_op_i2i16:
380 case nir_op_i2i8:
381 case nir_op_u2f32:
382 case nir_op_u2f16:
383 case nir_op_u2u32:
384 case nir_op_u2u16:
385 case nir_op_u2u8:
386 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
387 break;
388 case nir_op_f2b32:
389 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
390 dst[0]->cat2.condition = IR3_COND_NE;
391 dst[0] = ir3_n2b(b, dst[0]);
392 break;
393 case nir_op_b2f16:
394 case nir_op_b2f32:
395 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
396 break;
397 case nir_op_b2i8:
398 case nir_op_b2i16:
399 case nir_op_b2i32:
400 dst[0] = ir3_b2n(b, src[0]);
401 break;
402 case nir_op_i2b32:
403 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
404 dst[0]->cat2.condition = IR3_COND_NE;
405 dst[0] = ir3_n2b(b, dst[0]);
406 break;
407
408 case nir_op_fneg:
409 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
410 break;
411 case nir_op_fabs:
412 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
413 break;
414 case nir_op_fmax:
415 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
416 break;
417 case nir_op_fmin:
418 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
419 break;
420 case nir_op_fsat:
421 /* if there is just a single use of the src, and it supports
422 * (sat) bit, we can just fold the (sat) flag back to the
423 * src instruction and create a mov. This is easier for cp
424 * to eliminate.
425 *
426 * TODO probably opc_cat==4 is ok too
427 */
428 if (alu->src[0].src.is_ssa &&
429 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
430 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
431 src[0]->flags |= IR3_INSTR_SAT;
432 dst[0] = ir3_MOV(b, src[0], TYPE_U32);
433 } else {
434 /* otherwise generate a max.f that saturates.. blob does
435 * similar (generating a cat2 mov using max.f)
436 */
437 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
438 dst[0]->flags |= IR3_INSTR_SAT;
439 }
440 break;
441 case nir_op_fmul:
442 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
443 break;
444 case nir_op_fadd:
445 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
446 break;
447 case nir_op_fsub:
448 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
449 break;
450 case nir_op_ffma:
451 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
452 break;
453 case nir_op_fddx:
454 dst[0] = ir3_DSX(b, src[0], 0);
455 dst[0]->cat5.type = TYPE_F32;
456 break;
457 case nir_op_fddy:
458 dst[0] = ir3_DSY(b, src[0], 0);
459 dst[0]->cat5.type = TYPE_F32;
460 break;
461 break;
462 case nir_op_flt32:
463 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
464 dst[0]->cat2.condition = IR3_COND_LT;
465 dst[0] = ir3_n2b(b, dst[0]);
466 break;
467 case nir_op_fge32:
468 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
469 dst[0]->cat2.condition = IR3_COND_GE;
470 dst[0] = ir3_n2b(b, dst[0]);
471 break;
472 case nir_op_feq32:
473 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
474 dst[0]->cat2.condition = IR3_COND_EQ;
475 dst[0] = ir3_n2b(b, dst[0]);
476 break;
477 case nir_op_fne32:
478 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
479 dst[0]->cat2.condition = IR3_COND_NE;
480 dst[0] = ir3_n2b(b, dst[0]);
481 break;
482 case nir_op_fceil:
483 dst[0] = ir3_CEIL_F(b, src[0], 0);
484 break;
485 case nir_op_ffloor:
486 dst[0] = ir3_FLOOR_F(b, src[0], 0);
487 break;
488 case nir_op_ftrunc:
489 dst[0] = ir3_TRUNC_F(b, src[0], 0);
490 break;
491 case nir_op_fround_even:
492 dst[0] = ir3_RNDNE_F(b, src[0], 0);
493 break;
494 case nir_op_fsign:
495 dst[0] = ir3_SIGN_F(b, src[0], 0);
496 break;
497
498 case nir_op_fsin:
499 dst[0] = ir3_SIN(b, src[0], 0);
500 break;
501 case nir_op_fcos:
502 dst[0] = ir3_COS(b, src[0], 0);
503 break;
504 case nir_op_frsq:
505 dst[0] = ir3_RSQ(b, src[0], 0);
506 break;
507 case nir_op_frcp:
508 dst[0] = ir3_RCP(b, src[0], 0);
509 break;
510 case nir_op_flog2:
511 dst[0] = ir3_LOG2(b, src[0], 0);
512 break;
513 case nir_op_fexp2:
514 dst[0] = ir3_EXP2(b, src[0], 0);
515 break;
516 case nir_op_fsqrt:
517 dst[0] = ir3_SQRT(b, src[0], 0);
518 break;
519
520 case nir_op_iabs:
521 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
522 break;
523 case nir_op_iadd:
524 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
525 break;
526 case nir_op_iand:
527 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
528 break;
529 case nir_op_imax:
530 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
531 break;
532 case nir_op_umax:
533 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
534 break;
535 case nir_op_imin:
536 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
537 break;
538 case nir_op_umin:
539 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
540 break;
541 case nir_op_imul:
542 /*
543 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
544 * mull.u tmp0, a, b ; mul low, i.e. al * bl
545 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
546 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
547 */
548 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0,
549 ir3_MADSH_M16(b, src[0], 0, src[1], 0,
550 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0);
551 break;
552 case nir_op_ineg:
553 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
554 break;
555 case nir_op_inot:
556 dst[0] = ir3_NOT_B(b, src[0], 0);
557 break;
558 case nir_op_ior:
559 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
560 break;
561 case nir_op_ishl:
562 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
563 break;
564 case nir_op_ishr:
565 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
566 break;
567 case nir_op_isub:
568 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
569 break;
570 case nir_op_ixor:
571 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
572 break;
573 case nir_op_ushr:
574 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
575 break;
576 case nir_op_ilt32:
577 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
578 dst[0]->cat2.condition = IR3_COND_LT;
579 dst[0] = ir3_n2b(b, dst[0]);
580 break;
581 case nir_op_ige32:
582 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
583 dst[0]->cat2.condition = IR3_COND_GE;
584 dst[0] = ir3_n2b(b, dst[0]);
585 break;
586 case nir_op_ieq32:
587 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
588 dst[0]->cat2.condition = IR3_COND_EQ;
589 dst[0] = ir3_n2b(b, dst[0]);
590 break;
591 case nir_op_ine32:
592 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
593 dst[0]->cat2.condition = IR3_COND_NE;
594 dst[0] = ir3_n2b(b, dst[0]);
595 break;
596 case nir_op_ult32:
597 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
598 dst[0]->cat2.condition = IR3_COND_LT;
599 dst[0] = ir3_n2b(b, dst[0]);
600 break;
601 case nir_op_uge32:
602 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
603 dst[0]->cat2.condition = IR3_COND_GE;
604 dst[0] = ir3_n2b(b, dst[0]);
605 break;
606
607 case nir_op_b32csel: {
608 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
609 compile_assert(ctx, bs[1] == bs[2]);
610 /* the boolean condition is 32b even if src[1] and src[2] are
611 * half-precision, but sel.b16 wants all three src's to be the
612 * same type.
613 */
614 if (bs[1] < 32)
615 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
616 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
617 break;
618 }
619 case nir_op_bit_count: {
620 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
621 // double check on earlier gen's. Once half-precision support is
622 // in place, this should probably move to a NIR lowering pass:
623 struct ir3_instruction *hi, *lo;
624
625 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
626 TYPE_U32, TYPE_U16);
627 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
628
629 hi = ir3_CBITS_B(b, hi, 0);
630 lo = ir3_CBITS_B(b, lo, 0);
631
632 // TODO maybe the builders should default to making dst half-precision
633 // if the src's were half precision, to make this less awkward.. otoh
634 // we should probably just do this lowering in NIR.
635 hi->regs[0]->flags |= IR3_REG_HALF;
636 lo->regs[0]->flags |= IR3_REG_HALF;
637
638 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
639 dst[0]->regs[0]->flags |= IR3_REG_HALF;
640 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
641 break;
642 }
643 case nir_op_ifind_msb: {
644 struct ir3_instruction *cmp;
645 dst[0] = ir3_CLZ_S(b, src[0], 0);
646 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
647 cmp->cat2.condition = IR3_COND_GE;
648 dst[0] = ir3_SEL_B32(b,
649 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
650 cmp, 0, dst[0], 0);
651 break;
652 }
653 case nir_op_ufind_msb:
654 dst[0] = ir3_CLZ_B(b, src[0], 0);
655 dst[0] = ir3_SEL_B32(b,
656 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
657 src[0], 0, dst[0], 0);
658 break;
659 case nir_op_find_lsb:
660 dst[0] = ir3_BFREV_B(b, src[0], 0);
661 dst[0] = ir3_CLZ_B(b, dst[0], 0);
662 break;
663 case nir_op_bitfield_reverse:
664 dst[0] = ir3_BFREV_B(b, src[0], 0);
665 break;
666
667 default:
668 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
669 nir_op_infos[alu->op].name);
670 break;
671 }
672
673 ir3_put_dst(ctx, &alu->dest.dest);
674 }
675
676 /* handles direct/indirect UBO reads: */
677 static void
678 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
679 struct ir3_instruction **dst)
680 {
681 struct ir3_block *b = ctx->block;
682 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
683 nir_const_value *const_offset;
684 /* UBO addresses are the first driver params: */
685 unsigned ubo = regid(ctx->so->constbase.ubo, 0);
686 const unsigned ptrsz = ir3_pointer_size(ctx);
687
688 int off = 0;
689
690 /* First src is ubo index, which could either be an immed or not: */
691 src0 = ir3_get_src(ctx, &intr->src[0])[0];
692 if (is_same_type_mov(src0) &&
693 (src0->regs[1]->flags & IR3_REG_IMMED)) {
694 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
695 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
696 } else {
697 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, 4));
698 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, 4));
699 }
700
701 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
702 addr = base_lo;
703
704 const_offset = nir_src_as_const_value(intr->src[1]);
705 if (const_offset) {
706 off += const_offset->u32[0];
707 } else {
708 /* For load_ubo_indirect, second src is indirect offset: */
709 src1 = ir3_get_src(ctx, &intr->src[1])[0];
710
711 /* and add offset to addr: */
712 addr = ir3_ADD_S(b, addr, 0, src1, 0);
713 }
714
715 /* if offset is to large to encode in the ldg, split it out: */
716 if ((off + (intr->num_components * 4)) > 1024) {
717 /* split out the minimal amount to improve the odds that
718 * cp can fit the immediate in the add.s instruction:
719 */
720 unsigned off2 = off + (intr->num_components * 4) - 1024;
721 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
722 off -= off2;
723 }
724
725 if (ptrsz == 2) {
726 struct ir3_instruction *carry;
727
728 /* handle 32b rollover, ie:
729 * if (addr < base_lo)
730 * base_hi++
731 */
732 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
733 carry->cat2.condition = IR3_COND_LT;
734 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
735
736 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
737 }
738
739 for (int i = 0; i < intr->num_components; i++) {
740 struct ir3_instruction *load =
741 ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
742 load->cat6.type = TYPE_U32;
743 load->cat6.src_offset = off + i * 4; /* byte offset */
744 dst[i] = load;
745 }
746 }
747
748 /* src[] = { block_index } */
749 static void
750 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
751 struct ir3_instruction **dst)
752 {
753 /* SSBO size stored as a const starting at ssbo_sizes: */
754 unsigned blk_idx = nir_src_as_const_value(intr->src[0])->u32[0];
755 unsigned idx = regid(ctx->so->constbase.ssbo_sizes, 0) +
756 ctx->so->const_layout.ssbo_size.off[blk_idx];
757
758 debug_assert(ctx->so->const_layout.ssbo_size.mask & (1 << blk_idx));
759
760 dst[0] = create_uniform(ctx->block, idx);
761 }
762
763 /* src[] = { offset }. const_index[] = { base } */
764 static void
765 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
766 struct ir3_instruction **dst)
767 {
768 struct ir3_block *b = ctx->block;
769 struct ir3_instruction *ldl, *offset;
770 unsigned base;
771
772 offset = ir3_get_src(ctx, &intr->src[0])[0];
773 base = nir_intrinsic_base(intr);
774
775 ldl = ir3_LDL(b, offset, 0, create_immed(b, intr->num_components), 0);
776 ldl->cat6.src_offset = base;
777 ldl->cat6.type = utype_dst(intr->dest);
778 ldl->regs[0]->wrmask = MASK(intr->num_components);
779
780 ldl->barrier_class = IR3_BARRIER_SHARED_R;
781 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
782
783 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
784 }
785
786 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
787 static void
788 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
789 {
790 struct ir3_block *b = ctx->block;
791 struct ir3_instruction *stl, *offset;
792 struct ir3_instruction * const *value;
793 unsigned base, wrmask;
794
795 value = ir3_get_src(ctx, &intr->src[0]);
796 offset = ir3_get_src(ctx, &intr->src[1])[0];
797
798 base = nir_intrinsic_base(intr);
799 wrmask = nir_intrinsic_write_mask(intr);
800
801 /* Combine groups of consecutive enabled channels in one write
802 * message. We use ffs to find the first enabled channel and then ffs on
803 * the bit-inverse, down-shifted writemask to determine the length of
804 * the block of enabled bits.
805 *
806 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
807 */
808 while (wrmask) {
809 unsigned first_component = ffs(wrmask) - 1;
810 unsigned length = ffs(~(wrmask >> first_component)) - 1;
811
812 stl = ir3_STL(b, offset, 0,
813 ir3_create_collect(ctx, &value[first_component], length), 0,
814 create_immed(b, length), 0);
815 stl->cat6.dst_offset = first_component + base;
816 stl->cat6.type = utype_src(intr->src[0]);
817 stl->barrier_class = IR3_BARRIER_SHARED_W;
818 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
819
820 array_insert(b, b->keeps, stl);
821
822 /* Clear the bits in the writemask that we just wrote, then try
823 * again to see if more channels are left.
824 */
825 wrmask &= (15 << (first_component + length));
826 }
827 }
828
829 /*
830 * CS shared variable atomic intrinsics
831 *
832 * All of the shared variable atomic memory operations read a value from
833 * memory, compute a new value using one of the operations below, write the
834 * new value to memory, and return the original value read.
835 *
836 * All operations take 2 sources except CompSwap that takes 3. These
837 * sources represent:
838 *
839 * 0: The offset into the shared variable storage region that the atomic
840 * operation will operate on.
841 * 1: The data parameter to the atomic function (i.e. the value to add
842 * in shared_atomic_add, etc).
843 * 2: For CompSwap only: the second data parameter.
844 */
845 static struct ir3_instruction *
846 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
847 {
848 struct ir3_block *b = ctx->block;
849 struct ir3_instruction *atomic, *src0, *src1;
850 type_t type = TYPE_U32;
851
852 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
853 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
854
855 switch (intr->intrinsic) {
856 case nir_intrinsic_shared_atomic_add:
857 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
858 break;
859 case nir_intrinsic_shared_atomic_imin:
860 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
861 type = TYPE_S32;
862 break;
863 case nir_intrinsic_shared_atomic_umin:
864 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
865 break;
866 case nir_intrinsic_shared_atomic_imax:
867 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
868 type = TYPE_S32;
869 break;
870 case nir_intrinsic_shared_atomic_umax:
871 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
872 break;
873 case nir_intrinsic_shared_atomic_and:
874 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
875 break;
876 case nir_intrinsic_shared_atomic_or:
877 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
878 break;
879 case nir_intrinsic_shared_atomic_xor:
880 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
881 break;
882 case nir_intrinsic_shared_atomic_exchange:
883 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
884 break;
885 case nir_intrinsic_shared_atomic_comp_swap:
886 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
887 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
888 ir3_get_src(ctx, &intr->src[2])[0],
889 src1,
890 }, 2);
891 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
892 break;
893 default:
894 unreachable("boo");
895 }
896
897 atomic->cat6.iim_val = 1;
898 atomic->cat6.d = 1;
899 atomic->cat6.type = type;
900 atomic->barrier_class = IR3_BARRIER_SHARED_W;
901 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
902
903 /* even if nothing consume the result, we can't DCE the instruction: */
904 array_insert(b, b->keeps, atomic);
905
906 return atomic;
907 }
908
909 /* TODO handle actual indirect/dynamic case.. which is going to be weird
910 * to handle with the image_mapping table..
911 */
912 static struct ir3_instruction *
913 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
914 {
915 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
916 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
917 struct ir3_instruction *texture, *sampler;
918
919 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
920 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
921
922 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
923 sampler,
924 texture,
925 }, 2);
926 }
927
928 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
929 static void
930 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
931 struct ir3_instruction **dst)
932 {
933 struct ir3_block *b = ctx->block;
934 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
935 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
936 struct ir3_instruction *sam;
937 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
938 struct ir3_instruction *coords[4];
939 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
940 type_t type = ir3_get_image_type(var);
941
942 /* hmm, this seems a bit odd, but it is what blob does and (at least
943 * a5xx) just faults on bogus addresses otherwise:
944 */
945 if (flags & IR3_INSTR_3D) {
946 flags &= ~IR3_INSTR_3D;
947 flags |= IR3_INSTR_A;
948 }
949
950 for (unsigned i = 0; i < ncoords; i++)
951 coords[i] = src0[i];
952
953 if (ncoords == 1)
954 coords[ncoords++] = create_immed(b, 0);
955
956 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
957 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
958
959 sam->barrier_class = IR3_BARRIER_IMAGE_R;
960 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
961
962 ir3_split_dest(b, dst, sam, 0, 4);
963 }
964
965 static void
966 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
967 struct ir3_instruction **dst)
968 {
969 struct ir3_block *b = ctx->block;
970 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
971 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
972 struct ir3_instruction *sam, *lod;
973 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
974
975 lod = create_immed(b, 0);
976 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
977 samp_tex, lod, NULL);
978
979 /* Array size actually ends up in .w rather than .z. This doesn't
980 * matter for miplevel 0, but for higher mips the value in z is
981 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
982 * returned, which means that we have to add 1 to it for arrays for
983 * a3xx.
984 *
985 * Note use a temporary dst and then copy, since the size of the dst
986 * array that is passed in is based on nir's understanding of the
987 * result size, not the hardware's
988 */
989 struct ir3_instruction *tmp[4];
990
991 ir3_split_dest(b, tmp, sam, 0, 4);
992
993 /* get_size instruction returns size in bytes instead of texels
994 * for imageBuffer, so we need to divide it by the pixel size
995 * of the image format.
996 *
997 * TODO: This is at least true on a5xx. Check other gens.
998 */
999 enum glsl_sampler_dim dim =
1000 glsl_get_sampler_dim(glsl_without_array(var->type));
1001 if (dim == GLSL_SAMPLER_DIM_BUF) {
1002 /* Since all the possible values the divisor can take are
1003 * power-of-two (4, 8, or 16), the division is implemented
1004 * as a shift-right.
1005 * During shader setup, the log2 of the image format's
1006 * bytes-per-pixel should have been emitted in 2nd slot of
1007 * image_dims. See ir3_shader::emit_image_dims().
1008 */
1009 unsigned cb = regid(ctx->so->constbase.image_dims, 0) +
1010 ctx->so->const_layout.image_dims.off[var->data.driver_location];
1011 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1012
1013 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1014 }
1015
1016 for (unsigned i = 0; i < ncoords; i++)
1017 dst[i] = tmp[i];
1018
1019 if (flags & IR3_INSTR_A) {
1020 if (ctx->compiler->levels_add_one) {
1021 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1022 } else {
1023 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1024 }
1025 }
1026 }
1027
1028 static void
1029 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1030 {
1031 struct ir3_block *b = ctx->block;
1032 struct ir3_instruction *barrier;
1033
1034 switch (intr->intrinsic) {
1035 case nir_intrinsic_barrier:
1036 barrier = ir3_BAR(b);
1037 barrier->cat7.g = true;
1038 barrier->cat7.l = true;
1039 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1040 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1041 break;
1042 case nir_intrinsic_memory_barrier:
1043 barrier = ir3_FENCE(b);
1044 barrier->cat7.g = true;
1045 barrier->cat7.r = true;
1046 barrier->cat7.w = true;
1047 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1048 IR3_BARRIER_BUFFER_W;
1049 barrier->barrier_conflict =
1050 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1051 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1052 break;
1053 case nir_intrinsic_memory_barrier_atomic_counter:
1054 case nir_intrinsic_memory_barrier_buffer:
1055 barrier = ir3_FENCE(b);
1056 barrier->cat7.g = true;
1057 barrier->cat7.r = true;
1058 barrier->cat7.w = true;
1059 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1060 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1061 IR3_BARRIER_BUFFER_W;
1062 break;
1063 case nir_intrinsic_memory_barrier_image:
1064 // TODO double check if this should have .g set
1065 barrier = ir3_FENCE(b);
1066 barrier->cat7.g = true;
1067 barrier->cat7.r = true;
1068 barrier->cat7.w = true;
1069 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1070 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1071 IR3_BARRIER_IMAGE_W;
1072 break;
1073 case nir_intrinsic_memory_barrier_shared:
1074 barrier = ir3_FENCE(b);
1075 barrier->cat7.g = true;
1076 barrier->cat7.l = true;
1077 barrier->cat7.r = true;
1078 barrier->cat7.w = true;
1079 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1080 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1081 IR3_BARRIER_SHARED_W;
1082 break;
1083 case nir_intrinsic_group_memory_barrier:
1084 barrier = ir3_FENCE(b);
1085 barrier->cat7.g = true;
1086 barrier->cat7.l = true;
1087 barrier->cat7.r = true;
1088 barrier->cat7.w = true;
1089 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1090 IR3_BARRIER_IMAGE_W |
1091 IR3_BARRIER_BUFFER_W;
1092 barrier->barrier_conflict =
1093 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1094 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1095 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1096 break;
1097 default:
1098 unreachable("boo");
1099 }
1100
1101 /* make sure barrier doesn't get DCE'd */
1102 array_insert(b, b->keeps, barrier);
1103 }
1104
1105 static void add_sysval_input_compmask(struct ir3_context *ctx,
1106 gl_system_value slot, unsigned compmask,
1107 struct ir3_instruction *instr)
1108 {
1109 struct ir3_shader_variant *so = ctx->so;
1110 unsigned r = regid(so->inputs_count, 0);
1111 unsigned n = so->inputs_count++;
1112
1113 so->inputs[n].sysval = true;
1114 so->inputs[n].slot = slot;
1115 so->inputs[n].compmask = compmask;
1116 so->inputs[n].regid = r;
1117 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1118 so->total_in++;
1119
1120 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1121 ctx->ir->inputs[r] = instr;
1122 }
1123
1124 static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1125 struct ir3_instruction *instr)
1126 {
1127 add_sysval_input_compmask(ctx, slot, 0x1, instr);
1128 }
1129
1130 static void
1131 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1132 {
1133 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1134 struct ir3_instruction **dst;
1135 struct ir3_instruction * const *src;
1136 struct ir3_block *b = ctx->block;
1137 nir_const_value *const_offset;
1138 int idx, comp;
1139
1140 if (info->has_dest) {
1141 unsigned n = nir_intrinsic_dest_components(intr);
1142 dst = ir3_get_dst(ctx, &intr->dest, n);
1143 } else {
1144 dst = NULL;
1145 }
1146
1147 switch (intr->intrinsic) {
1148 case nir_intrinsic_load_uniform:
1149 idx = nir_intrinsic_base(intr);
1150 const_offset = nir_src_as_const_value(intr->src[0]);
1151 if (const_offset) {
1152 idx += const_offset->u32[0];
1153 for (int i = 0; i < intr->num_components; i++) {
1154 unsigned n = idx * 4 + i;
1155 dst[i] = create_uniform(b, n);
1156 }
1157 } else {
1158 src = ir3_get_src(ctx, &intr->src[0]);
1159 for (int i = 0; i < intr->num_components; i++) {
1160 int n = idx * 4 + i;
1161 dst[i] = create_uniform_indirect(b, n,
1162 ir3_get_addr(ctx, src[0], 4));
1163 }
1164 /* NOTE: if relative addressing is used, we set
1165 * constlen in the compiler (to worst-case value)
1166 * since we don't know in the assembler what the max
1167 * addr reg value can be:
1168 */
1169 ctx->so->constlen = ctx->s->num_uniforms;
1170 }
1171 break;
1172 case nir_intrinsic_load_ubo:
1173 emit_intrinsic_load_ubo(ctx, intr, dst);
1174 break;
1175 case nir_intrinsic_load_input:
1176 idx = nir_intrinsic_base(intr);
1177 comp = nir_intrinsic_component(intr);
1178 const_offset = nir_src_as_const_value(intr->src[0]);
1179 if (const_offset) {
1180 idx += const_offset->u32[0];
1181 for (int i = 0; i < intr->num_components; i++) {
1182 unsigned n = idx * 4 + i + comp;
1183 dst[i] = ctx->ir->inputs[n];
1184 }
1185 } else {
1186 src = ir3_get_src(ctx, &intr->src[0]);
1187 struct ir3_instruction *collect =
1188 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1189 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1190 for (int i = 0; i < intr->num_components; i++) {
1191 unsigned n = idx * 4 + i + comp;
1192 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1193 n, addr, collect);
1194 }
1195 }
1196 break;
1197 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1198 * pass and replaced by an ir3-specifc version that adds the
1199 * dword-offset in the last source.
1200 */
1201 case nir_intrinsic_load_ssbo_ir3:
1202 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1203 break;
1204 case nir_intrinsic_store_ssbo_ir3:
1205 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1206 break;
1207 case nir_intrinsic_get_buffer_size:
1208 emit_intrinsic_ssbo_size(ctx, intr, dst);
1209 break;
1210 case nir_intrinsic_ssbo_atomic_add_ir3:
1211 case nir_intrinsic_ssbo_atomic_imin_ir3:
1212 case nir_intrinsic_ssbo_atomic_umin_ir3:
1213 case nir_intrinsic_ssbo_atomic_imax_ir3:
1214 case nir_intrinsic_ssbo_atomic_umax_ir3:
1215 case nir_intrinsic_ssbo_atomic_and_ir3:
1216 case nir_intrinsic_ssbo_atomic_or_ir3:
1217 case nir_intrinsic_ssbo_atomic_xor_ir3:
1218 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1219 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1220 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1221 break;
1222 case nir_intrinsic_load_shared:
1223 emit_intrinsic_load_shared(ctx, intr, dst);
1224 break;
1225 case nir_intrinsic_store_shared:
1226 emit_intrinsic_store_shared(ctx, intr);
1227 break;
1228 case nir_intrinsic_shared_atomic_add:
1229 case nir_intrinsic_shared_atomic_imin:
1230 case nir_intrinsic_shared_atomic_umin:
1231 case nir_intrinsic_shared_atomic_imax:
1232 case nir_intrinsic_shared_atomic_umax:
1233 case nir_intrinsic_shared_atomic_and:
1234 case nir_intrinsic_shared_atomic_or:
1235 case nir_intrinsic_shared_atomic_xor:
1236 case nir_intrinsic_shared_atomic_exchange:
1237 case nir_intrinsic_shared_atomic_comp_swap:
1238 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1239 break;
1240 case nir_intrinsic_image_deref_load:
1241 emit_intrinsic_load_image(ctx, intr, dst);
1242 break;
1243 case nir_intrinsic_image_deref_store:
1244 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1245 break;
1246 case nir_intrinsic_image_deref_size:
1247 emit_intrinsic_image_size(ctx, intr, dst);
1248 break;
1249 case nir_intrinsic_image_deref_atomic_add:
1250 case nir_intrinsic_image_deref_atomic_min:
1251 case nir_intrinsic_image_deref_atomic_max:
1252 case nir_intrinsic_image_deref_atomic_and:
1253 case nir_intrinsic_image_deref_atomic_or:
1254 case nir_intrinsic_image_deref_atomic_xor:
1255 case nir_intrinsic_image_deref_atomic_exchange:
1256 case nir_intrinsic_image_deref_atomic_comp_swap:
1257 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1258 break;
1259 case nir_intrinsic_barrier:
1260 case nir_intrinsic_memory_barrier:
1261 case nir_intrinsic_group_memory_barrier:
1262 case nir_intrinsic_memory_barrier_atomic_counter:
1263 case nir_intrinsic_memory_barrier_buffer:
1264 case nir_intrinsic_memory_barrier_image:
1265 case nir_intrinsic_memory_barrier_shared:
1266 emit_intrinsic_barrier(ctx, intr);
1267 /* note that blk ptr no longer valid, make that obvious: */
1268 b = NULL;
1269 break;
1270 case nir_intrinsic_store_output:
1271 idx = nir_intrinsic_base(intr);
1272 comp = nir_intrinsic_component(intr);
1273 const_offset = nir_src_as_const_value(intr->src[1]);
1274 compile_assert(ctx, const_offset != NULL);
1275 idx += const_offset->u32[0];
1276
1277 src = ir3_get_src(ctx, &intr->src[0]);
1278 for (int i = 0; i < intr->num_components; i++) {
1279 unsigned n = idx * 4 + i + comp;
1280 ctx->ir->outputs[n] = src[i];
1281 }
1282 break;
1283 case nir_intrinsic_load_base_vertex:
1284 case nir_intrinsic_load_first_vertex:
1285 if (!ctx->basevertex) {
1286 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1287 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex);
1288 }
1289 dst[0] = ctx->basevertex;
1290 break;
1291 case nir_intrinsic_load_vertex_id_zero_base:
1292 case nir_intrinsic_load_vertex_id:
1293 if (!ctx->vertex_id) {
1294 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1295 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1296 ctx->vertex_id = create_input(ctx, 0);
1297 add_sysval_input(ctx, sv, ctx->vertex_id);
1298 }
1299 dst[0] = ctx->vertex_id;
1300 break;
1301 case nir_intrinsic_load_instance_id:
1302 if (!ctx->instance_id) {
1303 ctx->instance_id = create_input(ctx, 0);
1304 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID,
1305 ctx->instance_id);
1306 }
1307 dst[0] = ctx->instance_id;
1308 break;
1309 case nir_intrinsic_load_sample_id:
1310 case nir_intrinsic_load_sample_id_no_per_sample:
1311 if (!ctx->samp_id) {
1312 ctx->samp_id = create_input(ctx, 0);
1313 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1314 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID,
1315 ctx->samp_id);
1316 }
1317 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1318 break;
1319 case nir_intrinsic_load_sample_mask_in:
1320 if (!ctx->samp_mask_in) {
1321 ctx->samp_mask_in = create_input(ctx, 0);
1322 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN,
1323 ctx->samp_mask_in);
1324 }
1325 dst[0] = ctx->samp_mask_in;
1326 break;
1327 case nir_intrinsic_load_user_clip_plane:
1328 idx = nir_intrinsic_ucp_id(intr);
1329 for (int i = 0; i < intr->num_components; i++) {
1330 unsigned n = idx * 4 + i;
1331 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1332 }
1333 break;
1334 case nir_intrinsic_load_front_face:
1335 if (!ctx->frag_face) {
1336 ctx->so->frag_face = true;
1337 ctx->frag_face = create_input(ctx, 0);
1338 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face);
1339 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1340 }
1341 /* for fragface, we get -1 for back and 0 for front. However this is
1342 * the inverse of what nir expects (where ~0 is true).
1343 */
1344 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1345 dst[0] = ir3_NOT_B(b, dst[0], 0);
1346 break;
1347 case nir_intrinsic_load_local_invocation_id:
1348 if (!ctx->local_invocation_id) {
1349 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7);
1350 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID,
1351 0x7, ctx->local_invocation_id);
1352 }
1353 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1354 break;
1355 case nir_intrinsic_load_work_group_id:
1356 if (!ctx->work_group_id) {
1357 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7);
1358 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID,
1359 0x7, ctx->work_group_id);
1360 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1361 }
1362 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1363 break;
1364 case nir_intrinsic_load_num_work_groups:
1365 for (int i = 0; i < intr->num_components; i++) {
1366 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1367 }
1368 break;
1369 case nir_intrinsic_load_local_group_size:
1370 for (int i = 0; i < intr->num_components; i++) {
1371 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1372 }
1373 break;
1374 case nir_intrinsic_discard_if:
1375 case nir_intrinsic_discard: {
1376 struct ir3_instruction *cond, *kill;
1377
1378 if (intr->intrinsic == nir_intrinsic_discard_if) {
1379 /* conditional discard: */
1380 src = ir3_get_src(ctx, &intr->src[0]);
1381 cond = ir3_b2n(b, src[0]);
1382 } else {
1383 /* unconditional discard: */
1384 cond = create_immed(b, 1);
1385 }
1386
1387 /* NOTE: only cmps.*.* can write p0.x: */
1388 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1389 cond->cat2.condition = IR3_COND_NE;
1390
1391 /* condition always goes in predicate register: */
1392 cond->regs[0]->num = regid(REG_P0, 0);
1393
1394 kill = ir3_KILL(b, cond, 0);
1395 array_insert(ctx->ir, ctx->ir->predicates, kill);
1396
1397 array_insert(b, b->keeps, kill);
1398 ctx->so->has_kill = true;
1399
1400 break;
1401 }
1402 default:
1403 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1404 nir_intrinsic_infos[intr->intrinsic].name);
1405 break;
1406 }
1407
1408 if (info->has_dest)
1409 ir3_put_dst(ctx, &intr->dest);
1410 }
1411
1412 static void
1413 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1414 {
1415 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1416 instr->def.num_components);
1417 type_t type = (instr->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1418
1419 for (int i = 0; i < instr->def.num_components; i++)
1420 dst[i] = create_immed_typed(ctx->block, instr->value.u32[i], type);
1421 }
1422
1423 static void
1424 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1425 {
1426 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1427 undef->def.num_components);
1428 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1429
1430 /* backend doesn't want undefined instructions, so just plug
1431 * in 0.0..
1432 */
1433 for (int i = 0; i < undef->def.num_components; i++)
1434 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1435 }
1436
1437 /*
1438 * texture fetch/sample instructions:
1439 */
1440
1441 static void
1442 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1443 {
1444 unsigned coords, flags = 0;
1445
1446 /* note: would use tex->coord_components.. except txs.. also,
1447 * since array index goes after shadow ref, we don't want to
1448 * count it:
1449 */
1450 switch (tex->sampler_dim) {
1451 case GLSL_SAMPLER_DIM_1D:
1452 case GLSL_SAMPLER_DIM_BUF:
1453 coords = 1;
1454 break;
1455 case GLSL_SAMPLER_DIM_2D:
1456 case GLSL_SAMPLER_DIM_RECT:
1457 case GLSL_SAMPLER_DIM_EXTERNAL:
1458 case GLSL_SAMPLER_DIM_MS:
1459 coords = 2;
1460 break;
1461 case GLSL_SAMPLER_DIM_3D:
1462 case GLSL_SAMPLER_DIM_CUBE:
1463 coords = 3;
1464 flags |= IR3_INSTR_3D;
1465 break;
1466 default:
1467 unreachable("bad sampler_dim");
1468 }
1469
1470 if (tex->is_shadow && tex->op != nir_texop_lod)
1471 flags |= IR3_INSTR_S;
1472
1473 if (tex->is_array && tex->op != nir_texop_lod)
1474 flags |= IR3_INSTR_A;
1475
1476 *flagsp = flags;
1477 *coordsp = coords;
1478 }
1479
1480 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1481 * or immediate (in which case it will get lowered later to a non .s2en
1482 * version of the tex instruction which encode tex/samp as immediates:
1483 */
1484 static struct ir3_instruction *
1485 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1486 {
1487 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1488 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1489 struct ir3_instruction *texture, *sampler;
1490
1491 if (texture_idx >= 0) {
1492 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1493 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1494 } else {
1495 /* TODO what to do for dynamic case? I guess we only need the
1496 * max index for astc srgb workaround so maybe not a problem
1497 * to worry about if we don't enable indirect samplers for
1498 * a4xx?
1499 */
1500 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1501 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1502 }
1503
1504 if (sampler_idx >= 0) {
1505 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1506 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1507 } else {
1508 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1509 }
1510
1511 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1512 sampler,
1513 texture,
1514 }, 2);
1515 }
1516
1517 static void
1518 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1519 {
1520 struct ir3_block *b = ctx->block;
1521 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1522 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1523 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1524 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1525 unsigned i, coords, flags, ncomp;
1526 unsigned nsrc0 = 0, nsrc1 = 0;
1527 type_t type;
1528 opc_t opc = 0;
1529
1530 ncomp = nir_dest_num_components(tex->dest);
1531
1532 coord = off = ddx = ddy = NULL;
1533 lod = proj = compare = sample_index = NULL;
1534
1535 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1536
1537 for (unsigned i = 0; i < tex->num_srcs; i++) {
1538 switch (tex->src[i].src_type) {
1539 case nir_tex_src_coord:
1540 coord = ir3_get_src(ctx, &tex->src[i].src);
1541 break;
1542 case nir_tex_src_bias:
1543 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1544 has_bias = true;
1545 break;
1546 case nir_tex_src_lod:
1547 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1548 has_lod = true;
1549 break;
1550 case nir_tex_src_comparator: /* shadow comparator */
1551 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1552 break;
1553 case nir_tex_src_projector:
1554 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1555 has_proj = true;
1556 break;
1557 case nir_tex_src_offset:
1558 off = ir3_get_src(ctx, &tex->src[i].src);
1559 has_off = true;
1560 break;
1561 case nir_tex_src_ddx:
1562 ddx = ir3_get_src(ctx, &tex->src[i].src);
1563 break;
1564 case nir_tex_src_ddy:
1565 ddy = ir3_get_src(ctx, &tex->src[i].src);
1566 break;
1567 case nir_tex_src_ms_index:
1568 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1569 break;
1570 case nir_tex_src_texture_offset:
1571 case nir_tex_src_sampler_offset:
1572 /* handled in get_tex_samp_src() */
1573 break;
1574 default:
1575 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1576 tex->src[i].src_type);
1577 return;
1578 }
1579 }
1580
1581 switch (tex->op) {
1582 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1583 case nir_texop_txb: opc = OPC_SAMB; break;
1584 case nir_texop_txl: opc = OPC_SAML; break;
1585 case nir_texop_txd: opc = OPC_SAMGQ; break;
1586 case nir_texop_txf: opc = OPC_ISAML; break;
1587 case nir_texop_lod: opc = OPC_GETLOD; break;
1588 case nir_texop_tg4:
1589 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1590 * what blob does, seems gather is broken?), and a3xx did
1591 * not support it (but probably could also emulate).
1592 */
1593 switch (tex->component) {
1594 case 0: opc = OPC_GATHER4R; break;
1595 case 1: opc = OPC_GATHER4G; break;
1596 case 2: opc = OPC_GATHER4B; break;
1597 case 3: opc = OPC_GATHER4A; break;
1598 }
1599 break;
1600 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
1601 case nir_texop_txs:
1602 case nir_texop_query_levels:
1603 case nir_texop_texture_samples:
1604 case nir_texop_samples_identical:
1605 case nir_texop_txf_ms_mcs:
1606 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1607 return;
1608 }
1609
1610 tex_info(tex, &flags, &coords);
1611
1612 /*
1613 * lay out the first argument in the proper order:
1614 * - actual coordinates first
1615 * - shadow reference
1616 * - array index
1617 * - projection w
1618 * - starting at offset 4, dpdx.xy, dpdy.xy
1619 *
1620 * bias/lod go into the second arg
1621 */
1622
1623 /* insert tex coords: */
1624 for (i = 0; i < coords; i++)
1625 src0[i] = coord[i];
1626
1627 nsrc0 = i;
1628
1629 /* scale up integer coords for TXF based on the LOD */
1630 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
1631 assert(has_lod);
1632 for (i = 0; i < coords; i++)
1633 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
1634 }
1635
1636 if (coords == 1) {
1637 /* hw doesn't do 1d, so we treat it as 2d with
1638 * height of 1, and patch up the y coord.
1639 */
1640 if (is_isam(opc)) {
1641 src0[nsrc0++] = create_immed(b, 0);
1642 } else {
1643 src0[nsrc0++] = create_immed(b, fui(0.5));
1644 }
1645 }
1646
1647 if (tex->is_shadow && tex->op != nir_texop_lod)
1648 src0[nsrc0++] = compare;
1649
1650 if (tex->is_array && tex->op != nir_texop_lod) {
1651 struct ir3_instruction *idx = coord[coords];
1652
1653 /* the array coord for cube arrays needs 0.5 added to it */
1654 if (ctx->compiler->array_index_add_half && !is_isam(opc))
1655 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
1656
1657 src0[nsrc0++] = idx;
1658 }
1659
1660 if (has_proj) {
1661 src0[nsrc0++] = proj;
1662 flags |= IR3_INSTR_P;
1663 }
1664
1665 /* pad to 4, then ddx/ddy: */
1666 if (tex->op == nir_texop_txd) {
1667 while (nsrc0 < 4)
1668 src0[nsrc0++] = create_immed(b, fui(0.0));
1669 for (i = 0; i < coords; i++)
1670 src0[nsrc0++] = ddx[i];
1671 if (coords < 2)
1672 src0[nsrc0++] = create_immed(b, fui(0.0));
1673 for (i = 0; i < coords; i++)
1674 src0[nsrc0++] = ddy[i];
1675 if (coords < 2)
1676 src0[nsrc0++] = create_immed(b, fui(0.0));
1677 }
1678
1679 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1680 * with scaled x coord according to requested sample:
1681 */
1682 if (tex->op == nir_texop_txf_ms) {
1683 if (ctx->compiler->txf_ms_with_isaml) {
1684 /* the samples are laid out in x dimension as
1685 * 0 1 2 3
1686 * x_ms = (x << ms) + sample_index;
1687 */
1688 struct ir3_instruction *ms;
1689 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
1690
1691 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
1692 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
1693
1694 opc = OPC_ISAML;
1695 } else {
1696 src0[nsrc0++] = sample_index;
1697 }
1698 }
1699
1700 /*
1701 * second argument (if applicable):
1702 * - offsets
1703 * - lod
1704 * - bias
1705 */
1706 if (has_off | has_lod | has_bias) {
1707 if (has_off) {
1708 unsigned off_coords = coords;
1709 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
1710 off_coords--;
1711 for (i = 0; i < off_coords; i++)
1712 src1[nsrc1++] = off[i];
1713 if (off_coords < 2)
1714 src1[nsrc1++] = create_immed(b, fui(0.0));
1715 flags |= IR3_INSTR_O;
1716 }
1717
1718 if (has_lod | has_bias)
1719 src1[nsrc1++] = lod;
1720 }
1721
1722 switch (tex->dest_type) {
1723 case nir_type_invalid:
1724 case nir_type_float:
1725 type = TYPE_F32;
1726 break;
1727 case nir_type_int:
1728 type = TYPE_S32;
1729 break;
1730 case nir_type_uint:
1731 case nir_type_bool:
1732 type = TYPE_U32;
1733 break;
1734 default:
1735 unreachable("bad dest_type");
1736 }
1737
1738 if (opc == OPC_GETLOD)
1739 type = TYPE_U32;
1740
1741 struct ir3_instruction *samp_tex = get_tex_samp_tex_src(ctx, tex);
1742 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
1743 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
1744
1745 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
1746 samp_tex, col0, col1);
1747
1748 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
1749 /* only need first 3 components: */
1750 sam->regs[0]->wrmask = 0x7;
1751 ir3_split_dest(b, dst, sam, 0, 3);
1752
1753 /* we need to sample the alpha separately with a non-ASTC
1754 * texture state:
1755 */
1756 sam = ir3_SAM(b, opc, type, 0b1000, flags,
1757 samp_tex, col0, col1);
1758
1759 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
1760
1761 /* fixup .w component: */
1762 ir3_split_dest(b, &dst[3], sam, 3, 1);
1763 } else {
1764 /* normal (non-workaround) case: */
1765 ir3_split_dest(b, dst, sam, 0, ncomp);
1766 }
1767
1768 /* GETLOD returns results in 4.8 fixed point */
1769 if (opc == OPC_GETLOD) {
1770 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
1771
1772 compile_assert(ctx, tex->dest_type == nir_type_float);
1773 for (i = 0; i < 2; i++) {
1774 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_U32, TYPE_F32), 0,
1775 factor, 0);
1776 }
1777 }
1778
1779 ir3_put_dst(ctx, &tex->dest);
1780 }
1781
1782 static void
1783 emit_tex_query_levels(struct ir3_context *ctx, nir_tex_instr *tex)
1784 {
1785 struct ir3_block *b = ctx->block;
1786 struct ir3_instruction **dst, *sam;
1787
1788 dst = ir3_get_dst(ctx, &tex->dest, 1);
1789
1790 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 0b0100, 0,
1791 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
1792
1793 /* even though there is only one component, since it ends
1794 * up in .z rather than .x, we need a split_dest()
1795 */
1796 ir3_split_dest(b, dst, sam, 0, 3);
1797
1798 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1799 * the value in TEX_CONST_0 is zero-based.
1800 */
1801 if (ctx->compiler->levels_add_one)
1802 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
1803
1804 ir3_put_dst(ctx, &tex->dest);
1805 }
1806
1807 static void
1808 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
1809 {
1810 struct ir3_block *b = ctx->block;
1811 struct ir3_instruction **dst, *sam;
1812 struct ir3_instruction *lod;
1813 unsigned flags, coords;
1814
1815 tex_info(tex, &flags, &coords);
1816
1817 /* Actually we want the number of dimensions, not coordinates. This
1818 * distinction only matters for cubes.
1819 */
1820 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
1821 coords = 2;
1822
1823 dst = ir3_get_dst(ctx, &tex->dest, 4);
1824
1825 compile_assert(ctx, tex->num_srcs == 1);
1826 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
1827
1828 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
1829
1830 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
1831 get_tex_samp_tex_src(ctx, tex), lod, NULL);
1832
1833 ir3_split_dest(b, dst, sam, 0, 4);
1834
1835 /* Array size actually ends up in .w rather than .z. This doesn't
1836 * matter for miplevel 0, but for higher mips the value in z is
1837 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1838 * returned, which means that we have to add 1 to it for arrays.
1839 */
1840 if (tex->is_array) {
1841 if (ctx->compiler->levels_add_one) {
1842 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
1843 } else {
1844 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
1845 }
1846 }
1847
1848 ir3_put_dst(ctx, &tex->dest);
1849 }
1850
1851 static void
1852 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
1853 {
1854 switch (jump->type) {
1855 case nir_jump_break:
1856 case nir_jump_continue:
1857 case nir_jump_return:
1858 /* I *think* we can simply just ignore this, and use the
1859 * successor block link to figure out where we need to
1860 * jump to for break/continue
1861 */
1862 break;
1863 default:
1864 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
1865 break;
1866 }
1867 }
1868
1869 static void
1870 emit_instr(struct ir3_context *ctx, nir_instr *instr)
1871 {
1872 switch (instr->type) {
1873 case nir_instr_type_alu:
1874 emit_alu(ctx, nir_instr_as_alu(instr));
1875 break;
1876 case nir_instr_type_deref:
1877 /* ignored, handled as part of the intrinsic they are src to */
1878 break;
1879 case nir_instr_type_intrinsic:
1880 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1881 break;
1882 case nir_instr_type_load_const:
1883 emit_load_const(ctx, nir_instr_as_load_const(instr));
1884 break;
1885 case nir_instr_type_ssa_undef:
1886 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
1887 break;
1888 case nir_instr_type_tex: {
1889 nir_tex_instr *tex = nir_instr_as_tex(instr);
1890 /* couple tex instructions get special-cased:
1891 */
1892 switch (tex->op) {
1893 case nir_texop_txs:
1894 emit_tex_txs(ctx, tex);
1895 break;
1896 case nir_texop_query_levels:
1897 emit_tex_query_levels(ctx, tex);
1898 break;
1899 default:
1900 emit_tex(ctx, tex);
1901 break;
1902 }
1903 break;
1904 }
1905 case nir_instr_type_jump:
1906 emit_jump(ctx, nir_instr_as_jump(instr));
1907 break;
1908 case nir_instr_type_phi:
1909 /* we have converted phi webs to regs in NIR by now */
1910 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
1911 break;
1912 case nir_instr_type_call:
1913 case nir_instr_type_parallel_copy:
1914 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
1915 break;
1916 }
1917 }
1918
1919 static struct ir3_block *
1920 get_block(struct ir3_context *ctx, const nir_block *nblock)
1921 {
1922 struct ir3_block *block;
1923 struct hash_entry *hentry;
1924 unsigned i;
1925
1926 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
1927 if (hentry)
1928 return hentry->data;
1929
1930 block = ir3_block_create(ctx->ir);
1931 block->nblock = nblock;
1932 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
1933
1934 block->predecessors_count = nblock->predecessors->entries;
1935 block->predecessors = ralloc_array_size(block,
1936 sizeof(block->predecessors[0]), block->predecessors_count);
1937 i = 0;
1938 set_foreach(nblock->predecessors, sentry) {
1939 block->predecessors[i++] = get_block(ctx, sentry->key);
1940 }
1941
1942 return block;
1943 }
1944
1945 static void
1946 emit_block(struct ir3_context *ctx, nir_block *nblock)
1947 {
1948 struct ir3_block *block = get_block(ctx, nblock);
1949
1950 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
1951 if (nblock->successors[i]) {
1952 block->successors[i] =
1953 get_block(ctx, nblock->successors[i]);
1954 }
1955 }
1956
1957 ctx->block = block;
1958 list_addtail(&block->node, &ctx->ir->block_list);
1959
1960 /* re-emit addr register in each block if needed: */
1961 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
1962 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
1963 ctx->addr_ht[i] = NULL;
1964 }
1965
1966 nir_foreach_instr(instr, nblock) {
1967 ctx->cur_instr = instr;
1968 emit_instr(ctx, instr);
1969 ctx->cur_instr = NULL;
1970 if (ctx->error)
1971 return;
1972 }
1973 }
1974
1975 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
1976
1977 static void
1978 emit_if(struct ir3_context *ctx, nir_if *nif)
1979 {
1980 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
1981
1982 ctx->block->condition =
1983 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
1984
1985 emit_cf_list(ctx, &nif->then_list);
1986 emit_cf_list(ctx, &nif->else_list);
1987 }
1988
1989 static void
1990 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
1991 {
1992 emit_cf_list(ctx, &nloop->body);
1993 }
1994
1995 static void
1996 stack_push(struct ir3_context *ctx)
1997 {
1998 ctx->stack++;
1999 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2000 }
2001
2002 static void
2003 stack_pop(struct ir3_context *ctx)
2004 {
2005 compile_assert(ctx, ctx->stack > 0);
2006 ctx->stack--;
2007 }
2008
2009 static void
2010 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2011 {
2012 foreach_list_typed(nir_cf_node, node, node, list) {
2013 switch (node->type) {
2014 case nir_cf_node_block:
2015 emit_block(ctx, nir_cf_node_as_block(node));
2016 break;
2017 case nir_cf_node_if:
2018 stack_push(ctx);
2019 emit_if(ctx, nir_cf_node_as_if(node));
2020 stack_pop(ctx);
2021 break;
2022 case nir_cf_node_loop:
2023 stack_push(ctx);
2024 emit_loop(ctx, nir_cf_node_as_loop(node));
2025 stack_pop(ctx);
2026 break;
2027 case nir_cf_node_function:
2028 ir3_context_error(ctx, "TODO\n");
2029 break;
2030 }
2031 }
2032 }
2033
2034 /* emit stream-out code. At this point, the current block is the original
2035 * (nir) end block, and nir ensures that all flow control paths terminate
2036 * into the end block. We re-purpose the original end block to generate
2037 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2038 * block holding stream-out write instructions, followed by the new end
2039 * block:
2040 *
2041 * blockOrigEnd {
2042 * p0.x = (vtxcnt < maxvtxcnt)
2043 * // succs: blockStreamOut, blockNewEnd
2044 * }
2045 * blockStreamOut {
2046 * ... stream-out instructions ...
2047 * // succs: blockNewEnd
2048 * }
2049 * blockNewEnd {
2050 * }
2051 */
2052 static void
2053 emit_stream_out(struct ir3_context *ctx)
2054 {
2055 struct ir3_shader_variant *v = ctx->so;
2056 struct ir3 *ir = ctx->ir;
2057 struct ir3_stream_output_info *strmout =
2058 &ctx->so->shader->stream_output;
2059 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2060 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2061 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2062
2063 /* create vtxcnt input in input block at top of shader,
2064 * so that it is seen as live over the entire duration
2065 * of the shader:
2066 */
2067 vtxcnt = create_input(ctx, 0);
2068 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt);
2069
2070 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2071
2072 /* at this point, we are at the original 'end' block,
2073 * re-purpose this block to stream-out condition, then
2074 * append stream-out block and new-end block
2075 */
2076 orig_end_block = ctx->block;
2077
2078 // TODO these blocks need to update predecessors..
2079 // maybe w/ store_global intrinsic, we could do this
2080 // stuff in nir->nir pass
2081
2082 stream_out_block = ir3_block_create(ir);
2083 list_addtail(&stream_out_block->node, &ir->block_list);
2084
2085 new_end_block = ir3_block_create(ir);
2086 list_addtail(&new_end_block->node, &ir->block_list);
2087
2088 orig_end_block->successors[0] = stream_out_block;
2089 orig_end_block->successors[1] = new_end_block;
2090 stream_out_block->successors[0] = new_end_block;
2091
2092 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2093 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2094 cond->regs[0]->num = regid(REG_P0, 0);
2095 cond->cat2.condition = IR3_COND_LT;
2096
2097 /* condition goes on previous block to the conditional,
2098 * since it is used to pick which of the two successor
2099 * paths to take:
2100 */
2101 orig_end_block->condition = cond;
2102
2103 /* switch to stream_out_block to generate the stream-out
2104 * instructions:
2105 */
2106 ctx->block = stream_out_block;
2107
2108 /* Calculate base addresses based on vtxcnt. Instructions
2109 * generated for bases not used in following loop will be
2110 * stripped out in the backend.
2111 */
2112 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2113 unsigned stride = strmout->stride[i];
2114 struct ir3_instruction *base, *off;
2115
2116 base = create_uniform(ctx->block, regid(v->constbase.tfbo, i));
2117
2118 /* 24-bit should be enough: */
2119 off = ir3_MUL_U(ctx->block, vtxcnt, 0,
2120 create_immed(ctx->block, stride * 4), 0);
2121
2122 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2123 }
2124
2125 /* Generate the per-output store instructions: */
2126 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2127 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2128 unsigned c = j + strmout->output[i].start_component;
2129 struct ir3_instruction *base, *out, *stg;
2130
2131 base = bases[strmout->output[i].output_buffer];
2132 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2133
2134 stg = ir3_STG(ctx->block, base, 0, out, 0,
2135 create_immed(ctx->block, 1), 0);
2136 stg->cat6.type = TYPE_U32;
2137 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2138
2139 array_insert(ctx->block, ctx->block->keeps, stg);
2140 }
2141 }
2142
2143 /* and finally switch to the new_end_block: */
2144 ctx->block = new_end_block;
2145 }
2146
2147 static void
2148 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2149 {
2150 nir_metadata_require(impl, nir_metadata_block_index);
2151
2152 compile_assert(ctx, ctx->stack == 0);
2153
2154 emit_cf_list(ctx, &impl->body);
2155 emit_block(ctx, impl->end_block);
2156
2157 compile_assert(ctx, ctx->stack == 0);
2158
2159 /* at this point, we should have a single empty block,
2160 * into which we emit the 'end' instruction.
2161 */
2162 compile_assert(ctx, list_empty(&ctx->block->instr_list));
2163
2164 /* If stream-out (aka transform-feedback) enabled, emit the
2165 * stream-out instructions, followed by a new empty block (into
2166 * which the 'end' instruction lands).
2167 *
2168 * NOTE: it is done in this order, rather than inserting before
2169 * we emit end_block, because NIR guarantees that all blocks
2170 * flow into end_block, and that end_block has no successors.
2171 * So by re-purposing end_block as the first block of stream-
2172 * out, we guarantee that all exit paths flow into the stream-
2173 * out instructions.
2174 */
2175 if ((ctx->compiler->gpu_id < 500) &&
2176 (ctx->so->shader->stream_output.num_outputs > 0) &&
2177 !ctx->so->binning_pass) {
2178 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2179 emit_stream_out(ctx);
2180 }
2181
2182 ir3_END(ctx->block);
2183 }
2184
2185 static struct ir3_instruction *
2186 create_frag_coord(struct ir3_context *ctx, unsigned comp)
2187 {
2188 struct ir3_block *block = ctx->block;
2189 struct ir3_instruction *instr;
2190
2191 if (!ctx->frag_coord) {
2192 ctx->frag_coord = create_input_compmask(ctx, 0, 0xf);
2193 /* defer add_sysval_input() until after all inputs created */
2194 }
2195
2196 ir3_split_dest(block, &instr, ctx->frag_coord, comp, 1);
2197
2198 switch (comp) {
2199 case 0: /* .x */
2200 case 1: /* .y */
2201 /* for frag_coord, we get unsigned values.. we need
2202 * to subtract (integer) 8 and divide by 16 (right-
2203 * shift by 4) then convert to float:
2204 *
2205 * sub.s tmp, src, 8
2206 * shr.b tmp, tmp, 4
2207 * mov.u32f32 dst, tmp
2208 *
2209 */
2210 instr = ir3_SUB_S(block, instr, 0,
2211 create_immed(block, 8), 0);
2212 instr = ir3_SHR_B(block, instr, 0,
2213 create_immed(block, 4), 0);
2214 instr = ir3_COV(block, instr, TYPE_U32, TYPE_F32);
2215
2216 return instr;
2217 case 2: /* .z */
2218 case 3: /* .w */
2219 default:
2220 /* seems that we can use these as-is: */
2221 return instr;
2222 }
2223 }
2224
2225 static void
2226 setup_input(struct ir3_context *ctx, nir_variable *in)
2227 {
2228 struct ir3_shader_variant *so = ctx->so;
2229 unsigned ncomp = glsl_get_components(in->type);
2230 unsigned n = in->data.driver_location;
2231 unsigned frac = in->data.location_frac;
2232 unsigned slot = in->data.location;
2233
2234 /* skip unread inputs, we could end up with (for example), unsplit
2235 * matrix/etc inputs in the case they are not read, so just silently
2236 * skip these.
2237 */
2238 if (ncomp > 4)
2239 return;
2240
2241 so->inputs[n].slot = slot;
2242 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2243 so->inputs_count = MAX2(so->inputs_count, n + 1);
2244 so->inputs[n].interpolate = in->data.interpolation;
2245
2246 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2247 for (int i = 0; i < ncomp; i++) {
2248 struct ir3_instruction *instr = NULL;
2249 unsigned idx = (n * 4) + i + frac;
2250
2251 if (slot == VARYING_SLOT_POS) {
2252 so->inputs[n].bary = false;
2253 so->frag_coord = true;
2254 instr = create_frag_coord(ctx, i);
2255 } else if (slot == VARYING_SLOT_PNTC) {
2256 /* see for example st_nir_fixup_varying_slots().. this is
2257 * maybe a bit mesa/st specific. But we need things to line
2258 * up for this in fdN_program:
2259 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2260 * if (emit->sprite_coord_enable & texmask) {
2261 * ...
2262 * }
2263 */
2264 so->inputs[n].slot = VARYING_SLOT_VAR8;
2265 so->inputs[n].bary = true;
2266 instr = create_frag_input(ctx, false);
2267 } else {
2268 bool use_ldlv = false;
2269
2270 /* detect the special case for front/back colors where
2271 * we need to do flat vs smooth shading depending on
2272 * rast state:
2273 */
2274 if (in->data.interpolation == INTERP_MODE_NONE) {
2275 switch (slot) {
2276 case VARYING_SLOT_COL0:
2277 case VARYING_SLOT_COL1:
2278 case VARYING_SLOT_BFC0:
2279 case VARYING_SLOT_BFC1:
2280 so->inputs[n].rasterflat = true;
2281 break;
2282 default:
2283 break;
2284 }
2285 }
2286
2287 if (ctx->compiler->flat_bypass) {
2288 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2289 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2290 use_ldlv = true;
2291 }
2292
2293 so->inputs[n].bary = true;
2294
2295 instr = create_frag_input(ctx, use_ldlv);
2296 }
2297
2298 compile_assert(ctx, idx < ctx->ir->ninputs);
2299
2300 ctx->ir->inputs[idx] = instr;
2301 }
2302 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2303 for (int i = 0; i < ncomp; i++) {
2304 unsigned idx = (n * 4) + i + frac;
2305 compile_assert(ctx, idx < ctx->ir->ninputs);
2306 ctx->ir->inputs[idx] = create_input(ctx, idx);
2307 }
2308 } else {
2309 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2310 }
2311
2312 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2313 so->total_in += ncomp;
2314 }
2315 }
2316
2317 static void
2318 setup_output(struct ir3_context *ctx, nir_variable *out)
2319 {
2320 struct ir3_shader_variant *so = ctx->so;
2321 unsigned ncomp = glsl_get_components(out->type);
2322 unsigned n = out->data.driver_location;
2323 unsigned frac = out->data.location_frac;
2324 unsigned slot = out->data.location;
2325 unsigned comp = 0;
2326
2327 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2328 switch (slot) {
2329 case FRAG_RESULT_DEPTH:
2330 comp = 2; /* tgsi will write to .z component */
2331 so->writes_pos = true;
2332 break;
2333 case FRAG_RESULT_COLOR:
2334 so->color0_mrt = 1;
2335 break;
2336 default:
2337 if (slot >= FRAG_RESULT_DATA0)
2338 break;
2339 ir3_context_error(ctx, "unknown FS output name: %s\n",
2340 gl_frag_result_name(slot));
2341 }
2342 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2343 switch (slot) {
2344 case VARYING_SLOT_POS:
2345 so->writes_pos = true;
2346 break;
2347 case VARYING_SLOT_PSIZ:
2348 so->writes_psize = true;
2349 break;
2350 case VARYING_SLOT_COL0:
2351 case VARYING_SLOT_COL1:
2352 case VARYING_SLOT_BFC0:
2353 case VARYING_SLOT_BFC1:
2354 case VARYING_SLOT_FOGC:
2355 case VARYING_SLOT_CLIP_DIST0:
2356 case VARYING_SLOT_CLIP_DIST1:
2357 case VARYING_SLOT_CLIP_VERTEX:
2358 break;
2359 default:
2360 if (slot >= VARYING_SLOT_VAR0)
2361 break;
2362 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2363 break;
2364 ir3_context_error(ctx, "unknown VS output name: %s\n",
2365 gl_varying_slot_name(slot));
2366 }
2367 } else {
2368 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2369 }
2370
2371 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2372
2373 so->outputs[n].slot = slot;
2374 so->outputs[n].regid = regid(n, comp);
2375 so->outputs_count = MAX2(so->outputs_count, n + 1);
2376
2377 for (int i = 0; i < ncomp; i++) {
2378 unsigned idx = (n * 4) + i + frac;
2379 compile_assert(ctx, idx < ctx->ir->noutputs);
2380 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2381 }
2382
2383 /* if varying packing doesn't happen, we could end up in a situation
2384 * with "holes" in the output, and since the per-generation code that
2385 * sets up varying linkage registers doesn't expect to have more than
2386 * one varying per vec4 slot, pad the holes.
2387 *
2388 * Note that this should probably generate a performance warning of
2389 * some sort.
2390 */
2391 for (int i = 0; i < frac; i++) {
2392 unsigned idx = (n * 4) + i;
2393 if (!ctx->ir->outputs[idx]) {
2394 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2395 }
2396 }
2397 }
2398
2399 static int
2400 max_drvloc(struct exec_list *vars)
2401 {
2402 int drvloc = -1;
2403 nir_foreach_variable(var, vars) {
2404 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2405 }
2406 return drvloc;
2407 }
2408
2409 static const unsigned max_sysvals[] = {
2410 [MESA_SHADER_FRAGMENT] = 24, // TODO
2411 [MESA_SHADER_VERTEX] = 16,
2412 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2413 [MESA_SHADER_KERNEL] = 16, // TODO how many do we actually need?
2414 };
2415
2416 static void
2417 emit_instructions(struct ir3_context *ctx)
2418 {
2419 unsigned ninputs, noutputs;
2420 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2421
2422 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2423 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2424
2425 /* we need to leave room for sysvals:
2426 */
2427 ninputs += max_sysvals[ctx->so->type];
2428
2429 ctx->ir = ir3_create(ctx->compiler, ninputs, noutputs);
2430
2431 /* Create inputs in first block: */
2432 ctx->block = get_block(ctx, nir_start_block(fxn));
2433 ctx->in_block = ctx->block;
2434 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2435
2436 ninputs -= max_sysvals[ctx->so->type];
2437
2438 /* for fragment shader, the vcoord input register is used as the
2439 * base for bary.f varying fetch instrs:
2440 */
2441 struct ir3_instruction *vcoord = NULL;
2442 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2443 struct ir3_instruction *xy[2];
2444
2445 vcoord = create_input_compmask(ctx, 0, 0x3);
2446 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2447
2448 ctx->frag_vcoord = ir3_create_collect(ctx, xy, 2);
2449 }
2450
2451 /* Setup inputs: */
2452 nir_foreach_variable(var, &ctx->s->inputs) {
2453 setup_input(ctx, var);
2454 }
2455
2456 /* Defer add_sysval_input() stuff until after setup_inputs(),
2457 * because sysvals need to be appended after varyings:
2458 */
2459 if (vcoord) {
2460 add_sysval_input_compmask(ctx, SYSTEM_VALUE_VARYING_COORD,
2461 0x3, vcoord);
2462 }
2463
2464 if (ctx->frag_coord) {
2465 add_sysval_input_compmask(ctx, SYSTEM_VALUE_FRAG_COORD,
2466 0xf, ctx->frag_coord);
2467 }
2468
2469 /* Setup outputs: */
2470 nir_foreach_variable(var, &ctx->s->outputs) {
2471 setup_output(ctx, var);
2472 }
2473
2474 /* Find # of samplers: */
2475 nir_foreach_variable(var, &ctx->s->uniforms) {
2476 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
2477 /* just assume that we'll be reading from images.. if it
2478 * is write-only we don't have to count it, but not sure
2479 * if there is a good way to know?
2480 */
2481 ctx->so->num_samp += glsl_type_get_image_count(var->type);
2482 }
2483
2484 /* Setup registers (which should only be arrays): */
2485 nir_foreach_register(reg, &ctx->s->registers) {
2486 ir3_declare_array(ctx, reg);
2487 }
2488
2489 /* NOTE: need to do something more clever when we support >1 fxn */
2490 nir_foreach_register(reg, &fxn->registers) {
2491 ir3_declare_array(ctx, reg);
2492 }
2493 /* And emit the body: */
2494 ctx->impl = fxn;
2495 emit_function(ctx, fxn);
2496 }
2497
2498 /* from NIR perspective, we actually have varying inputs. But the varying
2499 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2500 * only actual inputs are the sysvals.
2501 */
2502 static void
2503 fixup_frag_inputs(struct ir3_context *ctx)
2504 {
2505 struct ir3_shader_variant *so = ctx->so;
2506 struct ir3 *ir = ctx->ir;
2507 unsigned i = 0;
2508
2509 /* sysvals should appear at the end of the inputs, drop everything else: */
2510 while ((i < so->inputs_count) && !so->inputs[i].sysval)
2511 i++;
2512
2513 /* at IR level, inputs are always blocks of 4 scalars: */
2514 i *= 4;
2515
2516 ir->inputs = &ir->inputs[i];
2517 ir->ninputs -= i;
2518 }
2519
2520 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2521 * need to assign the tex state indexes for these after we know the
2522 * max tex index.
2523 */
2524 static void
2525 fixup_astc_srgb(struct ir3_context *ctx)
2526 {
2527 struct ir3_shader_variant *so = ctx->so;
2528 /* indexed by original tex idx, value is newly assigned alpha sampler
2529 * state tex idx. Zero is invalid since there is at least one sampler
2530 * if we get here.
2531 */
2532 unsigned alt_tex_state[16] = {0};
2533 unsigned tex_idx = ctx->max_texture_index + 1;
2534 unsigned idx = 0;
2535
2536 so->astc_srgb.base = tex_idx;
2537
2538 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
2539 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
2540
2541 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
2542
2543 if (alt_tex_state[sam->cat5.tex] == 0) {
2544 /* assign new alternate/alpha tex state slot: */
2545 alt_tex_state[sam->cat5.tex] = tex_idx++;
2546 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
2547 so->astc_srgb.count++;
2548 }
2549
2550 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
2551 }
2552 }
2553
2554 static void
2555 fixup_binning_pass(struct ir3_context *ctx)
2556 {
2557 struct ir3_shader_variant *so = ctx->so;
2558 struct ir3 *ir = ctx->ir;
2559 unsigned i, j;
2560
2561 for (i = 0, j = 0; i < so->outputs_count; i++) {
2562 unsigned slot = so->outputs[i].slot;
2563
2564 /* throw away everything but first position/psize */
2565 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
2566 if (i != j) {
2567 so->outputs[j] = so->outputs[i];
2568 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
2569 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
2570 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
2571 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
2572 }
2573 j++;
2574 }
2575 }
2576 so->outputs_count = j;
2577 ir->noutputs = j * 4;
2578 }
2579
2580 int
2581 ir3_compile_shader_nir(struct ir3_compiler *compiler,
2582 struct ir3_shader_variant *so)
2583 {
2584 struct ir3_context *ctx;
2585 struct ir3 *ir;
2586 struct ir3_instruction **inputs;
2587 unsigned i, actual_in, inloc;
2588 int ret = 0, max_bary;
2589
2590 assert(!so->ir);
2591
2592 ctx = ir3_context_init(compiler, so);
2593 if (!ctx) {
2594 DBG("INIT failed!");
2595 ret = -1;
2596 goto out;
2597 }
2598
2599 emit_instructions(ctx);
2600
2601 if (ctx->error) {
2602 DBG("EMIT failed!");
2603 ret = -1;
2604 goto out;
2605 }
2606
2607 ir = so->ir = ctx->ir;
2608
2609 /* keep track of the inputs from TGSI perspective.. */
2610 inputs = ir->inputs;
2611
2612 /* but fixup actual inputs for frag shader: */
2613 if (so->type == MESA_SHADER_FRAGMENT)
2614 fixup_frag_inputs(ctx);
2615
2616 /* at this point, for binning pass, throw away unneeded outputs: */
2617 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
2618 fixup_binning_pass(ctx);
2619
2620 /* if we want half-precision outputs, mark the output registers
2621 * as half:
2622 */
2623 if (so->key.half_precision) {
2624 for (i = 0; i < ir->noutputs; i++) {
2625 struct ir3_instruction *out = ir->outputs[i];
2626
2627 if (!out)
2628 continue;
2629
2630 /* if frag shader writes z, that needs to be full precision: */
2631 if (so->outputs[i/4].slot == FRAG_RESULT_DEPTH)
2632 continue;
2633
2634 out->regs[0]->flags |= IR3_REG_HALF;
2635 /* output could be a fanout (ie. texture fetch output)
2636 * in which case we need to propagate the half-reg flag
2637 * up to the definer so that RA sees it:
2638 */
2639 if (out->opc == OPC_META_FO) {
2640 out = out->regs[1]->instr;
2641 out->regs[0]->flags |= IR3_REG_HALF;
2642 }
2643
2644 if (out->opc == OPC_MOV) {
2645 out->cat1.dst_type = half_type(out->cat1.dst_type);
2646 }
2647 }
2648 }
2649
2650 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2651 printf("BEFORE CP:\n");
2652 ir3_print(ir);
2653 }
2654
2655 ir3_cp(ir, so);
2656
2657 /* at this point, for binning pass, throw away unneeded outputs:
2658 * Note that for a6xx and later, we do this after ir3_cp to ensure
2659 * that the uniform/constant layout for BS and VS matches, so that
2660 * we can re-use same VS_CONST state group.
2661 */
2662 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
2663 fixup_binning_pass(ctx);
2664
2665 /* Insert mov if there's same instruction for each output.
2666 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
2667 */
2668 for (int i = ir->noutputs - 1; i >= 0; i--) {
2669 if (!ir->outputs[i])
2670 continue;
2671 for (unsigned j = 0; j < i; j++) {
2672 if (ir->outputs[i] == ir->outputs[j]) {
2673 ir->outputs[i] =
2674 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
2675 }
2676 }
2677 }
2678
2679 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2680 printf("BEFORE GROUPING:\n");
2681 ir3_print(ir);
2682 }
2683
2684 ir3_sched_add_deps(ir);
2685
2686 /* Group left/right neighbors, inserting mov's where needed to
2687 * solve conflicts:
2688 */
2689 ir3_group(ir);
2690
2691 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2692 printf("AFTER GROUPING:\n");
2693 ir3_print(ir);
2694 }
2695
2696 ir3_depth(ir);
2697
2698 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2699 printf("AFTER DEPTH:\n");
2700 ir3_print(ir);
2701 }
2702
2703 /* do Sethi–Ullman numbering before scheduling: */
2704 ir3_sun(ir);
2705
2706 ret = ir3_sched(ir);
2707 if (ret) {
2708 DBG("SCHED failed!");
2709 goto out;
2710 }
2711
2712 if (compiler->gpu_id >= 600) {
2713 ir3_a6xx_fixup_atomic_dests(ir, so);
2714 }
2715
2716 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2717 printf("AFTER SCHED:\n");
2718 ir3_print(ir);
2719 }
2720
2721 ret = ir3_ra(ir, so->type, so->frag_coord, so->frag_face);
2722 if (ret) {
2723 DBG("RA failed!");
2724 goto out;
2725 }
2726
2727 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2728 printf("AFTER RA:\n");
2729 ir3_print(ir);
2730 }
2731
2732 /* fixup input/outputs: */
2733 for (i = 0; i < so->outputs_count; i++) {
2734 /* sometimes we get outputs that don't write the .x coord, like:
2735 *
2736 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
2737 *
2738 * Presumably the result of varying packing and then eliminating
2739 * some unneeded varyings? Just skip head to the first valid
2740 * component of the output.
2741 */
2742 for (unsigned j = 0; j < 4; j++) {
2743 struct ir3_instruction *instr = ir->outputs[(i*4) + j];
2744 if (instr) {
2745 so->outputs[i].regid = instr->regs[0]->num;
2746 break;
2747 }
2748 }
2749 }
2750
2751 /* Note that some or all channels of an input may be unused: */
2752 actual_in = 0;
2753 inloc = 0;
2754 for (i = 0; i < so->inputs_count; i++) {
2755 unsigned j, reg = regid(63,0), compmask = 0, maxcomp = 0;
2756 so->inputs[i].ncomp = 0;
2757 so->inputs[i].inloc = inloc;
2758 for (j = 0; j < 4; j++) {
2759 struct ir3_instruction *in = inputs[(i*4) + j];
2760 if (in && !(in->flags & IR3_INSTR_UNUSED)) {
2761 compmask |= (1 << j);
2762 reg = in->regs[0]->num - j;
2763 actual_in++;
2764 so->inputs[i].ncomp++;
2765 if ((so->type == MESA_SHADER_FRAGMENT) && so->inputs[i].bary) {
2766 /* assign inloc: */
2767 assert(in->regs[1]->flags & IR3_REG_IMMED);
2768 in->regs[1]->iim_val = inloc + j;
2769 maxcomp = j + 1;
2770 }
2771 }
2772 }
2773 if ((so->type == MESA_SHADER_FRAGMENT) && compmask && so->inputs[i].bary) {
2774 so->varying_in++;
2775 so->inputs[i].compmask = (1 << maxcomp) - 1;
2776 inloc += maxcomp;
2777 } else if (!so->inputs[i].sysval) {
2778 so->inputs[i].compmask = compmask;
2779 }
2780 so->inputs[i].regid = reg;
2781 }
2782
2783 if (ctx->astc_srgb)
2784 fixup_astc_srgb(ctx);
2785
2786 /* We need to do legalize after (for frag shader's) the "bary.f"
2787 * offsets (inloc) have been assigned.
2788 */
2789 ir3_legalize(ir, &so->has_ssbo, &max_bary);
2790
2791 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2792 printf("AFTER LEGALIZE:\n");
2793 ir3_print(ir);
2794 }
2795
2796 so->branchstack = ctx->max_stack;
2797
2798 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
2799 if (so->type == MESA_SHADER_VERTEX)
2800 so->total_in = actual_in;
2801 else
2802 so->total_in = max_bary + 1;
2803
2804 so->max_sun = ir->max_sun;
2805
2806 out:
2807 if (ret) {
2808 if (so->ir)
2809 ir3_destroy(so->ir);
2810 so->ir = NULL;
2811 }
2812 ir3_context_free(ctx);
2813
2814 return ret;
2815 }