2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
38 #include "instr-a3xx.h"
40 #include "ir3_context.h"
43 static struct ir3_instruction
*
44 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
45 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
47 struct ir3_block
*block
= ctx
->block
;
48 struct ir3_instruction
*mov
;
49 struct ir3_register
*src
;
51 mov
= ir3_instr_create(block
, OPC_MOV
);
52 mov
->cat1
.src_type
= TYPE_U32
;
53 mov
->cat1
.dst_type
= TYPE_U32
;
55 src
= __ssa_src(mov
, collect
, IR3_REG_RELATIV
);
57 src
->array
.offset
= n
;
59 ir3_instr_set_address(mov
, address
);
64 static struct ir3_instruction
*
65 create_input(struct ir3_context
*ctx
, unsigned compmask
)
67 struct ir3_instruction
*in
;
69 in
= ir3_instr_create(ctx
->in_block
, OPC_META_INPUT
);
70 in
->input
.sysval
= ~0;
71 __ssa_dst(in
)->wrmask
= compmask
;
73 array_insert(ctx
->ir
, ctx
->ir
->inputs
, in
);
78 static struct ir3_instruction
*
79 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
, unsigned n
)
81 struct ir3_block
*block
= ctx
->block
;
82 struct ir3_instruction
*instr
;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction
*inloc
= create_immed(block
, n
);
87 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
88 instr
->cat6
.type
= TYPE_U32
;
89 instr
->cat6
.iim_val
= 1;
91 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->ij_pixel
, 0);
92 instr
->regs
[2]->wrmask
= 0x3;
98 static struct ir3_instruction
*
99 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
104 unsigned n
= const_state
->offsets
.driver_param
;
105 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
106 return create_uniform(ctx
->block
, r
);
110 * Adreno uses uint rather than having dedicated bool type,
111 * which (potentially) requires some conversion, in particular
112 * when using output of an bool instr to int input, or visa
116 * -------+---------+-------+-
120 * To convert from an adreno bool (uint) to nir, use:
122 * absneg.s dst, (neg)src
124 * To convert back in the other direction:
126 * absneg.s dst, (abs)arc
128 * The CP step can clean up the absneg.s that cancel each other
129 * out, and with a slight bit of extra cleverness (to recognize
130 * the instructions which produce either a 0 or 1) can eliminate
131 * the absneg.s's completely when an instruction that wants
132 * 0/1 consumes the result. For example, when a nir 'bcsel'
133 * consumes the result of 'feq'. So we should be able to get by
134 * without a boolean resolve step, and without incuring any
135 * extra penalty in instruction count.
138 /* NIR bool -> native (adreno): */
139 static struct ir3_instruction
*
140 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
142 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
145 /* native (adreno) -> NIR bool: */
146 static struct ir3_instruction
*
147 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
149 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
153 * alu/sfu instructions:
156 static struct ir3_instruction
*
157 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
158 unsigned src_bitsize
, nir_op op
)
160 type_t src_type
, dst_type
;
164 case nir_op_f2f16_rtne
:
165 case nir_op_f2f16_rtz
:
173 switch (src_bitsize
) {
181 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
190 switch (src_bitsize
) {
201 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
210 switch (src_bitsize
) {
221 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
226 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
236 case nir_op_f2f16_rtne
:
237 case nir_op_f2f16_rtz
:
239 /* TODO how to handle rounding mode? */
276 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
279 return ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
283 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
285 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
286 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
287 unsigned bs
[info
->num_inputs
]; /* bit size */
288 struct ir3_block
*b
= ctx
->block
;
289 unsigned dst_sz
, wrmask
;
290 type_t dst_type
= nir_dest_bit_size(alu
->dest
.dest
) < 32 ?
293 if (alu
->dest
.dest
.is_ssa
) {
294 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
295 wrmask
= (1 << dst_sz
) - 1;
297 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
298 wrmask
= alu
->dest
.write_mask
;
301 dst
= ir3_get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
303 /* Vectors are special in that they have non-scalarized writemasks,
304 * and just take the first swizzle channel for each argument in
305 * order into each writemask channel.
307 if ((alu
->op
== nir_op_vec2
) ||
308 (alu
->op
== nir_op_vec3
) ||
309 (alu
->op
== nir_op_vec4
)) {
311 for (int i
= 0; i
< info
->num_inputs
; i
++) {
312 nir_alu_src
*asrc
= &alu
->src
[i
];
314 compile_assert(ctx
, !asrc
->abs
);
315 compile_assert(ctx
, !asrc
->negate
);
317 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
319 src
[i
] = create_immed_typed(ctx
->block
, 0, dst_type
);
320 dst
[i
] = ir3_MOV(b
, src
[i
], dst_type
);
323 ir3_put_dst(ctx
, &alu
->dest
.dest
);
327 /* We also get mov's with more than one component for mov's so
328 * handle those specially:
330 if (alu
->op
== nir_op_mov
) {
331 nir_alu_src
*asrc
= &alu
->src
[0];
332 struct ir3_instruction
*const *src0
= ir3_get_src(ctx
, &asrc
->src
);
334 for (unsigned i
= 0; i
< dst_sz
; i
++) {
335 if (wrmask
& (1 << i
)) {
336 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], dst_type
);
342 ir3_put_dst(ctx
, &alu
->dest
.dest
);
346 /* General case: We can just grab the one used channel per src. */
347 for (int i
= 0; i
< info
->num_inputs
; i
++) {
348 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
349 nir_alu_src
*asrc
= &alu
->src
[i
];
351 compile_assert(ctx
, !asrc
->abs
);
352 compile_assert(ctx
, !asrc
->negate
);
354 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
355 bs
[i
] = nir_src_bit_size(asrc
->src
);
357 compile_assert(ctx
, src
[i
]);
362 case nir_op_f2f16_rtne
:
363 case nir_op_f2f16_rtz
:
381 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
383 case nir_op_fquantize2f16
:
384 dst
[0] = create_cov(ctx
,
385 create_cov(ctx
, src
[0], 32, nir_op_f2f16
),
389 struct ir3_instruction
*zero
= create_immed_typed(b
, 0, TYPE_F16
);
390 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, zero
, 0);
391 dst
[0]->cat2
.condition
= IR3_COND_NE
;
395 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
396 dst
[0]->cat2
.condition
= IR3_COND_NE
;
399 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F16
);
402 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
407 dst
[0] = ir3_b2n(b
, src
[0]);
410 struct ir3_instruction
*zero
= create_immed_typed(b
, 0, TYPE_S16
);
411 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, zero
, 0);
412 dst
[0]->cat2
.condition
= IR3_COND_NE
;
416 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
417 dst
[0]->cat2
.condition
= IR3_COND_NE
;
421 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
424 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
427 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
430 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
433 /* if there is just a single use of the src, and it supports
434 * (sat) bit, we can just fold the (sat) flag back to the
435 * src instruction and create a mov. This is easier for cp
438 * TODO probably opc_cat==4 is ok too
440 if (alu
->src
[0].src
.is_ssa
&&
441 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
442 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
443 src
[0]->flags
|= IR3_INSTR_SAT
;
444 dst
[0] = ir3_MOV(b
, src
[0], dst_type
);
446 /* otherwise generate a max.f that saturates.. blob does
447 * similar (generating a cat2 mov using max.f)
449 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
450 dst
[0]->flags
|= IR3_INSTR_SAT
;
454 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
457 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
460 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
463 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
466 case nir_op_fddx_coarse
:
467 dst
[0] = ir3_DSX(b
, src
[0], 0);
468 dst
[0]->cat5
.type
= TYPE_F32
;
470 case nir_op_fddx_fine
:
471 dst
[0] = ir3_DSXPP_1(b
, src
[0], 0);
472 dst
[0]->cat5
.type
= TYPE_F32
;
475 case nir_op_fddy_coarse
:
476 dst
[0] = ir3_DSY(b
, src
[0], 0);
477 dst
[0]->cat5
.type
= TYPE_F32
;
480 case nir_op_fddy_fine
:
481 dst
[0] = ir3_DSYPP_1(b
, src
[0], 0);
482 dst
[0]->cat5
.type
= TYPE_F32
;
486 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
487 dst
[0]->cat2
.condition
= IR3_COND_LT
;
491 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
492 dst
[0]->cat2
.condition
= IR3_COND_GE
;
496 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
497 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
501 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
502 dst
[0]->cat2
.condition
= IR3_COND_NE
;
505 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
508 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
511 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
513 case nir_op_fround_even
:
514 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
517 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
521 dst
[0] = ir3_SIN(b
, src
[0], 0);
524 dst
[0] = ir3_COS(b
, src
[0], 0);
527 dst
[0] = ir3_RSQ(b
, src
[0], 0);
530 dst
[0] = ir3_RCP(b
, src
[0], 0);
533 dst
[0] = ir3_LOG2(b
, src
[0], 0);
536 dst
[0] = ir3_EXP2(b
, src
[0], 0);
539 dst
[0] = ir3_SQRT(b
, src
[0], 0);
543 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
546 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
549 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
552 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
555 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
558 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
561 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
563 case nir_op_umul_low
:
564 dst
[0] = ir3_MULL_U(b
, src
[0], 0, src
[1], 0);
566 case nir_op_imadsh_mix16
:
567 dst
[0] = ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0, src
[2], 0);
569 case nir_op_imad24_ir3
:
570 dst
[0] = ir3_MAD_S24(b
, src
[0], 0, src
[1], 0, src
[2], 0);
573 dst
[0] = ir3_MUL_S24(b
, src
[0], 0, src
[1], 0);
576 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
579 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
582 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
585 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
588 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
591 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
594 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
597 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
601 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
602 dst
[0]->cat2
.condition
= IR3_COND_LT
;
606 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
607 dst
[0]->cat2
.condition
= IR3_COND_GE
;
611 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
612 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
616 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
617 dst
[0]->cat2
.condition
= IR3_COND_NE
;
621 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
622 dst
[0]->cat2
.condition
= IR3_COND_LT
;
626 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
627 dst
[0]->cat2
.condition
= IR3_COND_GE
;
631 case nir_op_b32csel
: {
632 struct ir3_instruction
*cond
= src
[0];
634 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
635 * we can ignore that and use original cond, since the nonzero-ness of
636 * cond stays the same.
638 if (cond
->opc
== OPC_ABSNEG_S
&&
640 (cond
->regs
[1]->flags
& (IR3_REG_SNEG
| IR3_REG_SABS
)) == IR3_REG_SNEG
) {
641 cond
= cond
->regs
[1]->instr
;
644 compile_assert(ctx
, bs
[1] == bs
[2]);
645 /* Make sure the boolean condition has the same bit size as the other
646 * two arguments, adding a conversion if necessary.
649 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
650 else if (bs
[1] > bs
[0])
651 cond
= ir3_COV(b
, cond
, TYPE_U16
, TYPE_U32
);
654 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
656 dst
[0] = ir3_SEL_B16(b
, src
[1], 0, cond
, 0, src
[2], 0);
659 case nir_op_bit_count
: {
660 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
661 // double check on earlier gen's. Once half-precision support is
662 // in place, this should probably move to a NIR lowering pass:
663 struct ir3_instruction
*hi
, *lo
;
665 hi
= ir3_COV(b
, ir3_SHR_B(b
, src
[0], 0, create_immed(b
, 16), 0),
667 lo
= ir3_COV(b
, src
[0], TYPE_U32
, TYPE_U16
);
669 hi
= ir3_CBITS_B(b
, hi
, 0);
670 lo
= ir3_CBITS_B(b
, lo
, 0);
672 // TODO maybe the builders should default to making dst half-precision
673 // if the src's were half precision, to make this less awkward.. otoh
674 // we should probably just do this lowering in NIR.
675 hi
->regs
[0]->flags
|= IR3_REG_HALF
;
676 lo
->regs
[0]->flags
|= IR3_REG_HALF
;
678 dst
[0] = ir3_ADD_S(b
, hi
, 0, lo
, 0);
679 dst
[0]->regs
[0]->flags
|= IR3_REG_HALF
;
680 dst
[0] = ir3_COV(b
, dst
[0], TYPE_U16
, TYPE_U32
);
683 case nir_op_ifind_msb
: {
684 struct ir3_instruction
*cmp
;
685 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
686 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
687 cmp
->cat2
.condition
= IR3_COND_GE
;
688 dst
[0] = ir3_SEL_B32(b
,
689 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
693 case nir_op_ufind_msb
:
694 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
695 dst
[0] = ir3_SEL_B32(b
,
696 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
697 src
[0], 0, dst
[0], 0);
699 case nir_op_find_lsb
:
700 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
701 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
703 case nir_op_bitfield_reverse
:
704 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
708 ir3_context_error(ctx
, "Unhandled ALU op: %s\n",
709 nir_op_infos
[alu
->op
].name
);
713 if (nir_alu_type_get_base_type(info
->output_type
) == nir_type_bool
) {
716 if (nir_dest_bit_size(alu
->dest
.dest
) < 32)
717 dst
[0]->regs
[0]->flags
|= IR3_REG_HALF
;
719 dst
[0] = ir3_n2b(b
, dst
[0]);
722 if (nir_dest_bit_size(alu
->dest
.dest
) < 32) {
723 for (unsigned i
= 0; i
< dst_sz
; i
++) {
724 dst
[i
]->regs
[0]->flags
|= IR3_REG_HALF
;
728 ir3_put_dst(ctx
, &alu
->dest
.dest
);
732 emit_intrinsic_load_ubo_ldc(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
733 struct ir3_instruction
**dst
)
735 struct ir3_block
*b
= ctx
->block
;
737 unsigned ncomp
= intr
->num_components
;
738 struct ir3_instruction
*offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
739 struct ir3_instruction
*idx
= ir3_get_src(ctx
, &intr
->src
[0])[0];
740 struct ir3_instruction
*ldc
= ir3_LDC(b
, idx
, 0, offset
, 0);
741 ldc
->regs
[0]->wrmask
= MASK(ncomp
);
742 ldc
->cat6
.iim_val
= intr
->num_components
;
744 ldc
->cat6
.type
= TYPE_U32
;
746 nir_intrinsic_instr
*bindless
= ir3_bindless_resource(intr
->src
[0]);
748 ldc
->flags
|= IR3_INSTR_B
;
749 ldc
->cat6
.base
= nir_intrinsic_desc_set(bindless
);
750 ctx
->so
->bindless_ubo
= true;
753 ir3_split_dest(b
, dst
, ldc
, 0, ncomp
);
757 /* handles direct/indirect UBO reads: */
759 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
760 struct ir3_instruction
**dst
)
762 if (ir3_bindless_resource(intr
->src
[0])) {
763 /* TODO: We should be using ldc for non-bindless things on a6xx as
766 emit_intrinsic_load_ubo_ldc(ctx
, intr
, dst
);
769 struct ir3_block
*b
= ctx
->block
;
770 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
771 /* UBO addresses are the first driver params, but subtract 2 here to
772 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
773 * is the uniforms: */
774 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
775 unsigned ubo
= regid(const_state
->offsets
.ubo
, 0) - 2;
776 const unsigned ptrsz
= ir3_pointer_size(ctx
->compiler
);
780 /* First src is ubo index, which could either be an immed or not: */
781 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0];
782 if (is_same_type_mov(src0
) &&
783 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
784 base_lo
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
785 base_hi
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
787 base_lo
= create_uniform_indirect(b
, ubo
, ir3_get_addr0(ctx
, src0
, ptrsz
));
788 base_hi
= create_uniform_indirect(b
, ubo
+ 1, ir3_get_addr0(ctx
, src0
, ptrsz
));
790 /* NOTE: since relative addressing is used, make sure constlen is
791 * at least big enough to cover all the UBO addresses, since the
792 * assembler won't know what the max address reg is.
794 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
795 const_state
->offsets
.ubo
+ (ctx
->s
->info
.num_ubos
* ptrsz
));
798 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
801 if (nir_src_is_const(intr
->src
[1])) {
802 off
+= nir_src_as_uint(intr
->src
[1]);
804 /* For load_ubo_indirect, second src is indirect offset: */
805 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0];
807 /* and add offset to addr: */
808 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
811 /* if offset is to large to encode in the ldg, split it out: */
812 if ((off
+ (intr
->num_components
* 4)) > 1024) {
813 /* split out the minimal amount to improve the odds that
814 * cp can fit the immediate in the add.s instruction:
816 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
817 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
822 struct ir3_instruction
*carry
;
824 /* handle 32b rollover, ie:
825 * if (addr < base_lo)
828 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
829 carry
->cat2
.condition
= IR3_COND_LT
;
830 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
832 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
835 for (int i
= 0; i
< intr
->num_components
; i
++) {
836 struct ir3_instruction
*load
=
837 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0, /* num components */
838 create_immed(b
, off
+ i
* 4), 0);
839 load
->cat6
.type
= TYPE_U32
;
844 /* src[] = { block_index } */
846 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
847 struct ir3_instruction
**dst
)
849 /* SSBO size stored as a const starting at ssbo_sizes: */
850 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
851 unsigned blk_idx
= nir_src_as_uint(intr
->src
[0]);
852 unsigned idx
= regid(const_state
->offsets
.ssbo_sizes
, 0) +
853 const_state
->ssbo_size
.off
[blk_idx
];
855 debug_assert(const_state
->ssbo_size
.mask
& (1 << blk_idx
));
857 dst
[0] = create_uniform(ctx
->block
, idx
);
860 /* src[] = { offset }. const_index[] = { base } */
862 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
863 struct ir3_instruction
**dst
)
865 struct ir3_block
*b
= ctx
->block
;
866 struct ir3_instruction
*ldl
, *offset
;
869 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
870 base
= nir_intrinsic_base(intr
);
872 ldl
= ir3_LDL(b
, offset
, 0,
873 create_immed(b
, intr
->num_components
), 0,
874 create_immed(b
, base
), 0);
876 ldl
->cat6
.type
= utype_dst(intr
->dest
);
877 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
879 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
880 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
882 ir3_split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
885 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
887 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
889 struct ir3_block
*b
= ctx
->block
;
890 struct ir3_instruction
*stl
, *offset
;
891 struct ir3_instruction
* const *value
;
892 unsigned base
, wrmask
;
894 value
= ir3_get_src(ctx
, &intr
->src
[0]);
895 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
897 base
= nir_intrinsic_base(intr
);
898 wrmask
= nir_intrinsic_write_mask(intr
);
900 /* Combine groups of consecutive enabled channels in one write
901 * message. We use ffs to find the first enabled channel and then ffs on
902 * the bit-inverse, down-shifted writemask to determine the length of
903 * the block of enabled bits.
905 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
908 unsigned first_component
= ffs(wrmask
) - 1;
909 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
911 stl
= ir3_STL(b
, offset
, 0,
912 ir3_create_collect(ctx
, &value
[first_component
], length
), 0,
913 create_immed(b
, length
), 0);
914 stl
->cat6
.dst_offset
= first_component
+ base
;
915 stl
->cat6
.type
= utype_src(intr
->src
[0]);
916 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
917 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
919 array_insert(b
, b
->keeps
, stl
);
921 /* Clear the bits in the writemask that we just wrote, then try
922 * again to see if more channels are left.
924 wrmask
&= (15 << (first_component
+ length
));
928 /* src[] = { offset }. const_index[] = { base } */
930 emit_intrinsic_load_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
931 struct ir3_instruction
**dst
)
933 struct ir3_block
*b
= ctx
->block
;
934 struct ir3_instruction
*load
, *offset
;
937 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
938 base
= nir_intrinsic_base(intr
);
940 load
= ir3_LDLW(b
, offset
, 0,
941 create_immed(b
, intr
->num_components
), 0,
942 create_immed(b
, base
), 0);
944 load
->cat6
.type
= utype_dst(intr
->dest
);
945 load
->regs
[0]->wrmask
= MASK(intr
->num_components
);
947 load
->barrier_class
= IR3_BARRIER_SHARED_R
;
948 load
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
950 ir3_split_dest(b
, dst
, load
, 0, intr
->num_components
);
953 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
955 emit_intrinsic_store_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
957 struct ir3_block
*b
= ctx
->block
;
958 struct ir3_instruction
*store
, *offset
;
959 struct ir3_instruction
* const *value
;
960 unsigned base
, wrmask
;
962 value
= ir3_get_src(ctx
, &intr
->src
[0]);
963 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
965 base
= nir_intrinsic_base(intr
);
966 wrmask
= nir_intrinsic_write_mask(intr
);
968 /* Combine groups of consecutive enabled channels in one write
969 * message. We use ffs to find the first enabled channel and then ffs on
970 * the bit-inverse, down-shifted writemask to determine the length of
971 * the block of enabled bits.
973 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
976 unsigned first_component
= ffs(wrmask
) - 1;
977 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
979 store
= ir3_STLW(b
, offset
, 0,
980 ir3_create_collect(ctx
, &value
[first_component
], length
), 0,
981 create_immed(b
, length
), 0);
983 store
->cat6
.dst_offset
= first_component
+ base
;
984 store
->cat6
.type
= utype_src(intr
->src
[0]);
985 store
->barrier_class
= IR3_BARRIER_SHARED_W
;
986 store
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
988 array_insert(b
, b
->keeps
, store
);
990 /* Clear the bits in the writemask that we just wrote, then try
991 * again to see if more channels are left.
993 wrmask
&= (15 << (first_component
+ length
));
998 * CS shared variable atomic intrinsics
1000 * All of the shared variable atomic memory operations read a value from
1001 * memory, compute a new value using one of the operations below, write the
1002 * new value to memory, and return the original value read.
1004 * All operations take 2 sources except CompSwap that takes 3. These
1005 * sources represent:
1007 * 0: The offset into the shared variable storage region that the atomic
1008 * operation will operate on.
1009 * 1: The data parameter to the atomic function (i.e. the value to add
1010 * in shared_atomic_add, etc).
1011 * 2: For CompSwap only: the second data parameter.
1013 static struct ir3_instruction
*
1014 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1016 struct ir3_block
*b
= ctx
->block
;
1017 struct ir3_instruction
*atomic
, *src0
, *src1
;
1018 type_t type
= TYPE_U32
;
1020 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1021 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0]; /* value */
1023 switch (intr
->intrinsic
) {
1024 case nir_intrinsic_shared_atomic_add
:
1025 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1027 case nir_intrinsic_shared_atomic_imin
:
1028 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1031 case nir_intrinsic_shared_atomic_umin
:
1032 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1034 case nir_intrinsic_shared_atomic_imax
:
1035 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1038 case nir_intrinsic_shared_atomic_umax
:
1039 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1041 case nir_intrinsic_shared_atomic_and
:
1042 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1044 case nir_intrinsic_shared_atomic_or
:
1045 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1047 case nir_intrinsic_shared_atomic_xor
:
1048 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1050 case nir_intrinsic_shared_atomic_exchange
:
1051 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1053 case nir_intrinsic_shared_atomic_comp_swap
:
1054 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1055 src1
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1056 ir3_get_src(ctx
, &intr
->src
[2])[0],
1059 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1065 atomic
->cat6
.iim_val
= 1;
1067 atomic
->cat6
.type
= type
;
1068 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1069 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1071 /* even if nothing consume the result, we can't DCE the instruction: */
1072 array_insert(b
, b
->keeps
, atomic
);
1077 struct tex_src_info
{
1079 unsigned tex_base
, samp_base
, tex_idx
, samp_idx
;
1080 /* For normal tex instructions */
1081 unsigned base
, combined_idx
, a1_val
, flags
;
1082 struct ir3_instruction
*samp_tex
;
1085 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1086 * to handle with the image_mapping table..
1088 static struct tex_src_info
1089 get_image_samp_tex_src(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1091 struct ir3_block
*b
= ctx
->block
;
1092 struct tex_src_info info
= { 0 };
1093 nir_intrinsic_instr
*bindless_tex
= ir3_bindless_resource(intr
->src
[0]);
1094 ctx
->so
->bindless_tex
= true;
1098 info
.flags
|= IR3_INSTR_B
;
1100 /* Gather information required to determine which encoding to
1101 * choose as well as for prefetch.
1103 info
.tex_base
= nir_intrinsic_desc_set(bindless_tex
);
1104 bool tex_const
= nir_src_is_const(bindless_tex
->src
[0]);
1106 info
.tex_idx
= nir_src_as_uint(bindless_tex
->src
[0]);
1109 /* Choose encoding. */
1110 if (tex_const
&& info
.tex_idx
< 256) {
1111 if (info
.tex_idx
< 16) {
1112 /* Everything fits within the instruction */
1113 info
.base
= info
.tex_base
;
1114 info
.combined_idx
= info
.samp_idx
| (info
.tex_idx
<< 4);
1116 info
.base
= info
.tex_base
;
1117 info
.a1_val
= info
.tex_idx
<< 3;
1118 info
.combined_idx
= 0;
1119 info
.flags
|= IR3_INSTR_A1EN
;
1121 info
.samp_tex
= NULL
;
1123 info
.flags
|= IR3_INSTR_S2EN
;
1124 info
.base
= info
.tex_base
;
1126 /* Note: the indirect source is now a vec2 instead of hvec2 */
1127 struct ir3_instruction
*texture
, *sampler
;
1129 texture
= ir3_get_src(ctx
, &intr
->src
[0])[0];
1130 sampler
= create_immed(b
, 0);
1131 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1137 info
.flags
|= IR3_INSTR_S2EN
;
1138 unsigned slot
= nir_src_as_uint(intr
->src
[0]);
1139 unsigned tex_idx
= ir3_image_to_tex(&ctx
->so
->image_mapping
, slot
);
1140 struct ir3_instruction
*texture
, *sampler
;
1142 texture
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1143 sampler
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1145 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1154 static struct ir3_instruction
*
1155 emit_sam(struct ir3_context
*ctx
, opc_t opc
, struct tex_src_info info
,
1156 type_t type
, unsigned wrmask
, struct ir3_instruction
*src0
,
1157 struct ir3_instruction
*src1
)
1159 struct ir3_instruction
*sam
, *addr
;
1160 if (info
.flags
& IR3_INSTR_A1EN
) {
1161 addr
= ir3_get_addr1(ctx
, info
.a1_val
);
1163 sam
= ir3_SAM(ctx
->block
, opc
, type
, 0b1111, info
.flags
,
1164 info
.samp_tex
, src0
, src1
);
1165 if (info
.flags
& IR3_INSTR_A1EN
) {
1166 ir3_instr_set_address(sam
, addr
);
1168 if (info
.flags
& IR3_INSTR_B
) {
1169 sam
->cat5
.tex_base
= info
.base
;
1170 sam
->cat5
.samp
= info
.combined_idx
;
1175 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1177 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1178 struct ir3_instruction
**dst
)
1180 struct ir3_block
*b
= ctx
->block
;
1181 struct tex_src_info info
= get_image_samp_tex_src(ctx
, intr
);
1182 struct ir3_instruction
*sam
;
1183 struct ir3_instruction
* const *src0
= ir3_get_src(ctx
, &intr
->src
[1]);
1184 struct ir3_instruction
*coords
[4];
1185 unsigned flags
, ncoords
= ir3_get_image_coords(intr
, &flags
);
1186 type_t type
= ir3_get_type_for_image_intrinsic(intr
);
1188 /* hmm, this seems a bit odd, but it is what blob does and (at least
1189 * a5xx) just faults on bogus addresses otherwise:
1191 if (flags
& IR3_INSTR_3D
) {
1192 flags
&= ~IR3_INSTR_3D
;
1193 flags
|= IR3_INSTR_A
;
1195 info
.flags
|= flags
;
1197 for (unsigned i
= 0; i
< ncoords
; i
++)
1198 coords
[i
] = src0
[i
];
1201 coords
[ncoords
++] = create_immed(b
, 0);
1203 sam
= emit_sam(ctx
, OPC_ISAM
, info
, type
, 0b1111,
1204 ir3_create_collect(ctx
, coords
, ncoords
), NULL
);
1206 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1207 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1209 ir3_split_dest(b
, dst
, sam
, 0, 4);
1213 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1214 struct ir3_instruction
**dst
)
1216 struct ir3_block
*b
= ctx
->block
;
1217 struct tex_src_info info
= get_image_samp_tex_src(ctx
, intr
);
1218 struct ir3_instruction
*sam
, *lod
;
1219 unsigned flags
, ncoords
= ir3_get_image_coords(intr
, &flags
);
1220 type_t dst_type
= nir_dest_bit_size(intr
->dest
) < 32 ?
1221 TYPE_U16
: TYPE_U32
;
1223 info
.flags
|= flags
;
1224 lod
= create_immed(b
, 0);
1225 sam
= emit_sam(ctx
, OPC_GETSIZE
, info
, dst_type
, 0b1111, lod
, NULL
);
1227 /* Array size actually ends up in .w rather than .z. This doesn't
1228 * matter for miplevel 0, but for higher mips the value in z is
1229 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1230 * returned, which means that we have to add 1 to it for arrays for
1233 * Note use a temporary dst and then copy, since the size of the dst
1234 * array that is passed in is based on nir's understanding of the
1235 * result size, not the hardware's
1237 struct ir3_instruction
*tmp
[4];
1239 ir3_split_dest(b
, tmp
, sam
, 0, 4);
1241 /* get_size instruction returns size in bytes instead of texels
1242 * for imageBuffer, so we need to divide it by the pixel size
1243 * of the image format.
1245 * TODO: This is at least true on a5xx. Check other gens.
1247 if (nir_intrinsic_image_dim(intr
) == GLSL_SAMPLER_DIM_BUF
) {
1248 /* Since all the possible values the divisor can take are
1249 * power-of-two (4, 8, or 16), the division is implemented
1251 * During shader setup, the log2 of the image format's
1252 * bytes-per-pixel should have been emitted in 2nd slot of
1253 * image_dims. See ir3_shader::emit_image_dims().
1255 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
1256 unsigned cb
= regid(const_state
->offsets
.image_dims
, 0) +
1257 const_state
->image_dims
.off
[nir_src_as_uint(intr
->src
[0])];
1258 struct ir3_instruction
*aux
= create_uniform(b
, cb
+ 1);
1260 tmp
[0] = ir3_SHR_B(b
, tmp
[0], 0, aux
, 0);
1263 for (unsigned i
= 0; i
< ncoords
; i
++)
1266 if (flags
& IR3_INSTR_A
) {
1267 if (ctx
->compiler
->levels_add_one
) {
1268 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
1270 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
1276 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1278 struct ir3_block
*b
= ctx
->block
;
1279 struct ir3_instruction
*barrier
;
1281 switch (intr
->intrinsic
) {
1282 case nir_intrinsic_control_barrier
:
1283 barrier
= ir3_BAR(b
);
1284 barrier
->cat7
.g
= true;
1285 barrier
->cat7
.l
= true;
1286 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1287 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1289 case nir_intrinsic_memory_barrier
:
1290 barrier
= ir3_FENCE(b
);
1291 barrier
->cat7
.g
= true;
1292 barrier
->cat7
.r
= true;
1293 barrier
->cat7
.w
= true;
1294 barrier
->cat7
.l
= true;
1295 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1296 IR3_BARRIER_BUFFER_W
;
1297 barrier
->barrier_conflict
=
1298 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1299 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1301 case nir_intrinsic_memory_barrier_buffer
:
1302 barrier
= ir3_FENCE(b
);
1303 barrier
->cat7
.g
= true;
1304 barrier
->cat7
.r
= true;
1305 barrier
->cat7
.w
= true;
1306 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1307 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1308 IR3_BARRIER_BUFFER_W
;
1310 case nir_intrinsic_memory_barrier_image
:
1311 // TODO double check if this should have .g set
1312 barrier
= ir3_FENCE(b
);
1313 barrier
->cat7
.g
= true;
1314 barrier
->cat7
.r
= true;
1315 barrier
->cat7
.w
= true;
1316 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1317 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1318 IR3_BARRIER_IMAGE_W
;
1320 case nir_intrinsic_memory_barrier_shared
:
1321 barrier
= ir3_FENCE(b
);
1322 barrier
->cat7
.g
= true;
1323 barrier
->cat7
.l
= true;
1324 barrier
->cat7
.r
= true;
1325 barrier
->cat7
.w
= true;
1326 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1327 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1328 IR3_BARRIER_SHARED_W
;
1330 case nir_intrinsic_group_memory_barrier
:
1331 barrier
= ir3_FENCE(b
);
1332 barrier
->cat7
.g
= true;
1333 barrier
->cat7
.l
= true;
1334 barrier
->cat7
.r
= true;
1335 barrier
->cat7
.w
= true;
1336 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1337 IR3_BARRIER_IMAGE_W
|
1338 IR3_BARRIER_BUFFER_W
;
1339 barrier
->barrier_conflict
=
1340 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1341 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1342 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1348 /* make sure barrier doesn't get DCE'd */
1349 array_insert(b
, b
->keeps
, barrier
);
1352 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1353 gl_system_value slot
, unsigned compmask
,
1354 struct ir3_instruction
*instr
)
1356 struct ir3_shader_variant
*so
= ctx
->so
;
1357 unsigned n
= so
->inputs_count
++;
1359 assert(instr
->opc
== OPC_META_INPUT
);
1360 instr
->input
.inidx
= n
;
1361 instr
->input
.sysval
= slot
;
1363 so
->inputs
[n
].sysval
= true;
1364 so
->inputs
[n
].slot
= slot
;
1365 so
->inputs
[n
].compmask
= compmask
;
1366 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1370 static struct ir3_instruction
*
1371 create_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1375 struct ir3_instruction
*sysval
= create_input(ctx
, compmask
);
1376 add_sysval_input_compmask(ctx
, slot
, compmask
, sysval
);
1380 static struct ir3_instruction
*
1381 get_barycentric_centroid(struct ir3_context
*ctx
)
1383 if (!ctx
->ij_centroid
) {
1384 struct ir3_instruction
*xy
[2];
1385 struct ir3_instruction
*ij
;
1387 ij
= create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
, 0x3);
1388 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1390 ctx
->ij_centroid
= ir3_create_collect(ctx
, xy
, 2);
1393 return ctx
->ij_centroid
;
1396 static struct ir3_instruction
*
1397 get_barycentric_sample(struct ir3_context
*ctx
)
1399 if (!ctx
->ij_sample
) {
1400 struct ir3_instruction
*xy
[2];
1401 struct ir3_instruction
*ij
;
1403 ij
= create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
, 0x3);
1404 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1406 ctx
->ij_sample
= ir3_create_collect(ctx
, xy
, 2);
1409 return ctx
->ij_sample
;
1412 static struct ir3_instruction
*
1413 get_barycentric_pixel(struct ir3_context
*ctx
)
1415 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1416 * this to create ij_pixel only on demand:
1418 return ctx
->ij_pixel
;
1421 static struct ir3_instruction
*
1422 get_frag_coord(struct ir3_context
*ctx
)
1424 if (!ctx
->frag_coord
) {
1425 struct ir3_block
*b
= ctx
->in_block
;
1426 struct ir3_instruction
*xyzw
[4];
1427 struct ir3_instruction
*hw_frag_coord
;
1429 hw_frag_coord
= create_sysval_input(ctx
, SYSTEM_VALUE_FRAG_COORD
, 0xf);
1430 ir3_split_dest(b
, xyzw
, hw_frag_coord
, 0, 4);
1432 /* for frag_coord.xy, we get unsigned values.. we need
1433 * to subtract (integer) 8 and divide by 16 (right-
1434 * shift by 4) then convert to float:
1438 * mov.u32f32 dst, tmp
1441 for (int i
= 0; i
< 2; i
++) {
1442 xyzw
[i
] = ir3_COV(b
, xyzw
[i
], TYPE_U32
, TYPE_F32
);
1443 xyzw
[i
] = ir3_MUL_F(b
, xyzw
[i
], 0, create_immed(b
, fui(1.0 / 16.0)), 0);
1446 ctx
->frag_coord
= ir3_create_collect(ctx
, xyzw
, 4);
1447 ctx
->so
->frag_coord
= true;
1450 return ctx
->frag_coord
;
1454 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1456 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1457 struct ir3_instruction
**dst
;
1458 struct ir3_instruction
* const *src
;
1459 struct ir3_block
*b
= ctx
->block
;
1462 if (info
->has_dest
) {
1463 unsigned n
= nir_intrinsic_dest_components(intr
);
1464 dst
= ir3_get_dst(ctx
, &intr
->dest
, n
);
1469 const unsigned primitive_param
= ctx
->so
->shader
->const_state
.offsets
.primitive_param
* 4;
1470 const unsigned primitive_map
= ctx
->so
->shader
->const_state
.offsets
.primitive_map
* 4;
1472 switch (intr
->intrinsic
) {
1473 case nir_intrinsic_load_uniform
:
1474 idx
= nir_intrinsic_base(intr
);
1475 if (nir_src_is_const(intr
->src
[0])) {
1476 idx
+= nir_src_as_uint(intr
->src
[0]);
1477 for (int i
= 0; i
< intr
->num_components
; i
++) {
1478 dst
[i
] = create_uniform_typed(b
, idx
+ i
,
1479 nir_dest_bit_size(intr
->dest
) < 32 ? TYPE_F16
: TYPE_F32
);
1482 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1483 for (int i
= 0; i
< intr
->num_components
; i
++) {
1484 dst
[i
] = create_uniform_indirect(b
, idx
+ i
,
1485 ir3_get_addr0(ctx
, src
[0], 1));
1487 /* NOTE: if relative addressing is used, we set
1488 * constlen in the compiler (to worst-case value)
1489 * since we don't know in the assembler what the max
1490 * addr reg value can be:
1492 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
1493 ctx
->so
->shader
->ubo_state
.size
/ 16);
1497 case nir_intrinsic_load_vs_primitive_stride_ir3
:
1498 dst
[0] = create_uniform(b
, primitive_param
+ 0);
1500 case nir_intrinsic_load_vs_vertex_stride_ir3
:
1501 dst
[0] = create_uniform(b
, primitive_param
+ 1);
1503 case nir_intrinsic_load_hs_patch_stride_ir3
:
1504 dst
[0] = create_uniform(b
, primitive_param
+ 2);
1506 case nir_intrinsic_load_patch_vertices_in
:
1507 dst
[0] = create_uniform(b
, primitive_param
+ 3);
1509 case nir_intrinsic_load_tess_param_base_ir3
:
1510 dst
[0] = create_uniform(b
, primitive_param
+ 4);
1511 dst
[1] = create_uniform(b
, primitive_param
+ 5);
1513 case nir_intrinsic_load_tess_factor_base_ir3
:
1514 dst
[0] = create_uniform(b
, primitive_param
+ 6);
1515 dst
[1] = create_uniform(b
, primitive_param
+ 7);
1518 case nir_intrinsic_load_primitive_location_ir3
:
1519 idx
= nir_intrinsic_driver_location(intr
);
1520 dst
[0] = create_uniform(b
, primitive_map
+ idx
);
1523 case nir_intrinsic_load_gs_header_ir3
:
1524 dst
[0] = ctx
->gs_header
;
1526 case nir_intrinsic_load_tcs_header_ir3
:
1527 dst
[0] = ctx
->tcs_header
;
1530 case nir_intrinsic_load_primitive_id
:
1531 dst
[0] = ctx
->primitive_id
;
1534 case nir_intrinsic_load_tess_coord
:
1535 if (!ctx
->tess_coord
) {
1537 create_sysval_input(ctx
, SYSTEM_VALUE_TESS_COORD
, 0x3);
1539 ir3_split_dest(b
, dst
, ctx
->tess_coord
, 0, 2);
1541 /* Unused, but ir3_put_dst() below wants to free something */
1542 dst
[2] = create_immed(b
, 0);
1545 case nir_intrinsic_end_patch_ir3
:
1546 assert(ctx
->so
->type
== MESA_SHADER_TESS_CTRL
);
1547 struct ir3_instruction
*end
= ir3_ENDIF(b
);
1548 array_insert(b
, b
->keeps
, end
);
1550 end
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1551 end
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
1554 case nir_intrinsic_store_global_ir3
: {
1555 struct ir3_instruction
*value
, *addr
, *offset
;
1557 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1558 ir3_get_src(ctx
, &intr
->src
[1])[0],
1559 ir3_get_src(ctx
, &intr
->src
[1])[1]
1562 offset
= ir3_get_src(ctx
, &intr
->src
[2])[0];
1564 value
= ir3_create_collect(ctx
, ir3_get_src(ctx
, &intr
->src
[0]),
1565 intr
->num_components
);
1567 struct ir3_instruction
*stg
=
1568 ir3_STG_G(ctx
->block
, addr
, 0, value
, 0,
1569 create_immed(ctx
->block
, intr
->num_components
), 0, offset
, 0);
1570 stg
->cat6
.type
= TYPE_U32
;
1571 stg
->cat6
.iim_val
= 1;
1573 array_insert(b
, b
->keeps
, stg
);
1575 stg
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1576 stg
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1580 case nir_intrinsic_load_global_ir3
: {
1581 struct ir3_instruction
*addr
, *offset
;
1583 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1584 ir3_get_src(ctx
, &intr
->src
[0])[0],
1585 ir3_get_src(ctx
, &intr
->src
[0])[1]
1588 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
1590 struct ir3_instruction
*load
=
1591 ir3_LDG(b
, addr
, 0, create_immed(ctx
->block
, intr
->num_components
),
1593 load
->cat6
.type
= TYPE_U32
;
1594 load
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1596 load
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1597 load
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1599 ir3_split_dest(b
, dst
, load
, 0, intr
->num_components
);
1603 case nir_intrinsic_load_ubo
:
1604 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1606 case nir_intrinsic_load_frag_coord
:
1607 ir3_split_dest(b
, dst
, get_frag_coord(ctx
), 0, 4);
1609 case nir_intrinsic_load_sample_pos_from_id
: {
1610 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1611 * but that doesn't seem necessary.
1613 struct ir3_instruction
*offset
=
1614 ir3_RGETPOS(b
, ir3_get_src(ctx
, &intr
->src
[0])[0], 0);
1615 offset
->regs
[0]->wrmask
= 0x3;
1616 offset
->cat5
.type
= TYPE_F32
;
1618 ir3_split_dest(b
, dst
, offset
, 0, 2);
1622 case nir_intrinsic_load_size_ir3
:
1623 if (!ctx
->ij_size
) {
1625 create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
, 0x1);
1627 dst
[0] = ctx
->ij_size
;
1629 case nir_intrinsic_load_barycentric_centroid
:
1630 ir3_split_dest(b
, dst
, get_barycentric_centroid(ctx
), 0, 2);
1632 case nir_intrinsic_load_barycentric_sample
:
1633 if (ctx
->so
->key
.msaa
) {
1634 ir3_split_dest(b
, dst
, get_barycentric_sample(ctx
), 0, 2);
1636 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1639 case nir_intrinsic_load_barycentric_pixel
:
1640 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1642 case nir_intrinsic_load_interpolated_input
:
1643 idx
= nir_intrinsic_base(intr
);
1644 comp
= nir_intrinsic_component(intr
);
1645 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1646 if (nir_src_is_const(intr
->src
[1])) {
1647 struct ir3_instruction
*coord
= ir3_create_collect(ctx
, src
, 2);
1648 idx
+= nir_src_as_uint(intr
->src
[1]);
1649 for (int i
= 0; i
< intr
->num_components
; i
++) {
1650 unsigned inloc
= idx
* 4 + i
+ comp
;
1651 if (ctx
->so
->inputs
[idx
].bary
&&
1652 !ctx
->so
->inputs
[idx
].use_ldlv
) {
1653 dst
[i
] = ir3_BARY_F(b
, create_immed(b
, inloc
), 0, coord
, 0);
1655 /* for non-varyings use the pre-setup input, since
1656 * that is easier than mapping things back to a
1657 * nir_variable to figure out what it is.
1659 dst
[i
] = ctx
->inputs
[inloc
];
1660 compile_assert(ctx
, dst
[i
]);
1664 ir3_context_error(ctx
, "unhandled");
1667 case nir_intrinsic_load_input
:
1668 idx
= nir_intrinsic_base(intr
);
1669 comp
= nir_intrinsic_component(intr
);
1670 if (nir_src_is_const(intr
->src
[0])) {
1671 idx
+= nir_src_as_uint(intr
->src
[0]);
1672 for (int i
= 0; i
< intr
->num_components
; i
++) {
1673 unsigned n
= idx
* 4 + i
+ comp
;
1674 dst
[i
] = ctx
->inputs
[n
];
1675 compile_assert(ctx
, ctx
->inputs
[n
]);
1678 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1679 struct ir3_instruction
*collect
=
1680 ir3_create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ninputs
);
1681 struct ir3_instruction
*addr
= ir3_get_addr0(ctx
, src
[0], 4);
1682 for (int i
= 0; i
< intr
->num_components
; i
++) {
1683 unsigned n
= idx
* 4 + i
+ comp
;
1684 dst
[i
] = create_indirect_load(ctx
, ctx
->ninputs
,
1689 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1690 * pass and replaced by an ir3-specifc version that adds the
1691 * dword-offset in the last source.
1693 case nir_intrinsic_load_ssbo_ir3
:
1694 ctx
->funcs
->emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1696 case nir_intrinsic_store_ssbo_ir3
:
1697 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1698 !ctx
->s
->info
.fs
.early_fragment_tests
)
1699 ctx
->so
->no_earlyz
= true;
1700 ctx
->funcs
->emit_intrinsic_store_ssbo(ctx
, intr
);
1702 case nir_intrinsic_get_buffer_size
:
1703 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
1705 case nir_intrinsic_ssbo_atomic_add_ir3
:
1706 case nir_intrinsic_ssbo_atomic_imin_ir3
:
1707 case nir_intrinsic_ssbo_atomic_umin_ir3
:
1708 case nir_intrinsic_ssbo_atomic_imax_ir3
:
1709 case nir_intrinsic_ssbo_atomic_umax_ir3
:
1710 case nir_intrinsic_ssbo_atomic_and_ir3
:
1711 case nir_intrinsic_ssbo_atomic_or_ir3
:
1712 case nir_intrinsic_ssbo_atomic_xor_ir3
:
1713 case nir_intrinsic_ssbo_atomic_exchange_ir3
:
1714 case nir_intrinsic_ssbo_atomic_comp_swap_ir3
:
1715 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1716 !ctx
->s
->info
.fs
.early_fragment_tests
)
1717 ctx
->so
->no_earlyz
= true;
1718 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_ssbo(ctx
, intr
);
1720 case nir_intrinsic_load_shared
:
1721 emit_intrinsic_load_shared(ctx
, intr
, dst
);
1723 case nir_intrinsic_store_shared
:
1724 emit_intrinsic_store_shared(ctx
, intr
);
1726 case nir_intrinsic_shared_atomic_add
:
1727 case nir_intrinsic_shared_atomic_imin
:
1728 case nir_intrinsic_shared_atomic_umin
:
1729 case nir_intrinsic_shared_atomic_imax
:
1730 case nir_intrinsic_shared_atomic_umax
:
1731 case nir_intrinsic_shared_atomic_and
:
1732 case nir_intrinsic_shared_atomic_or
:
1733 case nir_intrinsic_shared_atomic_xor
:
1734 case nir_intrinsic_shared_atomic_exchange
:
1735 case nir_intrinsic_shared_atomic_comp_swap
:
1736 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
1738 case nir_intrinsic_image_load
:
1739 emit_intrinsic_load_image(ctx
, intr
, dst
);
1741 case nir_intrinsic_bindless_image_load
:
1742 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1743 * so using isam doesn't work.
1745 * TODO: can we use isam if we fill out more fields?
1747 ctx
->funcs
->emit_intrinsic_load_image(ctx
, intr
, dst
);
1749 case nir_intrinsic_image_store
:
1750 case nir_intrinsic_bindless_image_store
:
1751 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1752 !ctx
->s
->info
.fs
.early_fragment_tests
)
1753 ctx
->so
->no_earlyz
= true;
1754 ctx
->funcs
->emit_intrinsic_store_image(ctx
, intr
);
1756 case nir_intrinsic_image_size
:
1757 case nir_intrinsic_bindless_image_size
:
1758 emit_intrinsic_image_size(ctx
, intr
, dst
);
1760 case nir_intrinsic_image_atomic_add
:
1761 case nir_intrinsic_bindless_image_atomic_add
:
1762 case nir_intrinsic_image_atomic_imin
:
1763 case nir_intrinsic_bindless_image_atomic_imin
:
1764 case nir_intrinsic_image_atomic_umin
:
1765 case nir_intrinsic_bindless_image_atomic_umin
:
1766 case nir_intrinsic_image_atomic_imax
:
1767 case nir_intrinsic_bindless_image_atomic_imax
:
1768 case nir_intrinsic_image_atomic_umax
:
1769 case nir_intrinsic_bindless_image_atomic_umax
:
1770 case nir_intrinsic_image_atomic_and
:
1771 case nir_intrinsic_bindless_image_atomic_and
:
1772 case nir_intrinsic_image_atomic_or
:
1773 case nir_intrinsic_bindless_image_atomic_or
:
1774 case nir_intrinsic_image_atomic_xor
:
1775 case nir_intrinsic_bindless_image_atomic_xor
:
1776 case nir_intrinsic_image_atomic_exchange
:
1777 case nir_intrinsic_bindless_image_atomic_exchange
:
1778 case nir_intrinsic_image_atomic_comp_swap
:
1779 case nir_intrinsic_bindless_image_atomic_comp_swap
:
1780 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1781 !ctx
->s
->info
.fs
.early_fragment_tests
)
1782 ctx
->so
->no_earlyz
= true;
1783 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_image(ctx
, intr
);
1785 case nir_intrinsic_control_barrier
:
1786 case nir_intrinsic_memory_barrier
:
1787 case nir_intrinsic_group_memory_barrier
:
1788 case nir_intrinsic_memory_barrier_buffer
:
1789 case nir_intrinsic_memory_barrier_image
:
1790 case nir_intrinsic_memory_barrier_shared
:
1791 emit_intrinsic_barrier(ctx
, intr
);
1792 /* note that blk ptr no longer valid, make that obvious: */
1795 case nir_intrinsic_store_output
:
1796 idx
= nir_intrinsic_base(intr
);
1797 comp
= nir_intrinsic_component(intr
);
1798 compile_assert(ctx
, nir_src_is_const(intr
->src
[1]));
1799 idx
+= nir_src_as_uint(intr
->src
[1]);
1801 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1802 for (int i
= 0; i
< intr
->num_components
; i
++) {
1803 unsigned n
= idx
* 4 + i
+ comp
;
1804 ctx
->outputs
[n
] = src
[i
];
1807 case nir_intrinsic_load_base_vertex
:
1808 case nir_intrinsic_load_first_vertex
:
1809 if (!ctx
->basevertex
) {
1810 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1812 dst
[0] = ctx
->basevertex
;
1814 case nir_intrinsic_load_base_instance
:
1815 if (!ctx
->base_instance
) {
1816 ctx
->base_instance
= create_driver_param(ctx
, IR3_DP_INSTID_BASE
);
1818 dst
[0] = ctx
->base_instance
;
1820 case nir_intrinsic_load_vertex_id_zero_base
:
1821 case nir_intrinsic_load_vertex_id
:
1822 if (!ctx
->vertex_id
) {
1823 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
1824 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
1825 ctx
->vertex_id
= create_sysval_input(ctx
, sv
, 0x1);
1827 dst
[0] = ctx
->vertex_id
;
1829 case nir_intrinsic_load_instance_id
:
1830 if (!ctx
->instance_id
) {
1831 ctx
->instance_id
= create_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
, 0x1);
1833 dst
[0] = ctx
->instance_id
;
1835 case nir_intrinsic_load_sample_id
:
1836 ctx
->so
->per_samp
= true;
1838 case nir_intrinsic_load_sample_id_no_per_sample
:
1839 if (!ctx
->samp_id
) {
1840 ctx
->samp_id
= create_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
, 0x1);
1841 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
1843 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
1845 case nir_intrinsic_load_sample_mask_in
:
1846 if (!ctx
->samp_mask_in
) {
1847 ctx
->samp_mask_in
= create_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
, 0x1);
1849 dst
[0] = ctx
->samp_mask_in
;
1851 case nir_intrinsic_load_user_clip_plane
:
1852 idx
= nir_intrinsic_ucp_id(intr
);
1853 for (int i
= 0; i
< intr
->num_components
; i
++) {
1854 unsigned n
= idx
* 4 + i
;
1855 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1858 case nir_intrinsic_load_front_face
:
1859 if (!ctx
->frag_face
) {
1860 ctx
->so
->frag_face
= true;
1861 ctx
->frag_face
= create_sysval_input(ctx
, SYSTEM_VALUE_FRONT_FACE
, 0x1);
1862 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1864 /* for fragface, we get -1 for back and 0 for front. However this is
1865 * the inverse of what nir expects (where ~0 is true).
1867 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
1868 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
1870 case nir_intrinsic_load_local_invocation_id
:
1871 if (!ctx
->local_invocation_id
) {
1872 ctx
->local_invocation_id
=
1873 create_sysval_input(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
, 0x7);
1875 ir3_split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
1877 case nir_intrinsic_load_work_group_id
:
1878 if (!ctx
->work_group_id
) {
1879 ctx
->work_group_id
=
1880 create_sysval_input(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
, 0x7);
1881 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
1883 ir3_split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
1885 case nir_intrinsic_load_num_work_groups
:
1886 for (int i
= 0; i
< intr
->num_components
; i
++) {
1887 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
1890 case nir_intrinsic_load_local_group_size
:
1891 for (int i
= 0; i
< intr
->num_components
; i
++) {
1892 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
1895 case nir_intrinsic_discard_if
:
1896 case nir_intrinsic_discard
: {
1897 struct ir3_instruction
*cond
, *kill
;
1899 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1900 /* conditional discard: */
1901 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1902 cond
= ir3_b2n(b
, src
[0]);
1904 /* unconditional discard: */
1905 cond
= create_immed(b
, 1);
1908 /* NOTE: only cmps.*.* can write p0.x: */
1909 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1910 cond
->cat2
.condition
= IR3_COND_NE
;
1912 /* condition always goes in predicate register: */
1913 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1914 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
1916 kill
= ir3_KILL(b
, cond
, 0);
1917 kill
->regs
[1]->num
= regid(REG_P0
, 0);
1918 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1920 array_insert(b
, b
->keeps
, kill
);
1921 ctx
->so
->no_earlyz
= true;
1926 case nir_intrinsic_cond_end_ir3
: {
1927 struct ir3_instruction
*cond
, *kill
;
1929 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1930 cond
= ir3_b2n(b
, src
[0]);
1932 /* NOTE: only cmps.*.* can write p0.x: */
1933 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1934 cond
->cat2
.condition
= IR3_COND_NE
;
1936 /* condition always goes in predicate register: */
1937 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1939 kill
= ir3_IF(b
, cond
, 0);
1941 kill
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1942 kill
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
1944 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1945 array_insert(b
, b
->keeps
, kill
);
1949 case nir_intrinsic_load_shared_ir3
:
1950 emit_intrinsic_load_shared_ir3(ctx
, intr
, dst
);
1952 case nir_intrinsic_store_shared_ir3
:
1953 emit_intrinsic_store_shared_ir3(ctx
, intr
);
1955 case nir_intrinsic_bindless_resource_ir3
:
1956 dst
[0] = ir3_get_src(ctx
, &intr
->src
[0])[0];
1959 ir3_context_error(ctx
, "Unhandled intrinsic type: %s\n",
1960 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1965 ir3_put_dst(ctx
, &intr
->dest
);
1969 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
1971 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &instr
->def
,
1972 instr
->def
.num_components
);
1974 if (instr
->def
.bit_size
< 32) {
1975 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1976 dst
[i
] = create_immed_typed(ctx
->block
,
1977 instr
->value
[i
].u16
,
1980 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1981 dst
[i
] = create_immed_typed(ctx
->block
,
1982 instr
->value
[i
].u32
,
1989 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
1991 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &undef
->def
,
1992 undef
->def
.num_components
);
1993 type_t type
= (undef
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
1995 /* backend doesn't want undefined instructions, so just plug
1998 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1999 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
2003 * texture fetch/sample instructions:
2007 get_tex_dest_type(nir_tex_instr
*tex
)
2011 switch (nir_alu_type_get_base_type(tex
->dest_type
)) {
2012 case nir_type_invalid
:
2013 case nir_type_float
:
2014 type
= nir_dest_bit_size(tex
->dest
) < 32 ? TYPE_F16
: TYPE_F32
;
2017 type
= nir_dest_bit_size(tex
->dest
) < 32 ? TYPE_S16
: TYPE_S32
;
2021 type
= nir_dest_bit_size(tex
->dest
) < 32 ? TYPE_U16
: TYPE_U32
;
2024 unreachable("bad dest_type");
2031 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2033 unsigned coords
= glsl_get_sampler_dim_coordinate_components(tex
->sampler_dim
);
2036 /* note: would use tex->coord_components.. except txs.. also,
2037 * since array index goes after shadow ref, we don't want to
2041 flags
|= IR3_INSTR_3D
;
2043 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2044 flags
|= IR3_INSTR_S
;
2046 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2047 flags
|= IR3_INSTR_A
;
2053 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2054 * or immediate (in which case it will get lowered later to a non .s2en
2055 * version of the tex instruction which encode tex/samp as immediates:
2057 static struct tex_src_info
2058 get_tex_samp_tex_src(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2060 struct ir3_block
*b
= ctx
->block
;
2061 struct tex_src_info info
= { 0 };
2062 int texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_handle
);
2063 int sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_handle
);
2064 struct ir3_instruction
*texture
, *sampler
;
2066 if (texture_idx
>= 0 || sampler_idx
>= 0) {
2068 info
.flags
|= IR3_INSTR_B
;
2070 /* Gather information required to determine which encoding to
2071 * choose as well as for prefetch.
2073 nir_intrinsic_instr
*bindless_tex
= NULL
;
2075 if (texture_idx
>= 0) {
2076 ctx
->so
->bindless_tex
= true;
2077 bindless_tex
= ir3_bindless_resource(tex
->src
[texture_idx
].src
);
2078 assert(bindless_tex
);
2079 info
.tex_base
= nir_intrinsic_desc_set(bindless_tex
);
2080 tex_const
= nir_src_is_const(bindless_tex
->src
[0]);
2082 info
.tex_idx
= nir_src_as_uint(bindless_tex
->src
[0]);
2084 /* To simplify some of the logic below, assume the index is
2085 * constant 0 when it's not enabled.
2090 nir_intrinsic_instr
*bindless_samp
= NULL
;
2092 if (sampler_idx
>= 0) {
2093 ctx
->so
->bindless_samp
= true;
2094 bindless_samp
= ir3_bindless_resource(tex
->src
[sampler_idx
].src
);
2095 assert(bindless_samp
);
2096 info
.samp_base
= nir_intrinsic_desc_set(bindless_samp
);
2097 samp_const
= nir_src_is_const(bindless_samp
->src
[0]);
2099 info
.samp_idx
= nir_src_as_uint(bindless_samp
->src
[0]);
2105 /* Choose encoding. */
2106 if (tex_const
&& samp_const
&& info
.tex_idx
< 256 && info
.samp_idx
< 256) {
2107 if (info
.tex_idx
< 16 && info
.samp_idx
< 16 &&
2108 (!bindless_tex
|| !bindless_samp
|| info
.tex_base
== info
.samp_base
)) {
2109 /* Everything fits within the instruction */
2110 info
.base
= info
.tex_base
;
2111 info
.combined_idx
= info
.samp_idx
| (info
.tex_idx
<< 4);
2113 info
.base
= info
.tex_base
;
2114 info
.a1_val
= info
.tex_idx
<< 3 | info
.samp_base
;
2115 info
.combined_idx
= info
.samp_idx
;
2116 info
.flags
|= IR3_INSTR_A1EN
;
2118 info
.samp_tex
= NULL
;
2120 info
.flags
|= IR3_INSTR_S2EN
;
2121 /* In the indirect case, we only use a1.x to store the sampler
2122 * base if it differs from the texture base.
2124 if (!bindless_tex
|| !bindless_samp
|| info
.tex_base
== info
.samp_base
) {
2125 info
.base
= info
.tex_base
;
2127 info
.base
= info
.tex_base
;
2128 info
.a1_val
= info
.samp_base
;
2129 info
.flags
|= IR3_INSTR_A1EN
;
2132 /* Note: the indirect source is now a vec2 instead of hvec2, and
2133 * for some reason the texture and sampler are swapped.
2135 struct ir3_instruction
*texture
, *sampler
;
2138 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
2140 texture
= create_immed(b
, 0);
2143 if (bindless_samp
) {
2144 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
2146 sampler
= create_immed(b
, 0);
2148 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2154 info
.flags
|= IR3_INSTR_S2EN
;
2155 texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
);
2156 sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
);
2157 if (texture_idx
>= 0) {
2158 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
2159 texture
= ir3_COV(ctx
->block
, texture
, TYPE_U32
, TYPE_U16
);
2161 /* TODO what to do for dynamic case? I guess we only need the
2162 * max index for astc srgb workaround so maybe not a problem
2163 * to worry about if we don't enable indirect samplers for
2166 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex
->texture_index
);
2167 texture
= create_immed_typed(ctx
->block
, tex
->texture_index
, TYPE_U16
);
2168 info
.tex_idx
= tex
->texture_index
;
2171 if (sampler_idx
>= 0) {
2172 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
2173 sampler
= ir3_COV(ctx
->block
, sampler
, TYPE_U32
, TYPE_U16
);
2175 sampler
= create_immed_typed(ctx
->block
, tex
->sampler_index
, TYPE_U16
);
2176 info
.samp_idx
= tex
->texture_index
;
2179 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2189 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2191 struct ir3_block
*b
= ctx
->block
;
2192 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2193 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2194 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
2195 struct tex_src_info info
= { 0 };
2196 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2197 unsigned i
, coords
, flags
, ncomp
;
2198 unsigned nsrc0
= 0, nsrc1
= 0;
2202 ncomp
= nir_dest_num_components(tex
->dest
);
2204 coord
= off
= ddx
= ddy
= NULL
;
2205 lod
= proj
= compare
= sample_index
= NULL
;
2207 dst
= ir3_get_dst(ctx
, &tex
->dest
, ncomp
);
2209 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2210 switch (tex
->src
[i
].src_type
) {
2211 case nir_tex_src_coord
:
2212 coord
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2214 case nir_tex_src_bias
:
2215 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2218 case nir_tex_src_lod
:
2219 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2222 case nir_tex_src_comparator
: /* shadow comparator */
2223 compare
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2225 case nir_tex_src_projector
:
2226 proj
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2229 case nir_tex_src_offset
:
2230 off
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2233 case nir_tex_src_ddx
:
2234 ddx
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2236 case nir_tex_src_ddy
:
2237 ddy
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2239 case nir_tex_src_ms_index
:
2240 sample_index
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2242 case nir_tex_src_texture_offset
:
2243 case nir_tex_src_sampler_offset
:
2244 case nir_tex_src_texture_handle
:
2245 case nir_tex_src_sampler_handle
:
2246 /* handled in get_tex_samp_src() */
2249 ir3_context_error(ctx
, "Unhandled NIR tex src type: %d\n",
2250 tex
->src
[i
].src_type
);
2256 case nir_texop_tex_prefetch
:
2257 compile_assert(ctx
, !has_bias
);
2258 compile_assert(ctx
, !has_lod
);
2259 compile_assert(ctx
, !compare
);
2260 compile_assert(ctx
, !has_proj
);
2261 compile_assert(ctx
, !has_off
);
2262 compile_assert(ctx
, !ddx
);
2263 compile_assert(ctx
, !ddy
);
2264 compile_assert(ctx
, !sample_index
);
2265 compile_assert(ctx
, nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
) < 0);
2266 compile_assert(ctx
, nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
) < 0);
2268 if (ctx
->so
->num_sampler_prefetch
< IR3_MAX_SAMPLER_PREFETCH
) {
2269 opc
= OPC_META_TEX_PREFETCH
;
2270 ctx
->so
->num_sampler_prefetch
++;
2274 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
2275 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2276 case nir_texop_txl
: opc
= OPC_SAML
; break;
2277 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2278 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2279 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2281 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2282 * what blob does, seems gather is broken?), and a3xx did
2283 * not support it (but probably could also emulate).
2285 switch (tex
->component
) {
2286 case 0: opc
= OPC_GATHER4R
; break;
2287 case 1: opc
= OPC_GATHER4G
; break;
2288 case 2: opc
= OPC_GATHER4B
; break;
2289 case 3: opc
= OPC_GATHER4A
; break;
2292 case nir_texop_txf_ms_fb
:
2293 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
2295 ir3_context_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2299 tex_info(tex
, &flags
, &coords
);
2302 * lay out the first argument in the proper order:
2303 * - actual coordinates first
2304 * - shadow reference
2307 * - starting at offset 4, dpdx.xy, dpdy.xy
2309 * bias/lod go into the second arg
2312 /* insert tex coords: */
2313 for (i
= 0; i
< coords
; i
++)
2318 /* scale up integer coords for TXF based on the LOD */
2319 if (ctx
->compiler
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2321 for (i
= 0; i
< coords
; i
++)
2322 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2326 /* hw doesn't do 1d, so we treat it as 2d with
2327 * height of 1, and patch up the y coord.
2330 src0
[nsrc0
++] = create_immed(b
, 0);
2332 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2336 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2337 src0
[nsrc0
++] = compare
;
2339 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2340 struct ir3_instruction
*idx
= coord
[coords
];
2342 /* the array coord for cube arrays needs 0.5 added to it */
2343 if (ctx
->compiler
->array_index_add_half
&& !is_isam(opc
))
2344 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2346 src0
[nsrc0
++] = idx
;
2350 src0
[nsrc0
++] = proj
;
2351 flags
|= IR3_INSTR_P
;
2354 /* pad to 4, then ddx/ddy: */
2355 if (tex
->op
== nir_texop_txd
) {
2357 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2358 for (i
= 0; i
< coords
; i
++)
2359 src0
[nsrc0
++] = ddx
[i
];
2361 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2362 for (i
= 0; i
< coords
; i
++)
2363 src0
[nsrc0
++] = ddy
[i
];
2365 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2368 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2369 * with scaled x coord according to requested sample:
2371 if (opc
== OPC_ISAMM
) {
2372 if (ctx
->compiler
->txf_ms_with_isaml
) {
2373 /* the samples are laid out in x dimension as
2375 * x_ms = (x << ms) + sample_index;
2377 struct ir3_instruction
*ms
;
2378 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
2380 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
2381 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
2385 src0
[nsrc0
++] = sample_index
;
2390 * second argument (if applicable):
2395 if (has_off
| has_lod
| has_bias
) {
2397 unsigned off_coords
= coords
;
2398 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2400 for (i
= 0; i
< off_coords
; i
++)
2401 src1
[nsrc1
++] = off
[i
];
2403 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2404 flags
|= IR3_INSTR_O
;
2407 if (has_lod
| has_bias
)
2408 src1
[nsrc1
++] = lod
;
2411 type
= get_tex_dest_type(tex
);
2413 if (opc
== OPC_GETLOD
)
2417 if (tex
->op
== nir_texop_txf_ms_fb
) {
2418 /* only expect a single txf_ms_fb per shader: */
2419 compile_assert(ctx
, !ctx
->so
->fb_read
);
2420 compile_assert(ctx
, ctx
->so
->type
== MESA_SHADER_FRAGMENT
);
2422 ctx
->so
->fb_read
= true;
2423 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2424 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2425 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2427 info
.flags
= IR3_INSTR_S2EN
;
2429 ctx
->so
->num_samp
++;
2431 info
= get_tex_samp_tex_src(ctx
, tex
);
2434 struct ir3_instruction
*col0
= ir3_create_collect(ctx
, src0
, nsrc0
);
2435 struct ir3_instruction
*col1
= ir3_create_collect(ctx
, src1
, nsrc1
);
2437 if (opc
== OPC_META_TEX_PREFETCH
) {
2438 int idx
= nir_tex_instr_src_index(tex
, nir_tex_src_coord
);
2440 compile_assert(ctx
, tex
->src
[idx
].src
.is_ssa
);
2442 sam
= ir3_META_TEX_PREFETCH(b
);
2443 __ssa_dst(sam
)->wrmask
= MASK(ncomp
); /* dst */
2444 __ssa_src(sam
, get_barycentric_pixel(ctx
), 0);
2445 sam
->prefetch
.input_offset
=
2446 ir3_nir_coord_offset(tex
->src
[idx
].src
.ssa
);
2447 /* make sure not to add irrelevant flags like S2EN */
2448 sam
->flags
= flags
| (info
.flags
& IR3_INSTR_B
);
2449 sam
->prefetch
.tex
= info
.tex_idx
;
2450 sam
->prefetch
.samp
= info
.samp_idx
;
2451 sam
->prefetch
.tex_base
= info
.tex_base
;
2452 sam
->prefetch
.samp_base
= info
.samp_base
;
2454 info
.flags
|= flags
;
2455 sam
= emit_sam(ctx
, opc
, info
, type
, MASK(ncomp
), col0
, col1
);
2458 if ((ctx
->astc_srgb
& (1 << tex
->texture_index
)) && !nir_tex_instr_is_query(tex
)) {
2459 assert(opc
!= OPC_META_TEX_PREFETCH
);
2461 /* only need first 3 components: */
2462 sam
->regs
[0]->wrmask
= 0x7;
2463 ir3_split_dest(b
, dst
, sam
, 0, 3);
2465 /* we need to sample the alpha separately with a non-ASTC
2468 sam
= ir3_SAM(b
, opc
, type
, 0b1000, flags
| info
.flags
,
2469 info
.samp_tex
, col0
, col1
);
2471 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2473 /* fixup .w component: */
2474 ir3_split_dest(b
, &dst
[3], sam
, 3, 1);
2476 /* normal (non-workaround) case: */
2477 ir3_split_dest(b
, dst
, sam
, 0, ncomp
);
2480 /* GETLOD returns results in 4.8 fixed point */
2481 if (opc
== OPC_GETLOD
) {
2482 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2484 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2485 for (i
= 0; i
< 2; i
++) {
2486 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_S32
, TYPE_F32
), 0,
2491 ir3_put_dst(ctx
, &tex
->dest
);
2495 emit_tex_info(struct ir3_context
*ctx
, nir_tex_instr
*tex
, unsigned idx
)
2497 struct ir3_block
*b
= ctx
->block
;
2498 struct ir3_instruction
**dst
, *sam
;
2499 type_t dst_type
= get_tex_dest_type(tex
);
2500 struct tex_src_info info
= get_tex_samp_tex_src(ctx
, tex
);
2502 dst
= ir3_get_dst(ctx
, &tex
->dest
, 1);
2504 sam
= emit_sam(ctx
, OPC_GETINFO
, info
, dst_type
, 1 << idx
, NULL
, NULL
);
2506 /* even though there is only one component, since it ends
2507 * up in .y/.z/.w rather than .x, we need a split_dest()
2510 ir3_split_dest(b
, dst
, sam
, 0, idx
+ 1);
2512 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2513 * the value in TEX_CONST_0 is zero-based.
2515 if (ctx
->compiler
->levels_add_one
)
2516 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2518 ir3_put_dst(ctx
, &tex
->dest
);
2522 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2524 struct ir3_block
*b
= ctx
->block
;
2525 struct ir3_instruction
**dst
, *sam
;
2526 struct ir3_instruction
*lod
;
2527 unsigned flags
, coords
;
2528 type_t dst_type
= get_tex_dest_type(tex
);
2529 struct tex_src_info info
= get_tex_samp_tex_src(ctx
, tex
);
2531 tex_info(tex
, &flags
, &coords
);
2532 info
.flags
|= flags
;
2534 /* Actually we want the number of dimensions, not coordinates. This
2535 * distinction only matters for cubes.
2537 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2540 dst
= ir3_get_dst(ctx
, &tex
->dest
, 4);
2542 compile_assert(ctx
, tex
->num_srcs
== 1);
2543 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2545 lod
= ir3_get_src(ctx
, &tex
->src
[0].src
)[0];
2547 sam
= emit_sam(ctx
, OPC_GETSIZE
, info
, dst_type
, 0b1111, lod
, NULL
);
2548 ir3_split_dest(b
, dst
, sam
, 0, 4);
2550 /* Array size actually ends up in .w rather than .z. This doesn't
2551 * matter for miplevel 0, but for higher mips the value in z is
2552 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2553 * returned, which means that we have to add 1 to it for arrays.
2555 if (tex
->is_array
) {
2556 if (ctx
->compiler
->levels_add_one
) {
2557 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2559 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2563 ir3_put_dst(ctx
, &tex
->dest
);
2567 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2569 switch (jump
->type
) {
2570 case nir_jump_break
:
2571 case nir_jump_continue
:
2572 case nir_jump_return
:
2573 /* I *think* we can simply just ignore this, and use the
2574 * successor block link to figure out where we need to
2575 * jump to for break/continue
2579 ir3_context_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2585 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2587 switch (instr
->type
) {
2588 case nir_instr_type_alu
:
2589 emit_alu(ctx
, nir_instr_as_alu(instr
));
2591 case nir_instr_type_deref
:
2592 /* ignored, handled as part of the intrinsic they are src to */
2594 case nir_instr_type_intrinsic
:
2595 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2597 case nir_instr_type_load_const
:
2598 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2600 case nir_instr_type_ssa_undef
:
2601 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2603 case nir_instr_type_tex
: {
2604 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2605 /* couple tex instructions get special-cased:
2609 emit_tex_txs(ctx
, tex
);
2611 case nir_texop_query_levels
:
2612 emit_tex_info(ctx
, tex
, 2);
2614 case nir_texop_texture_samples
:
2615 emit_tex_info(ctx
, tex
, 3);
2623 case nir_instr_type_jump
:
2624 emit_jump(ctx
, nir_instr_as_jump(instr
));
2626 case nir_instr_type_phi
:
2627 /* we have converted phi webs to regs in NIR by now */
2628 ir3_context_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2630 case nir_instr_type_call
:
2631 case nir_instr_type_parallel_copy
:
2632 ir3_context_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2637 static struct ir3_block
*
2638 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2640 struct ir3_block
*block
;
2641 struct hash_entry
*hentry
;
2643 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2645 return hentry
->data
;
2647 block
= ir3_block_create(ctx
->ir
);
2648 block
->nblock
= nblock
;
2649 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2651 block
->predecessors
= _mesa_pointer_set_create(block
);
2652 set_foreach(nblock
->predecessors
, sentry
) {
2653 _mesa_set_add(block
->predecessors
, get_block(ctx
, sentry
->key
));
2660 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2662 struct ir3_block
*block
= get_block(ctx
, nblock
);
2664 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2665 if (nblock
->successors
[i
]) {
2666 block
->successors
[i
] =
2667 get_block(ctx
, nblock
->successors
[i
]);
2672 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2674 /* re-emit addr register in each block if needed: */
2675 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr0_ht
); i
++) {
2676 _mesa_hash_table_destroy(ctx
->addr0_ht
[i
], NULL
);
2677 ctx
->addr0_ht
[i
] = NULL
;
2680 _mesa_hash_table_u64_destroy(ctx
->addr1_ht
, NULL
);
2681 ctx
->addr1_ht
= NULL
;
2683 nir_foreach_instr (instr
, nblock
) {
2684 ctx
->cur_instr
= instr
;
2685 emit_instr(ctx
, instr
);
2686 ctx
->cur_instr
= NULL
;
2692 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2695 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2697 struct ir3_instruction
*condition
= ir3_get_src(ctx
, &nif
->condition
)[0];
2699 ctx
->block
->condition
=
2700 ir3_get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2702 emit_cf_list(ctx
, &nif
->then_list
);
2703 emit_cf_list(ctx
, &nif
->else_list
);
2707 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2709 emit_cf_list(ctx
, &nloop
->body
);
2714 stack_push(struct ir3_context
*ctx
)
2717 ctx
->max_stack
= MAX2(ctx
->max_stack
, ctx
->stack
);
2721 stack_pop(struct ir3_context
*ctx
)
2723 compile_assert(ctx
, ctx
->stack
> 0);
2728 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2730 foreach_list_typed (nir_cf_node
, node
, node
, list
) {
2731 switch (node
->type
) {
2732 case nir_cf_node_block
:
2733 emit_block(ctx
, nir_cf_node_as_block(node
));
2735 case nir_cf_node_if
:
2737 emit_if(ctx
, nir_cf_node_as_if(node
));
2740 case nir_cf_node_loop
:
2742 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2745 case nir_cf_node_function
:
2746 ir3_context_error(ctx
, "TODO\n");
2752 /* emit stream-out code. At this point, the current block is the original
2753 * (nir) end block, and nir ensures that all flow control paths terminate
2754 * into the end block. We re-purpose the original end block to generate
2755 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2756 * block holding stream-out write instructions, followed by the new end
2760 * p0.x = (vtxcnt < maxvtxcnt)
2761 * // succs: blockStreamOut, blockNewEnd
2764 * ... stream-out instructions ...
2765 * // succs: blockNewEnd
2771 emit_stream_out(struct ir3_context
*ctx
)
2773 struct ir3
*ir
= ctx
->ir
;
2774 struct ir3_stream_output_info
*strmout
=
2775 &ctx
->so
->shader
->stream_output
;
2776 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2777 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2778 struct ir3_instruction
*bases
[IR3_MAX_SO_BUFFERS
];
2780 /* create vtxcnt input in input block at top of shader,
2781 * so that it is seen as live over the entire duration
2784 vtxcnt
= create_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, 0x1);
2785 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2787 /* at this point, we are at the original 'end' block,
2788 * re-purpose this block to stream-out condition, then
2789 * append stream-out block and new-end block
2791 orig_end_block
= ctx
->block
;
2793 // TODO these blocks need to update predecessors..
2794 // maybe w/ store_global intrinsic, we could do this
2795 // stuff in nir->nir pass
2797 stream_out_block
= ir3_block_create(ir
);
2798 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2800 new_end_block
= ir3_block_create(ir
);
2801 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2803 orig_end_block
->successors
[0] = stream_out_block
;
2804 orig_end_block
->successors
[1] = new_end_block
;
2805 stream_out_block
->successors
[0] = new_end_block
;
2807 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2808 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2809 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2810 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
2811 cond
->cat2
.condition
= IR3_COND_LT
;
2813 /* condition goes on previous block to the conditional,
2814 * since it is used to pick which of the two successor
2817 orig_end_block
->condition
= cond
;
2819 /* switch to stream_out_block to generate the stream-out
2822 ctx
->block
= stream_out_block
;
2824 /* Calculate base addresses based on vtxcnt. Instructions
2825 * generated for bases not used in following loop will be
2826 * stripped out in the backend.
2828 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2829 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
2830 unsigned stride
= strmout
->stride
[i
];
2831 struct ir3_instruction
*base
, *off
;
2833 base
= create_uniform(ctx
->block
, regid(const_state
->offsets
.tfbo
, i
));
2835 /* 24-bit should be enough: */
2836 off
= ir3_MUL_U24(ctx
->block
, vtxcnt
, 0,
2837 create_immed(ctx
->block
, stride
* 4), 0);
2839 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2842 /* Generate the per-output store instructions: */
2843 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2844 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2845 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2846 struct ir3_instruction
*base
, *out
, *stg
;
2848 base
= bases
[strmout
->output
[i
].output_buffer
];
2849 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2851 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2852 create_immed(ctx
->block
, 1), 0);
2853 stg
->cat6
.type
= TYPE_U32
;
2854 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2856 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2860 /* and finally switch to the new_end_block: */
2861 ctx
->block
= new_end_block
;
2865 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2867 nir_metadata_require(impl
, nir_metadata_block_index
);
2869 compile_assert(ctx
, ctx
->stack
== 0);
2871 emit_cf_list(ctx
, &impl
->body
);
2872 emit_block(ctx
, impl
->end_block
);
2874 compile_assert(ctx
, ctx
->stack
== 0);
2876 /* at this point, we should have a single empty block,
2877 * into which we emit the 'end' instruction.
2879 compile_assert(ctx
, list_is_empty(&ctx
->block
->instr_list
));
2881 /* If stream-out (aka transform-feedback) enabled, emit the
2882 * stream-out instructions, followed by a new empty block (into
2883 * which the 'end' instruction lands).
2885 * NOTE: it is done in this order, rather than inserting before
2886 * we emit end_block, because NIR guarantees that all blocks
2887 * flow into end_block, and that end_block has no successors.
2888 * So by re-purposing end_block as the first block of stream-
2889 * out, we guarantee that all exit paths flow into the stream-
2892 if ((ctx
->compiler
->gpu_id
< 500) &&
2893 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2894 !ctx
->so
->binning_pass
) {
2895 debug_assert(ctx
->so
->type
== MESA_SHADER_VERTEX
);
2896 emit_stream_out(ctx
);
2899 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2900 * NOP and has an epilogue that writes the VS outputs to local storage, to
2901 * be read by the HS. Then it resets execution mask (chmask) and chains
2902 * to the next shader (chsh).
2904 if ((ctx
->so
->type
== MESA_SHADER_VERTEX
&&
2905 (ctx
->so
->key
.has_gs
|| ctx
->so
->key
.tessellation
)) ||
2906 (ctx
->so
->type
== MESA_SHADER_TESS_EVAL
&& ctx
->so
->key
.has_gs
)) {
2907 struct ir3_instruction
*chmask
=
2908 ir3_CHMASK(ctx
->block
);
2909 chmask
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2910 chmask
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2912 struct ir3_instruction
*chsh
=
2913 ir3_CHSH(ctx
->block
);
2914 chsh
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2915 chsh
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2917 ir3_END(ctx
->block
);
2922 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2924 struct ir3_shader_variant
*so
= ctx
->so
;
2925 unsigned ncomp
= glsl_get_components(in
->type
);
2926 unsigned n
= in
->data
.driver_location
;
2927 unsigned frac
= in
->data
.location_frac
;
2928 unsigned slot
= in
->data
.location
;
2930 /* Inputs are loaded using ldlw or ldg for these stages. */
2931 if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
||
2932 ctx
->so
->type
== MESA_SHADER_TESS_EVAL
||
2933 ctx
->so
->type
== MESA_SHADER_GEOMETRY
)
2936 /* skip unread inputs, we could end up with (for example), unsplit
2937 * matrix/etc inputs in the case they are not read, so just silently
2943 so
->inputs
[n
].slot
= slot
;
2944 so
->inputs
[n
].compmask
|= (1 << (ncomp
+ frac
)) - 1;
2945 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2946 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2948 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2950 /* if any varyings have 'sample' qualifer, that triggers us
2951 * to run in per-sample mode:
2953 so
->per_samp
|= in
->data
.sample
;
2955 for (int i
= 0; i
< ncomp
; i
++) {
2956 struct ir3_instruction
*instr
= NULL
;
2957 unsigned idx
= (n
* 4) + i
+ frac
;
2959 if (slot
== VARYING_SLOT_POS
) {
2960 ir3_context_error(ctx
, "fragcoord should be a sysval!\n");
2961 } else if (slot
== VARYING_SLOT_PNTC
) {
2962 /* see for example st_nir_fixup_varying_slots().. this is
2963 * maybe a bit mesa/st specific. But we need things to line
2964 * up for this in fdN_program:
2965 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2966 * if (emit->sprite_coord_enable & texmask) {
2970 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2971 so
->inputs
[n
].bary
= true;
2972 instr
= create_frag_input(ctx
, false, idx
);
2974 /* detect the special case for front/back colors where
2975 * we need to do flat vs smooth shading depending on
2978 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2980 case VARYING_SLOT_COL0
:
2981 case VARYING_SLOT_COL1
:
2982 case VARYING_SLOT_BFC0
:
2983 case VARYING_SLOT_BFC1
:
2984 so
->inputs
[n
].rasterflat
= true;
2991 if (ctx
->compiler
->flat_bypass
) {
2992 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2993 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2994 so
->inputs
[n
].use_ldlv
= true;
2997 so
->inputs
[n
].bary
= true;
2999 instr
= create_frag_input(ctx
, so
->inputs
[n
].use_ldlv
, idx
);
3002 compile_assert(ctx
, idx
< ctx
->ninputs
);
3004 ctx
->inputs
[idx
] = instr
;
3006 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
3007 struct ir3_instruction
*input
= NULL
, *in
;
3008 struct ir3_instruction
*components
[4];
3009 unsigned mask
= (1 << (ncomp
+ frac
)) - 1;
3011 foreach_input (in
, ctx
->ir
) {
3012 if (in
->input
.inidx
== n
) {
3019 input
= create_input(ctx
, mask
);
3020 input
->input
.inidx
= n
;
3022 input
->regs
[0]->wrmask
|= mask
;
3025 ir3_split_dest(ctx
->block
, components
, input
, frac
, ncomp
);
3027 for (int i
= 0; i
< ncomp
; i
++) {
3028 unsigned idx
= (n
* 4) + i
+ frac
;
3029 compile_assert(ctx
, idx
< ctx
->ninputs
);
3030 ctx
->inputs
[idx
] = components
[i
];
3033 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3036 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== MESA_SHADER_VERTEX
)) {
3037 so
->total_in
+= ncomp
;
3041 /* Initially we assign non-packed inloc's for varyings, as we don't really
3042 * know up-front which components will be unused. After all the compilation
3043 * stages we scan the shader to see which components are actually used, and
3044 * re-pack the inlocs to eliminate unneeded varyings.
3047 pack_inlocs(struct ir3_context
*ctx
)
3049 struct ir3_shader_variant
*so
= ctx
->so
;
3050 uint8_t used_components
[so
->inputs_count
];
3052 memset(used_components
, 0, sizeof(used_components
));
3055 * First Step: scan shader to find which bary.f/ldlv remain:
3058 foreach_block (block
, &ctx
->ir
->block_list
) {
3059 foreach_instr (instr
, &block
->instr_list
) {
3060 if (is_input(instr
)) {
3061 unsigned inloc
= instr
->regs
[1]->iim_val
;
3062 unsigned i
= inloc
/ 4;
3063 unsigned j
= inloc
% 4;
3065 compile_assert(ctx
, instr
->regs
[1]->flags
& IR3_REG_IMMED
);
3066 compile_assert(ctx
, i
< so
->inputs_count
);
3068 used_components
[i
] |= 1 << j
;
3069 } else if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3070 for (int n
= 0; n
< 2; n
++) {
3071 unsigned inloc
= instr
->prefetch
.input_offset
+ n
;
3072 unsigned i
= inloc
/ 4;
3073 unsigned j
= inloc
% 4;
3075 compile_assert(ctx
, i
< so
->inputs_count
);
3077 used_components
[i
] |= 1 << j
;
3084 * Second Step: reassign varying inloc/slots:
3087 unsigned actual_in
= 0;
3090 for (unsigned i
= 0; i
< so
->inputs_count
; i
++) {
3091 unsigned compmask
= 0, maxcomp
= 0;
3093 so
->inputs
[i
].inloc
= inloc
;
3094 so
->inputs
[i
].bary
= false;
3096 for (unsigned j
= 0; j
< 4; j
++) {
3097 if (!(used_components
[i
] & (1 << j
)))
3100 compmask
|= (1 << j
);
3104 /* at this point, since used_components[i] mask is only
3105 * considering varyings (ie. not sysvals) we know this
3108 so
->inputs
[i
].bary
= true;
3111 if (so
->inputs
[i
].bary
) {
3113 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3119 * Third Step: reassign packed inloc's:
3122 foreach_block (block
, &ctx
->ir
->block_list
) {
3123 foreach_instr (instr
, &block
->instr_list
) {
3124 if (is_input(instr
)) {
3125 unsigned inloc
= instr
->regs
[1]->iim_val
;
3126 unsigned i
= inloc
/ 4;
3127 unsigned j
= inloc
% 4;
3129 instr
->regs
[1]->iim_val
= so
->inputs
[i
].inloc
+ j
;
3130 } else if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3131 unsigned i
= instr
->prefetch
.input_offset
/ 4;
3132 unsigned j
= instr
->prefetch
.input_offset
% 4;
3133 instr
->prefetch
.input_offset
= so
->inputs
[i
].inloc
+ j
;
3140 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3142 struct ir3_shader_variant
*so
= ctx
->so
;
3143 unsigned ncomp
= glsl_get_components(out
->type
);
3144 unsigned n
= out
->data
.driver_location
;
3145 unsigned frac
= out
->data
.location_frac
;
3146 unsigned slot
= out
->data
.location
;
3149 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3151 case FRAG_RESULT_DEPTH
:
3152 comp
= 2; /* tgsi will write to .z component */
3153 so
->writes_pos
= true;
3155 case FRAG_RESULT_COLOR
:
3158 case FRAG_RESULT_SAMPLE_MASK
:
3159 so
->writes_smask
= true;
3162 if (slot
>= FRAG_RESULT_DATA0
)
3164 ir3_context_error(ctx
, "unknown FS output name: %s\n",
3165 gl_frag_result_name(slot
));
3167 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
3168 ctx
->so
->type
== MESA_SHADER_TESS_EVAL
||
3169 ctx
->so
->type
== MESA_SHADER_GEOMETRY
) {
3171 case VARYING_SLOT_POS
:
3172 so
->writes_pos
= true;
3174 case VARYING_SLOT_PSIZ
:
3175 so
->writes_psize
= true;
3177 case VARYING_SLOT_PRIMITIVE_ID
:
3178 case VARYING_SLOT_LAYER
:
3179 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3
:
3180 debug_assert(ctx
->so
->type
== MESA_SHADER_GEOMETRY
);
3182 case VARYING_SLOT_COL0
:
3183 case VARYING_SLOT_COL1
:
3184 case VARYING_SLOT_BFC0
:
3185 case VARYING_SLOT_BFC1
:
3186 case VARYING_SLOT_FOGC
:
3187 case VARYING_SLOT_CLIP_DIST0
:
3188 case VARYING_SLOT_CLIP_DIST1
:
3189 case VARYING_SLOT_CLIP_VERTEX
:
3192 if (slot
>= VARYING_SLOT_VAR0
)
3194 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3196 ir3_context_error(ctx
, "unknown %s shader output name: %s\n",
3197 _mesa_shader_stage_to_string(ctx
->so
->type
),
3198 gl_varying_slot_name(slot
));
3200 } else if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
) {
3201 /* output lowered to buffer writes. */
3204 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3207 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3209 so
->outputs
[n
].slot
= slot
;
3210 so
->outputs
[n
].regid
= regid(n
, comp
);
3211 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3213 for (int i
= 0; i
< ncomp
; i
++) {
3214 unsigned idx
= (n
* 4) + i
+ frac
;
3215 compile_assert(ctx
, idx
< ctx
->noutputs
);
3216 ctx
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3219 /* if varying packing doesn't happen, we could end up in a situation
3220 * with "holes" in the output, and since the per-generation code that
3221 * sets up varying linkage registers doesn't expect to have more than
3222 * one varying per vec4 slot, pad the holes.
3224 * Note that this should probably generate a performance warning of
3227 for (int i
= 0; i
< frac
; i
++) {
3228 unsigned idx
= (n
* 4) + i
;
3229 if (!ctx
->outputs
[idx
]) {
3230 ctx
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3236 max_drvloc(struct exec_list
*vars
)
3239 nir_foreach_variable (var
, vars
) {
3240 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3246 emit_instructions(struct ir3_context
*ctx
)
3248 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3250 ctx
->ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3251 ctx
->noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3253 ctx
->inputs
= rzalloc_array(ctx
, struct ir3_instruction
*, ctx
->ninputs
);
3254 ctx
->outputs
= rzalloc_array(ctx
, struct ir3_instruction
*, ctx
->noutputs
);
3256 ctx
->ir
= ir3_create(ctx
->compiler
, ctx
->so
->type
);
3258 /* Create inputs in first block: */
3259 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3260 ctx
->in_block
= ctx
->block
;
3261 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3263 /* for fragment shader, the vcoord input register is used as the
3264 * base for bary.f varying fetch instrs:
3266 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3267 * until emit_intrinsic when we know they are actually needed.
3268 * For now, we defer creating ctx->ij_centroid, etc, since we
3269 * only need ij_pixel for "old style" varying inputs (ie.
3272 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3273 ctx
->ij_pixel
= create_input(ctx
, 0x3);
3277 nir_foreach_variable (var
, &ctx
->s
->inputs
) {
3278 setup_input(ctx
, var
);
3281 /* Defer add_sysval_input() stuff until after setup_inputs(),
3282 * because sysvals need to be appended after varyings:
3284 if (ctx
->ij_pixel
) {
3285 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
,
3286 0x3, ctx
->ij_pixel
);
3290 /* Tesselation shaders always need primitive ID for indexing the
3291 * BO. Geometry shaders don't always need it but when they do it has be
3292 * delivered and unclobbered in the VS. To make things easy, we always
3293 * make room for it in VS/DS.
3295 bool has_tess
= ctx
->so
->key
.tessellation
!= IR3_TESS_NONE
;
3296 bool has_gs
= ctx
->so
->key
.has_gs
;
3297 switch (ctx
->so
->type
) {
3298 case MESA_SHADER_VERTEX
:
3300 ctx
->tcs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_TCS_HEADER_IR3
, 0x1);
3301 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3302 } else if (has_gs
) {
3303 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3304 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3307 case MESA_SHADER_TESS_CTRL
:
3308 ctx
->tcs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_TCS_HEADER_IR3
, 0x1);
3309 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3311 case MESA_SHADER_TESS_EVAL
:
3313 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3314 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3316 case MESA_SHADER_GEOMETRY
:
3317 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3318 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3324 /* Setup outputs: */
3325 nir_foreach_variable (var
, &ctx
->s
->outputs
) {
3326 setup_output(ctx
, var
);
3329 /* Find # of samplers: */
3330 nir_foreach_variable (var
, &ctx
->s
->uniforms
) {
3331 ctx
->so
->num_samp
+= glsl_type_get_sampler_count(var
->type
);
3332 /* just assume that we'll be reading from images.. if it
3333 * is write-only we don't have to count it, but not sure
3334 * if there is a good way to know?
3336 ctx
->so
->num_samp
+= glsl_type_get_image_count(var
->type
);
3339 /* NOTE: need to do something more clever when we support >1 fxn */
3340 nir_foreach_register (reg
, &fxn
->registers
) {
3341 ir3_declare_array(ctx
, reg
);
3343 /* And emit the body: */
3345 emit_function(ctx
, fxn
);
3348 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3349 * need to assign the tex state indexes for these after we know the
3353 fixup_astc_srgb(struct ir3_context
*ctx
)
3355 struct ir3_shader_variant
*so
= ctx
->so
;
3356 /* indexed by original tex idx, value is newly assigned alpha sampler
3357 * state tex idx. Zero is invalid since there is at least one sampler
3360 unsigned alt_tex_state
[16] = {0};
3361 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3364 so
->astc_srgb
.base
= tex_idx
;
3366 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3367 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3369 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3371 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3372 /* assign new alternate/alpha tex state slot: */
3373 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3374 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3375 so
->astc_srgb
.count
++;
3378 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3383 fixup_binning_pass(struct ir3_context
*ctx
)
3385 struct ir3_shader_variant
*so
= ctx
->so
;
3386 struct ir3
*ir
= ctx
->ir
;
3389 /* first pass, remove unused outputs from the IR level outputs: */
3390 for (i
= 0, j
= 0; i
< ir
->outputs_count
; i
++) {
3391 struct ir3_instruction
*out
= ir
->outputs
[i
];
3392 assert(out
->opc
== OPC_META_COLLECT
);
3393 unsigned outidx
= out
->collect
.outidx
;
3394 unsigned slot
= so
->outputs
[outidx
].slot
;
3396 /* throw away everything but first position/psize */
3397 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3398 ir
->outputs
[j
] = ir
->outputs
[i
];
3402 ir
->outputs_count
= j
;
3404 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3407 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3408 unsigned slot
= so
->outputs
[i
].slot
;
3410 /* throw away everything but first position/psize */
3411 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3412 so
->outputs
[j
] = so
->outputs
[i
];
3414 /* fixup outidx to point to new output table entry: */
3415 struct ir3_instruction
*out
;
3416 foreach_output (out
, ir
) {
3417 if (out
->collect
.outidx
== i
) {
3418 out
->collect
.outidx
= j
;
3426 so
->outputs_count
= j
;
3430 collect_tex_prefetches(struct ir3_context
*ctx
, struct ir3
*ir
)
3434 /* Collect sampling instructions eligible for pre-dispatch. */
3435 foreach_block (block
, &ir
->block_list
) {
3436 foreach_instr_safe (instr
, &block
->instr_list
) {
3437 if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3438 assert(idx
< ARRAY_SIZE(ctx
->so
->sampler_prefetch
));
3439 struct ir3_sampler_prefetch
*fetch
=
3440 &ctx
->so
->sampler_prefetch
[idx
];
3443 if (instr
->flags
& IR3_INSTR_B
) {
3444 fetch
->cmd
= IR3_SAMPLER_BINDLESS_PREFETCH_CMD
;
3445 /* In bindless mode, the index is actually the base */
3446 fetch
->tex_id
= instr
->prefetch
.tex_base
;
3447 fetch
->samp_id
= instr
->prefetch
.samp_base
;
3448 fetch
->tex_bindless_id
= instr
->prefetch
.tex
;
3449 fetch
->samp_bindless_id
= instr
->prefetch
.samp
;
3451 fetch
->cmd
= IR3_SAMPLER_PREFETCH_CMD
;
3452 fetch
->tex_id
= instr
->prefetch
.tex
;
3453 fetch
->samp_id
= instr
->prefetch
.samp
;
3455 fetch
->wrmask
= instr
->regs
[0]->wrmask
;
3456 fetch
->dst
= instr
->regs
[0]->num
;
3457 fetch
->src
= instr
->prefetch
.input_offset
;
3460 MAX2(ctx
->so
->total_in
, instr
->prefetch
.input_offset
+ 2);
3462 /* Disable half precision until supported. */
3463 fetch
->half_precision
= !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
3465 /* Remove the prefetch placeholder instruction: */
3466 list_delinit(&instr
->node
);
3473 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3474 struct ir3_shader_variant
*so
)
3476 struct ir3_context
*ctx
;
3478 int ret
= 0, max_bary
;
3482 ctx
= ir3_context_init(compiler
, so
);
3484 DBG("INIT failed!");
3489 emit_instructions(ctx
);
3492 DBG("EMIT failed!");
3497 ir
= so
->ir
= ctx
->ir
;
3499 assert((ctx
->noutputs
% 4) == 0);
3501 /* Setup IR level outputs, which are "collects" that gather
3502 * the scalar components of outputs.
3504 for (unsigned i
= 0; i
< ctx
->noutputs
; i
+= 4) {
3506 /* figure out the # of components written:
3508 * TODO do we need to handle holes, ie. if .x and .z
3509 * components written, but .y component not written?
3511 for (unsigned j
= 0; j
< 4; j
++) {
3512 if (!ctx
->outputs
[i
+ j
])
3517 /* Note that in some stages, like TCS, store_output is
3518 * lowered to memory writes, so no components of the
3519 * are "written" from the PoV of traditional store-
3520 * output instructions:
3525 struct ir3_instruction
*out
=
3526 ir3_create_collect(ctx
, &ctx
->outputs
[i
], ncomp
);
3529 assert(outidx
< so
->outputs_count
);
3531 /* stash index into so->outputs[] so we can map the
3532 * output back to slot/etc later:
3534 out
->collect
.outidx
= outidx
;
3536 array_insert(ir
, ir
->outputs
, out
);
3539 /* Set up the gs header as an output for the vertex shader so it won't
3540 * clobber it for the tess ctrl shader.
3542 * TODO this could probably be done more cleanly in a nir pass.
3544 if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
3545 (ctx
->so
->key
.has_gs
&& ctx
->so
->type
== MESA_SHADER_TESS_EVAL
)) {
3546 if (ctx
->primitive_id
) {
3547 unsigned n
= so
->outputs_count
++;
3548 so
->outputs
[n
].slot
= VARYING_SLOT_PRIMITIVE_ID
;
3550 struct ir3_instruction
*out
=
3551 ir3_create_collect(ctx
, &ctx
->primitive_id
, 1);
3552 out
->collect
.outidx
= n
;
3553 array_insert(ir
, ir
->outputs
, out
);
3556 if (ctx
->gs_header
) {
3557 unsigned n
= so
->outputs_count
++;
3558 so
->outputs
[n
].slot
= VARYING_SLOT_GS_HEADER_IR3
;
3559 struct ir3_instruction
*out
=
3560 ir3_create_collect(ctx
, &ctx
->gs_header
, 1);
3561 out
->collect
.outidx
= n
;
3562 array_insert(ir
, ir
->outputs
, out
);
3565 if (ctx
->tcs_header
) {
3566 unsigned n
= so
->outputs_count
++;
3567 so
->outputs
[n
].slot
= VARYING_SLOT_TCS_HEADER_IR3
;
3568 struct ir3_instruction
*out
=
3569 ir3_create_collect(ctx
, &ctx
->tcs_header
, 1);
3570 out
->collect
.outidx
= n
;
3571 array_insert(ir
, ir
->outputs
, out
);
3575 /* at this point, for binning pass, throw away unneeded outputs: */
3576 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
< 600))
3577 fixup_binning_pass(ctx
);
3579 ir3_debug_print(ir
, "BEFORE CF");
3583 ir3_debug_print(ir
, "BEFORE CP");
3587 /* at this point, for binning pass, throw away unneeded outputs:
3588 * Note that for a6xx and later, we do this after ir3_cp to ensure
3589 * that the uniform/constant layout for BS and VS matches, so that
3590 * we can re-use same VS_CONST state group.
3592 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
>= 600))
3593 fixup_binning_pass(ctx
);
3595 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3596 * need to make sure not to remove any inputs that are used by
3597 * the nonbinning VS.
3599 if (ctx
->compiler
->gpu_id
>= 600 && so
->binning_pass
&&
3600 so
->type
== MESA_SHADER_VERTEX
) {
3601 for (int i
= 0; i
< ctx
->ninputs
; i
++) {
3602 struct ir3_instruction
*in
= ctx
->inputs
[i
];
3610 debug_assert(n
< so
->nonbinning
->inputs_count
);
3612 if (so
->nonbinning
->inputs
[n
].sysval
)
3615 /* be sure to keep inputs, even if only used in VS */
3616 if (so
->nonbinning
->inputs
[n
].compmask
& (1 << c
))
3617 array_insert(in
->block
, in
->block
->keeps
, in
);
3621 ir3_debug_print(ir
, "BEFORE GROUPING");
3623 ir3_sched_add_deps(ir
);
3625 /* Group left/right neighbors, inserting mov's where needed to
3630 ir3_debug_print(ir
, "AFTER GROUPING");
3634 ir3_debug_print(ir
, "AFTER DEPTH");
3636 /* do Sethi–Ullman numbering before scheduling: */
3639 ret
= ir3_sched(ir
);
3641 DBG("SCHED failed!");
3645 ir3_debug_print(ir
, "AFTER SCHED");
3647 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3648 * with draw pass VS, so binning and draw pass can both use the
3651 * Note that VS inputs are expected to be full precision.
3653 bool pre_assign_inputs
= (ir
->compiler
->gpu_id
>= 600) &&
3654 (ir
->type
== MESA_SHADER_VERTEX
) &&
3657 if (pre_assign_inputs
) {
3658 for (unsigned i
= 0; i
< ctx
->ninputs
; i
++) {
3659 struct ir3_instruction
*instr
= ctx
->inputs
[i
];
3666 unsigned regid
= so
->nonbinning
->inputs
[n
].regid
+ c
;
3668 instr
->regs
[0]->num
= regid
;
3671 ret
= ir3_ra(so
, ctx
->inputs
, ctx
->ninputs
);
3672 } else if (ctx
->tcs_header
) {
3673 /* We need to have these values in the same registers between VS and TCS
3674 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3677 ctx
->tcs_header
->regs
[0]->num
= regid(0, 0);
3678 ctx
->primitive_id
->regs
[0]->num
= regid(0, 1);
3679 struct ir3_instruction
*precolor
[] = { ctx
->tcs_header
, ctx
->primitive_id
};
3680 ret
= ir3_ra(so
, precolor
, ARRAY_SIZE(precolor
));
3681 } else if (ctx
->gs_header
) {
3682 /* We need to have these values in the same registers between producer
3683 * (VS or DS) and GS since the producer chains to GS and doesn't get
3684 * the sysvals redelivered.
3687 ctx
->gs_header
->regs
[0]->num
= regid(0, 0);
3688 ctx
->primitive_id
->regs
[0]->num
= regid(0, 1);
3689 struct ir3_instruction
*precolor
[] = { ctx
->gs_header
, ctx
->primitive_id
};
3690 ret
= ir3_ra(so
, precolor
, ARRAY_SIZE(precolor
));
3691 } else if (so
->num_sampler_prefetch
) {
3692 assert(so
->type
== MESA_SHADER_FRAGMENT
);
3693 struct ir3_instruction
*instr
, *precolor
[2];
3696 foreach_input (instr
, ir
) {
3697 if (instr
->input
.sysval
!= SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
)
3700 assert(idx
< ARRAY_SIZE(precolor
));
3702 precolor
[idx
] = instr
;
3703 instr
->regs
[0]->num
= idx
;
3707 ret
= ir3_ra(so
, precolor
, idx
);
3709 ret
= ir3_ra(so
, NULL
, 0);
3718 ir3_debug_print(ir
, "AFTER POSTSCHED");
3720 if (compiler
->gpu_id
>= 600) {
3721 if (ir3_a6xx_fixup_atomic_dests(ir
, so
)) {
3722 ir3_debug_print(ir
, "AFTER ATOMIC FIXUP");
3726 if (so
->type
== MESA_SHADER_FRAGMENT
)
3730 * Fixup inputs/outputs to point to the actual registers assigned:
3732 * 1) initialize to r63.x (invalid/unused)
3733 * 2) iterate IR level inputs/outputs and update the variants
3734 * inputs/outputs table based on the assigned registers for
3735 * the remaining inputs/outputs.
3738 for (unsigned i
= 0; i
< so
->inputs_count
; i
++)
3739 so
->inputs
[i
].regid
= INVALID_REG
;
3740 for (unsigned i
= 0; i
< so
->outputs_count
; i
++)
3741 so
->outputs
[i
].regid
= INVALID_REG
;
3743 struct ir3_instruction
*out
;
3744 foreach_output (out
, ir
) {
3745 assert(out
->opc
== OPC_META_COLLECT
);
3746 unsigned outidx
= out
->collect
.outidx
;
3748 so
->outputs
[outidx
].regid
= out
->regs
[0]->num
;
3749 so
->outputs
[outidx
].half
= !!(out
->regs
[0]->flags
& IR3_REG_HALF
);
3752 struct ir3_instruction
*in
;
3753 foreach_input (in
, ir
) {
3754 assert(in
->opc
== OPC_META_INPUT
);
3755 unsigned inidx
= in
->input
.inidx
;
3757 if (pre_assign_inputs
&& !so
->inputs
[inidx
].sysval
) {
3758 if (VALIDREG(so
->nonbinning
->inputs
[inidx
].regid
)) {
3759 compile_assert(ctx
, in
->regs
[0]->num
==
3760 so
->nonbinning
->inputs
[inidx
].regid
);
3761 compile_assert(ctx
, !!(in
->regs
[0]->flags
& IR3_REG_HALF
) ==
3762 so
->nonbinning
->inputs
[inidx
].half
);
3764 so
->inputs
[inidx
].regid
= so
->nonbinning
->inputs
[inidx
].regid
;
3765 so
->inputs
[inidx
].half
= so
->nonbinning
->inputs
[inidx
].half
;
3767 so
->inputs
[inidx
].regid
= in
->regs
[0]->num
;
3768 so
->inputs
[inidx
].half
= !!(in
->regs
[0]->flags
& IR3_REG_HALF
);
3773 fixup_astc_srgb(ctx
);
3775 /* We need to do legalize after (for frag shader's) the "bary.f"
3776 * offsets (inloc) have been assigned.
3778 ir3_legalize(ir
, so
, &max_bary
);
3780 ir3_debug_print(ir
, "AFTER LEGALIZE");
3782 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3783 * know what we might have to wait on when coming in from VS chsh.
3785 if (so
->type
== MESA_SHADER_TESS_CTRL
||
3786 so
->type
== MESA_SHADER_GEOMETRY
) {
3787 foreach_block (block
, &ir
->block_list
) {
3788 foreach_instr (instr
, &block
->instr_list
) {
3789 instr
->flags
|= IR3_INSTR_SS
| IR3_INSTR_SY
;
3795 so
->branchstack
= ctx
->max_stack
;
3797 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3798 if (so
->type
== MESA_SHADER_FRAGMENT
)
3799 so
->total_in
= max_bary
+ 1;
3801 so
->max_sun
= ir
->max_sun
;
3803 /* Collect sampling instructions eligible for pre-dispatch. */
3804 collect_tex_prefetches(ctx
, ir
);
3806 if (so
->type
== MESA_SHADER_FRAGMENT
&&
3807 ctx
->s
->info
.fs
.needs_helper_invocations
)
3808 so
->need_pixlod
= true;
3813 ir3_destroy(so
->ir
);
3816 ir3_context_free(ctx
);