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freedreno/ir3: Fix the type of half-float indirect uniform loads.
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42 void
43 ir3_handle_bindless_cat6(struct ir3_instruction *instr, nir_src rsrc)
44 {
45 nir_intrinsic_instr *intrin = ir3_bindless_resource(rsrc);
46 if (!intrin)
47 return;
48
49 instr->flags |= IR3_INSTR_B;
50 instr->cat6.base = nir_intrinsic_desc_set(intrin);
51 }
52
53 static struct ir3_instruction *
54 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
55 struct ir3_instruction *address, struct ir3_instruction *collect)
56 {
57 struct ir3_block *block = ctx->block;
58 struct ir3_instruction *mov;
59 struct ir3_register *src;
60
61 mov = ir3_instr_create(block, OPC_MOV);
62 mov->cat1.src_type = TYPE_U32;
63 mov->cat1.dst_type = TYPE_U32;
64 __ssa_dst(mov);
65 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
66 src->size = arrsz;
67 src->array.offset = n;
68
69 ir3_instr_set_address(mov, address);
70
71 return mov;
72 }
73
74 static struct ir3_instruction *
75 create_input(struct ir3_context *ctx, unsigned compmask)
76 {
77 struct ir3_instruction *in;
78
79 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
80 in->input.sysval = ~0;
81 __ssa_dst(in)->wrmask = compmask;
82
83 array_insert(ctx->ir, ctx->ir->inputs, in);
84
85 return in;
86 }
87
88 static struct ir3_instruction *
89 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
90 {
91 struct ir3_block *block = ctx->block;
92 struct ir3_instruction *instr;
93 /* packed inloc is fixed up later: */
94 struct ir3_instruction *inloc = create_immed(block, n);
95
96 if (use_ldlv) {
97 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
98 instr->cat6.type = TYPE_U32;
99 instr->cat6.iim_val = 1;
100 } else {
101 instr = ir3_BARY_F(block, inloc, 0, ctx->ij[IJ_PERSP_PIXEL], 0);
102 instr->regs[2]->wrmask = 0x3;
103 }
104
105 return instr;
106 }
107
108 static struct ir3_instruction *
109 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
110 {
111 /* first four vec4 sysval's reserved for UBOs: */
112 /* NOTE: dp is in scalar, but there can be >4 dp components: */
113 struct ir3_const_state *const_state = ir3_const_state(ctx->so);
114 unsigned n = const_state->offsets.driver_param;
115 unsigned r = regid(n + dp / 4, dp % 4);
116 return create_uniform(ctx->block, r);
117 }
118
119 /*
120 * Adreno's comparisons produce a 1 for true and 0 for false, in either 16 or
121 * 32-bit registers. We use NIR's 1-bit integers to represent bools, and
122 * trust that we will only see and/or/xor on those 1-bit values, so we can
123 * safely store NIR i1s in a 32-bit reg while always containing either a 1 or
124 * 0.
125 */
126
127 /*
128 * alu/sfu instructions:
129 */
130
131 static struct ir3_instruction *
132 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
133 unsigned src_bitsize, nir_op op)
134 {
135 type_t src_type, dst_type;
136
137 switch (op) {
138 case nir_op_f2f32:
139 case nir_op_f2f16_rtne:
140 case nir_op_f2f16_rtz:
141 case nir_op_f2f16:
142 case nir_op_f2i32:
143 case nir_op_f2i16:
144 case nir_op_f2i8:
145 case nir_op_f2u32:
146 case nir_op_f2u16:
147 case nir_op_f2u8:
148 switch (src_bitsize) {
149 case 32:
150 src_type = TYPE_F32;
151 break;
152 case 16:
153 src_type = TYPE_F16;
154 break;
155 default:
156 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
157 }
158 break;
159
160 case nir_op_i2f32:
161 case nir_op_i2f16:
162 case nir_op_i2i32:
163 case nir_op_i2i16:
164 case nir_op_i2i8:
165 switch (src_bitsize) {
166 case 32:
167 src_type = TYPE_S32;
168 break;
169 case 16:
170 src_type = TYPE_S16;
171 break;
172 case 8:
173 src_type = TYPE_S8;
174 break;
175 default:
176 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
177 }
178 break;
179
180 case nir_op_u2f32:
181 case nir_op_u2f16:
182 case nir_op_u2u32:
183 case nir_op_u2u16:
184 case nir_op_u2u8:
185 switch (src_bitsize) {
186 case 32:
187 src_type = TYPE_U32;
188 break;
189 case 16:
190 src_type = TYPE_U16;
191 break;
192 case 8:
193 src_type = TYPE_U8;
194 break;
195 default:
196 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
197 }
198 break;
199
200 case nir_op_b2f16:
201 case nir_op_b2f32:
202 case nir_op_b2i8:
203 case nir_op_b2i16:
204 case nir_op_b2i32:
205 src_type = TYPE_U32;
206 break;
207
208 default:
209 ir3_context_error(ctx, "invalid conversion op: %u", op);
210 }
211
212 switch (op) {
213 case nir_op_f2f32:
214 case nir_op_i2f32:
215 case nir_op_u2f32:
216 case nir_op_b2f32:
217 dst_type = TYPE_F32;
218 break;
219
220 case nir_op_f2f16_rtne:
221 case nir_op_f2f16_rtz:
222 case nir_op_f2f16:
223 case nir_op_i2f16:
224 case nir_op_u2f16:
225 case nir_op_b2f16:
226 dst_type = TYPE_F16;
227 break;
228
229 case nir_op_f2i32:
230 case nir_op_i2i32:
231 case nir_op_b2i32:
232 dst_type = TYPE_S32;
233 break;
234
235 case nir_op_f2i16:
236 case nir_op_i2i16:
237 case nir_op_b2i16:
238 dst_type = TYPE_S16;
239 break;
240
241 case nir_op_f2i8:
242 case nir_op_i2i8:
243 case nir_op_b2i8:
244 dst_type = TYPE_S8;
245 break;
246
247 case nir_op_f2u32:
248 case nir_op_u2u32:
249 dst_type = TYPE_U32;
250 break;
251
252 case nir_op_f2u16:
253 case nir_op_u2u16:
254 dst_type = TYPE_U16;
255 break;
256
257 case nir_op_f2u8:
258 case nir_op_u2u8:
259 dst_type = TYPE_U8;
260 break;
261
262 default:
263 ir3_context_error(ctx, "invalid conversion op: %u", op);
264 }
265
266 if (src_type == dst_type)
267 return src;
268
269 struct ir3_instruction *cov =
270 ir3_COV(ctx->block, src, src_type, dst_type);
271
272 if (op == nir_op_f2f16_rtne)
273 cov->regs[0]->flags |= IR3_REG_EVEN;
274
275 return cov;
276 }
277
278 static void
279 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
280 {
281 const nir_op_info *info = &nir_op_infos[alu->op];
282 struct ir3_instruction **dst, *src[info->num_inputs];
283 unsigned bs[info->num_inputs]; /* bit size */
284 struct ir3_block *b = ctx->block;
285 unsigned dst_sz, wrmask;
286 type_t dst_type = nir_dest_bit_size(alu->dest.dest) == 16 ?
287 TYPE_U16 : TYPE_U32;
288
289 if (alu->dest.dest.is_ssa) {
290 dst_sz = alu->dest.dest.ssa.num_components;
291 wrmask = (1 << dst_sz) - 1;
292 } else {
293 dst_sz = alu->dest.dest.reg.reg->num_components;
294 wrmask = alu->dest.write_mask;
295 }
296
297 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
298
299 /* Vectors are special in that they have non-scalarized writemasks,
300 * and just take the first swizzle channel for each argument in
301 * order into each writemask channel.
302 */
303 if ((alu->op == nir_op_vec2) ||
304 (alu->op == nir_op_vec3) ||
305 (alu->op == nir_op_vec4)) {
306
307 for (int i = 0; i < info->num_inputs; i++) {
308 nir_alu_src *asrc = &alu->src[i];
309
310 compile_assert(ctx, !asrc->abs);
311 compile_assert(ctx, !asrc->negate);
312
313 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
314 if (!src[i])
315 src[i] = create_immed_typed(ctx->block, 0, dst_type);
316 dst[i] = ir3_MOV(b, src[i], dst_type);
317 }
318
319 ir3_put_dst(ctx, &alu->dest.dest);
320 return;
321 }
322
323 /* We also get mov's with more than one component for mov's so
324 * handle those specially:
325 */
326 if (alu->op == nir_op_mov) {
327 nir_alu_src *asrc = &alu->src[0];
328 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
329
330 for (unsigned i = 0; i < dst_sz; i++) {
331 if (wrmask & (1 << i)) {
332 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
333 } else {
334 dst[i] = NULL;
335 }
336 }
337
338 ir3_put_dst(ctx, &alu->dest.dest);
339 return;
340 }
341
342 /* General case: We can just grab the one used channel per src. */
343 for (int i = 0; i < info->num_inputs; i++) {
344 unsigned chan = ffs(alu->dest.write_mask) - 1;
345 nir_alu_src *asrc = &alu->src[i];
346
347 compile_assert(ctx, !asrc->abs);
348 compile_assert(ctx, !asrc->negate);
349
350 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
351 bs[i] = nir_src_bit_size(asrc->src);
352
353 compile_assert(ctx, src[i]);
354 }
355
356 switch (alu->op) {
357 case nir_op_f2f32:
358 case nir_op_f2f16_rtne:
359 case nir_op_f2f16_rtz:
360 case nir_op_f2f16:
361 case nir_op_f2i32:
362 case nir_op_f2i16:
363 case nir_op_f2i8:
364 case nir_op_f2u32:
365 case nir_op_f2u16:
366 case nir_op_f2u8:
367 case nir_op_i2f32:
368 case nir_op_i2f16:
369 case nir_op_i2i32:
370 case nir_op_i2i16:
371 case nir_op_i2i8:
372 case nir_op_u2f32:
373 case nir_op_u2f16:
374 case nir_op_u2u32:
375 case nir_op_u2u16:
376 case nir_op_u2u8:
377 case nir_op_b2f16:
378 case nir_op_b2f32:
379 case nir_op_b2i8:
380 case nir_op_b2i16:
381 case nir_op_b2i32:
382 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
383 break;
384
385 case nir_op_fquantize2f16:
386 dst[0] = create_cov(ctx,
387 create_cov(ctx, src[0], 32, nir_op_f2f16),
388 16, nir_op_f2f32);
389 break;
390 case nir_op_f2b1:
391 dst[0] = ir3_CMPS_F(b,
392 src[0], 0,
393 create_immed_typed(b, 0, bs[0] == 16 ? TYPE_F16 : TYPE_F32), 0);
394 dst[0]->cat2.condition = IR3_COND_NE;
395 break;
396
397 case nir_op_i2b1:
398 /* i2b1 will appear when translating from nir_load_ubo or
399 * nir_intrinsic_load_ssbo, where any non-zero value is true.
400 */
401 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
402 dst[0]->cat2.condition = IR3_COND_NE;
403 break;
404
405 case nir_op_b2b1:
406 /* b2b1 will appear when translating from
407 *
408 * - nir_intrinsic_load_shared of a 32-bit 0/~0 value.
409 * - nir_intrinsic_load_constant of a 32-bit 0/~0 value
410 *
411 * A negate can turn those into a 1 or 0 for us.
412 */
413 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
414 break;
415
416 case nir_op_b2b32:
417 /* b2b32 will appear when converting our 1-bit bools to a store_shared
418 * argument.
419 *
420 * A negate can turn those into a ~0 for us.
421 */
422 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
423 break;
424
425 case nir_op_fneg:
426 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
427 break;
428 case nir_op_fabs:
429 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
430 break;
431 case nir_op_fmax:
432 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
433 break;
434 case nir_op_fmin:
435 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
436 break;
437 case nir_op_fsat:
438 /* if there is just a single use of the src, and it supports
439 * (sat) bit, we can just fold the (sat) flag back to the
440 * src instruction and create a mov. This is easier for cp
441 * to eliminate.
442 *
443 * NOTE: a3xx definitely seen not working with flat bary.f. Same test
444 * uses ldlv on a4xx+, so not definitive. Seems rare enough to apply
445 * everywhere.
446 *
447 * TODO probably opc_cat==4 is ok too
448 */
449 if (alu->src[0].src.is_ssa &&
450 src[0]->opc != OPC_BARY_F &&
451 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
452 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
453 src[0]->flags |= IR3_INSTR_SAT;
454 dst[0] = ir3_MOV(b, src[0], dst_type);
455 } else {
456 /* otherwise generate a max.f that saturates.. blob does
457 * similar (generating a cat2 mov using max.f)
458 */
459 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
460 dst[0]->flags |= IR3_INSTR_SAT;
461 }
462 break;
463 case nir_op_fmul:
464 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
465 break;
466 case nir_op_fadd:
467 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
468 break;
469 case nir_op_fsub:
470 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
471 break;
472 case nir_op_ffma:
473 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
474 break;
475 case nir_op_fddx:
476 case nir_op_fddx_coarse:
477 dst[0] = ir3_DSX(b, src[0], 0);
478 dst[0]->cat5.type = TYPE_F32;
479 break;
480 case nir_op_fddx_fine:
481 dst[0] = ir3_DSXPP_MACRO(b, src[0], 0);
482 dst[0]->cat5.type = TYPE_F32;
483 break;
484 case nir_op_fddy:
485 case nir_op_fddy_coarse:
486 dst[0] = ir3_DSY(b, src[0], 0);
487 dst[0]->cat5.type = TYPE_F32;
488 break;
489 break;
490 case nir_op_fddy_fine:
491 dst[0] = ir3_DSYPP_MACRO(b, src[0], 0);
492 dst[0]->cat5.type = TYPE_F32;
493 break;
494 case nir_op_flt:
495 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
496 dst[0]->cat2.condition = IR3_COND_LT;
497 break;
498 case nir_op_fge:
499 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
500 dst[0]->cat2.condition = IR3_COND_GE;
501 break;
502 case nir_op_feq:
503 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
504 dst[0]->cat2.condition = IR3_COND_EQ;
505 break;
506 case nir_op_fne:
507 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
508 dst[0]->cat2.condition = IR3_COND_NE;
509 break;
510 case nir_op_fceil:
511 dst[0] = ir3_CEIL_F(b, src[0], 0);
512 break;
513 case nir_op_ffloor:
514 dst[0] = ir3_FLOOR_F(b, src[0], 0);
515 break;
516 case nir_op_ftrunc:
517 dst[0] = ir3_TRUNC_F(b, src[0], 0);
518 break;
519 case nir_op_fround_even:
520 dst[0] = ir3_RNDNE_F(b, src[0], 0);
521 break;
522 case nir_op_fsign:
523 dst[0] = ir3_SIGN_F(b, src[0], 0);
524 break;
525
526 case nir_op_fsin:
527 dst[0] = ir3_SIN(b, src[0], 0);
528 break;
529 case nir_op_fcos:
530 dst[0] = ir3_COS(b, src[0], 0);
531 break;
532 case nir_op_frsq:
533 dst[0] = ir3_RSQ(b, src[0], 0);
534 break;
535 case nir_op_frcp:
536 dst[0] = ir3_RCP(b, src[0], 0);
537 break;
538 case nir_op_flog2:
539 dst[0] = ir3_LOG2(b, src[0], 0);
540 break;
541 case nir_op_fexp2:
542 dst[0] = ir3_EXP2(b, src[0], 0);
543 break;
544 case nir_op_fsqrt:
545 dst[0] = ir3_SQRT(b, src[0], 0);
546 break;
547
548 case nir_op_iabs:
549 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
550 break;
551 case nir_op_iadd:
552 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
553 break;
554 case nir_op_iand:
555 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
556 break;
557 case nir_op_imax:
558 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
559 break;
560 case nir_op_umax:
561 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
562 break;
563 case nir_op_imin:
564 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_umin:
567 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
568 break;
569 case nir_op_umul_low:
570 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
571 break;
572 case nir_op_imadsh_mix16:
573 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
574 break;
575 case nir_op_imad24_ir3:
576 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
577 break;
578 case nir_op_imul24:
579 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
580 break;
581 case nir_op_ineg:
582 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
583 break;
584 case nir_op_inot:
585 if (bs[0] == 1) {
586 dst[0] = ir3_SUB_U(b, create_immed(ctx->block, 1), 0, src[0], 0);
587 } else {
588 dst[0] = ir3_NOT_B(b, src[0], 0);
589 }
590 break;
591 case nir_op_ior:
592 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
593 break;
594 case nir_op_ishl:
595 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
596 break;
597 case nir_op_ishr:
598 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
599 break;
600 case nir_op_isub:
601 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
602 break;
603 case nir_op_ixor:
604 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
605 break;
606 case nir_op_ushr:
607 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
608 break;
609 case nir_op_ilt:
610 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
611 dst[0]->cat2.condition = IR3_COND_LT;
612 break;
613 case nir_op_ige:
614 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
615 dst[0]->cat2.condition = IR3_COND_GE;
616 break;
617 case nir_op_ieq:
618 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
619 dst[0]->cat2.condition = IR3_COND_EQ;
620 break;
621 case nir_op_ine:
622 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
623 dst[0]->cat2.condition = IR3_COND_NE;
624 break;
625 case nir_op_ult:
626 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
627 dst[0]->cat2.condition = IR3_COND_LT;
628 break;
629 case nir_op_uge:
630 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
631 dst[0]->cat2.condition = IR3_COND_GE;
632 break;
633
634 case nir_op_bcsel: {
635 struct ir3_instruction *cond = src[0];
636
637 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
638 * we can ignore that and use original cond, since the nonzero-ness of
639 * cond stays the same.
640 */
641 if (cond->opc == OPC_ABSNEG_S &&
642 cond->flags == 0 &&
643 (cond->regs[1]->flags & (IR3_REG_SNEG | IR3_REG_SABS)) == IR3_REG_SNEG) {
644 cond = cond->regs[1]->instr;
645 }
646
647 compile_assert(ctx, bs[1] == bs[2]);
648 /* The condition's size has to match the other two arguments' size, so
649 * convert down if necessary.
650 */
651 if (bs[1] == 16) {
652 struct hash_entry *prev_entry =
653 _mesa_hash_table_search(ctx->sel_cond_conversions, src[0]);
654 if (prev_entry) {
655 cond = prev_entry->data;
656 } else {
657 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
658 _mesa_hash_table_insert(ctx->sel_cond_conversions, src[0], cond);
659 }
660 }
661
662 if (bs[1] != 16)
663 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
664 else
665 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
666 break;
667 }
668 case nir_op_bit_count: {
669 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
670 // double check on earlier gen's. Once half-precision support is
671 // in place, this should probably move to a NIR lowering pass:
672 struct ir3_instruction *hi, *lo;
673
674 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
675 TYPE_U32, TYPE_U16);
676 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
677
678 hi = ir3_CBITS_B(b, hi, 0);
679 lo = ir3_CBITS_B(b, lo, 0);
680
681 // TODO maybe the builders should default to making dst half-precision
682 // if the src's were half precision, to make this less awkward.. otoh
683 // we should probably just do this lowering in NIR.
684 hi->regs[0]->flags |= IR3_REG_HALF;
685 lo->regs[0]->flags |= IR3_REG_HALF;
686
687 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
688 dst[0]->regs[0]->flags |= IR3_REG_HALF;
689 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
690 break;
691 }
692 case nir_op_ifind_msb: {
693 struct ir3_instruction *cmp;
694 dst[0] = ir3_CLZ_S(b, src[0], 0);
695 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
696 cmp->cat2.condition = IR3_COND_GE;
697 dst[0] = ir3_SEL_B32(b,
698 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
699 cmp, 0, dst[0], 0);
700 break;
701 }
702 case nir_op_ufind_msb:
703 dst[0] = ir3_CLZ_B(b, src[0], 0);
704 dst[0] = ir3_SEL_B32(b,
705 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
706 src[0], 0, dst[0], 0);
707 break;
708 case nir_op_find_lsb:
709 dst[0] = ir3_BFREV_B(b, src[0], 0);
710 dst[0] = ir3_CLZ_B(b, dst[0], 0);
711 break;
712 case nir_op_bitfield_reverse:
713 dst[0] = ir3_BFREV_B(b, src[0], 0);
714 break;
715
716 default:
717 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
718 nir_op_infos[alu->op].name);
719 break;
720 }
721
722 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
723 assert(nir_dest_bit_size(alu->dest.dest) == 1 ||
724 alu->op == nir_op_b2b32);
725 assert(dst_sz == 1);
726 } else {
727 /* 1-bit values stored in 32-bit registers are only valid for certain
728 * ALU ops.
729 */
730 switch (alu->op) {
731 case nir_op_iand:
732 case nir_op_ior:
733 case nir_op_ixor:
734 case nir_op_inot:
735 case nir_op_bcsel:
736 break;
737 default:
738 compile_assert(ctx, nir_dest_bit_size(alu->dest.dest) != 1);
739 }
740 }
741
742 ir3_put_dst(ctx, &alu->dest.dest);
743 }
744
745 static void
746 emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr,
747 struct ir3_instruction **dst)
748 {
749 struct ir3_block *b = ctx->block;
750
751 unsigned ncomp = intr->num_components;
752 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
753 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
754 struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0);
755 ldc->regs[0]->wrmask = MASK(ncomp);
756 ldc->cat6.iim_val = ncomp;
757 ldc->cat6.d = nir_intrinsic_base(intr);
758 ldc->cat6.type = TYPE_U32;
759
760 ir3_handle_bindless_cat6(ldc, intr->src[0]);
761 if (ldc->flags & IR3_INSTR_B)
762 ctx->so->bindless_ubo = true;
763
764 ir3_split_dest(b, dst, ldc, 0, ncomp);
765 }
766
767
768 /* handles direct/indirect UBO reads: */
769 static void
770 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
771 struct ir3_instruction **dst)
772 {
773 struct ir3_block *b = ctx->block;
774 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
775 const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
776 unsigned ubo = regid(const_state->offsets.ubo, 0);
777 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
778
779 int off = 0;
780
781 /* First src is ubo index, which could either be an immed or not: */
782 src0 = ir3_get_src(ctx, &intr->src[0])[0];
783 if (is_same_type_mov(src0) &&
784 (src0->regs[1]->flags & IR3_REG_IMMED)) {
785 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
786 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
787 } else {
788 base_lo = create_uniform_indirect(b, ubo, TYPE_U32, ir3_get_addr0(ctx, src0, ptrsz));
789 base_hi = create_uniform_indirect(b, ubo + 1, TYPE_U32, ir3_get_addr0(ctx, src0, ptrsz));
790
791 /* NOTE: since relative addressing is used, make sure constlen is
792 * at least big enough to cover all the UBO addresses, since the
793 * assembler won't know what the max address reg is.
794 */
795 ctx->so->constlen = MAX2(ctx->so->constlen,
796 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
797 }
798
799 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
800 addr = base_lo;
801
802 if (nir_src_is_const(intr->src[1])) {
803 off += nir_src_as_uint(intr->src[1]);
804 } else {
805 /* For load_ubo_indirect, second src is indirect offset: */
806 src1 = ir3_get_src(ctx, &intr->src[1])[0];
807
808 /* and add offset to addr: */
809 addr = ir3_ADD_S(b, addr, 0, src1, 0);
810 }
811
812 /* if offset is to large to encode in the ldg, split it out: */
813 if ((off + (intr->num_components * 4)) > 1024) {
814 /* split out the minimal amount to improve the odds that
815 * cp can fit the immediate in the add.s instruction:
816 */
817 unsigned off2 = off + (intr->num_components * 4) - 1024;
818 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
819 off -= off2;
820 }
821
822 if (ptrsz == 2) {
823 struct ir3_instruction *carry;
824
825 /* handle 32b rollover, ie:
826 * if (addr < base_lo)
827 * base_hi++
828 */
829 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
830 carry->cat2.condition = IR3_COND_LT;
831 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
832
833 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
834 }
835
836 for (int i = 0; i < intr->num_components; i++) {
837 struct ir3_instruction *load =
838 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
839 create_immed(b, off + i * 4), 0);
840 load->cat6.type = TYPE_U32;
841 dst[i] = load;
842 }
843 }
844
845 /* src[] = { block_index } */
846 static void
847 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
848 struct ir3_instruction **dst)
849 {
850 if (ir3_bindless_resource(intr->src[0])) {
851 struct ir3_block *b = ctx->block;
852 struct ir3_instruction *ibo = ir3_ssbo_to_ibo(ctx, intr->src[0]);
853 struct ir3_instruction *resinfo = ir3_RESINFO(b, ibo, 0);
854 resinfo->cat6.iim_val = 1;
855 resinfo->cat6.d = 1;
856 resinfo->cat6.type = TYPE_U32;
857 resinfo->cat6.typed = false;
858 /* resinfo has no writemask and always writes out 3 components */
859 resinfo->regs[0]->wrmask = MASK(3);
860 ir3_handle_bindless_cat6(resinfo, intr->src[0]);
861 struct ir3_instruction *resinfo_dst;
862 ir3_split_dest(b, &resinfo_dst, resinfo, 0, 1);
863 /* Unfortunately resinfo returns the array length, i.e. in dwords,
864 * while NIR expects us to return the size in bytes.
865 *
866 * TODO: fix this in NIR.
867 */
868 *dst = ir3_SHL_B(b, resinfo_dst, 0, create_immed(b, 2), 0);
869 return;
870 }
871
872 /* SSBO size stored as a const starting at ssbo_sizes: */
873 const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
874 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
875 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
876 const_state->ssbo_size.off[blk_idx];
877
878 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
879
880 dst[0] = create_uniform(ctx->block, idx);
881 }
882
883 /* src[] = { offset }. const_index[] = { base } */
884 static void
885 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
886 struct ir3_instruction **dst)
887 {
888 struct ir3_block *b = ctx->block;
889 struct ir3_instruction *ldl, *offset;
890 unsigned base;
891
892 offset = ir3_get_src(ctx, &intr->src[0])[0];
893 base = nir_intrinsic_base(intr);
894
895 ldl = ir3_LDL(b, offset, 0,
896 create_immed(b, intr->num_components), 0,
897 create_immed(b, base), 0);
898
899 ldl->cat6.type = utype_dst(intr->dest);
900 ldl->regs[0]->wrmask = MASK(intr->num_components);
901
902 ldl->barrier_class = IR3_BARRIER_SHARED_R;
903 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
904
905 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
906 }
907
908 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
909 static void
910 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
911 {
912 struct ir3_block *b = ctx->block;
913 struct ir3_instruction *stl, *offset;
914 struct ir3_instruction * const *value;
915 unsigned base, wrmask, ncomp;
916
917 value = ir3_get_src(ctx, &intr->src[0]);
918 offset = ir3_get_src(ctx, &intr->src[1])[0];
919
920 base = nir_intrinsic_base(intr);
921 wrmask = nir_intrinsic_write_mask(intr);
922 ncomp = ffs(~wrmask) - 1;
923
924 assert(wrmask == BITFIELD_MASK(intr->num_components));
925
926 stl = ir3_STL(b, offset, 0,
927 ir3_create_collect(ctx, value, ncomp), 0,
928 create_immed(b, ncomp), 0);
929 stl->cat6.dst_offset = base;
930 stl->cat6.type = utype_src(intr->src[0]);
931 stl->barrier_class = IR3_BARRIER_SHARED_W;
932 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
933
934 array_insert(b, b->keeps, stl);
935 }
936
937 /* src[] = { offset }. const_index[] = { base } */
938 static void
939 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
940 struct ir3_instruction **dst)
941 {
942 struct ir3_block *b = ctx->block;
943 struct ir3_instruction *load, *offset;
944 unsigned base;
945
946 offset = ir3_get_src(ctx, &intr->src[0])[0];
947 base = nir_intrinsic_base(intr);
948
949 load = ir3_LDLW(b, offset, 0,
950 create_immed(b, intr->num_components), 0,
951 create_immed(b, base), 0);
952
953 /* for a650, use LDL for tess ctrl inputs: */
954 if (ctx->so->type == MESA_SHADER_TESS_CTRL && ctx->compiler->tess_use_shared)
955 load->opc = OPC_LDL;
956
957 load->cat6.type = utype_dst(intr->dest);
958 load->regs[0]->wrmask = MASK(intr->num_components);
959
960 load->barrier_class = IR3_BARRIER_SHARED_R;
961 load->barrier_conflict = IR3_BARRIER_SHARED_W;
962
963 ir3_split_dest(b, dst, load, 0, intr->num_components);
964 }
965
966 /* src[] = { value, offset }. const_index[] = { base } */
967 static void
968 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
969 {
970 struct ir3_block *b = ctx->block;
971 struct ir3_instruction *store, *offset;
972 struct ir3_instruction * const *value;
973
974 value = ir3_get_src(ctx, &intr->src[0]);
975 offset = ir3_get_src(ctx, &intr->src[1])[0];
976
977 store = ir3_STLW(b, offset, 0,
978 ir3_create_collect(ctx, value, intr->num_components), 0,
979 create_immed(b, intr->num_components), 0);
980
981 /* for a650, use STL for vertex outputs used by tess ctrl shader: */
982 if (ctx->so->type == MESA_SHADER_VERTEX && ctx->so->key.tessellation &&
983 ctx->compiler->tess_use_shared)
984 store->opc = OPC_STL;
985
986 store->cat6.dst_offset = nir_intrinsic_base(intr);
987 store->cat6.type = utype_src(intr->src[0]);
988 store->barrier_class = IR3_BARRIER_SHARED_W;
989 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
990
991 array_insert(b, b->keeps, store);
992 }
993
994 /*
995 * CS shared variable atomic intrinsics
996 *
997 * All of the shared variable atomic memory operations read a value from
998 * memory, compute a new value using one of the operations below, write the
999 * new value to memory, and return the original value read.
1000 *
1001 * All operations take 2 sources except CompSwap that takes 3. These
1002 * sources represent:
1003 *
1004 * 0: The offset into the shared variable storage region that the atomic
1005 * operation will operate on.
1006 * 1: The data parameter to the atomic function (i.e. the value to add
1007 * in shared_atomic_add, etc).
1008 * 2: For CompSwap only: the second data parameter.
1009 */
1010 static struct ir3_instruction *
1011 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1012 {
1013 struct ir3_block *b = ctx->block;
1014 struct ir3_instruction *atomic, *src0, *src1;
1015 type_t type = TYPE_U32;
1016
1017 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
1018 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
1019
1020 switch (intr->intrinsic) {
1021 case nir_intrinsic_shared_atomic_add:
1022 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
1023 break;
1024 case nir_intrinsic_shared_atomic_imin:
1025 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1026 type = TYPE_S32;
1027 break;
1028 case nir_intrinsic_shared_atomic_umin:
1029 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1030 break;
1031 case nir_intrinsic_shared_atomic_imax:
1032 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1033 type = TYPE_S32;
1034 break;
1035 case nir_intrinsic_shared_atomic_umax:
1036 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1037 break;
1038 case nir_intrinsic_shared_atomic_and:
1039 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1040 break;
1041 case nir_intrinsic_shared_atomic_or:
1042 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1043 break;
1044 case nir_intrinsic_shared_atomic_xor:
1045 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1046 break;
1047 case nir_intrinsic_shared_atomic_exchange:
1048 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1049 break;
1050 case nir_intrinsic_shared_atomic_comp_swap:
1051 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1052 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1053 ir3_get_src(ctx, &intr->src[2])[0],
1054 src1,
1055 }, 2);
1056 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1057 break;
1058 default:
1059 unreachable("boo");
1060 }
1061
1062 atomic->cat6.iim_val = 1;
1063 atomic->cat6.d = 1;
1064 atomic->cat6.type = type;
1065 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1066 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1067
1068 /* even if nothing consume the result, we can't DCE the instruction: */
1069 array_insert(b, b->keeps, atomic);
1070
1071 return atomic;
1072 }
1073
1074 struct tex_src_info {
1075 /* For prefetch */
1076 unsigned tex_base, samp_base, tex_idx, samp_idx;
1077 /* For normal tex instructions */
1078 unsigned base, combined_idx, a1_val, flags;
1079 struct ir3_instruction *samp_tex;
1080 };
1081
1082 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1083 * to handle with the image_mapping table..
1084 */
1085 static struct tex_src_info
1086 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1087 {
1088 struct ir3_block *b = ctx->block;
1089 struct tex_src_info info = { 0 };
1090 nir_intrinsic_instr *bindless_tex = ir3_bindless_resource(intr->src[0]);
1091 ctx->so->bindless_tex = true;
1092
1093 if (bindless_tex) {
1094 /* Bindless case */
1095 info.flags |= IR3_INSTR_B;
1096
1097 /* Gather information required to determine which encoding to
1098 * choose as well as for prefetch.
1099 */
1100 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
1101 bool tex_const = nir_src_is_const(bindless_tex->src[0]);
1102 if (tex_const)
1103 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
1104 info.samp_idx = 0;
1105
1106 /* Choose encoding. */
1107 if (tex_const && info.tex_idx < 256) {
1108 if (info.tex_idx < 16) {
1109 /* Everything fits within the instruction */
1110 info.base = info.tex_base;
1111 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
1112 } else {
1113 info.base = info.tex_base;
1114 info.a1_val = info.tex_idx << 3;
1115 info.combined_idx = 0;
1116 info.flags |= IR3_INSTR_A1EN;
1117 }
1118 info.samp_tex = NULL;
1119 } else {
1120 info.flags |= IR3_INSTR_S2EN;
1121 info.base = info.tex_base;
1122
1123 /* Note: the indirect source is now a vec2 instead of hvec2 */
1124 struct ir3_instruction *texture, *sampler;
1125
1126 texture = ir3_get_src(ctx, &intr->src[0])[0];
1127 sampler = create_immed(b, 0);
1128 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1129 texture,
1130 sampler,
1131 }, 2);
1132 }
1133 } else {
1134 info.flags |= IR3_INSTR_S2EN;
1135 unsigned slot = nir_src_as_uint(intr->src[0]);
1136 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1137 struct ir3_instruction *texture, *sampler;
1138
1139 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1140 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1141
1142 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1143 sampler,
1144 texture,
1145 }, 2);
1146 }
1147
1148 return info;
1149 }
1150
1151 static struct ir3_instruction *
1152 emit_sam(struct ir3_context *ctx, opc_t opc, struct tex_src_info info,
1153 type_t type, unsigned wrmask, struct ir3_instruction *src0,
1154 struct ir3_instruction *src1)
1155 {
1156 struct ir3_instruction *sam, *addr;
1157 if (info.flags & IR3_INSTR_A1EN) {
1158 addr = ir3_get_addr1(ctx, info.a1_val);
1159 }
1160 sam = ir3_SAM(ctx->block, opc, type, 0b1111, info.flags,
1161 info.samp_tex, src0, src1);
1162 if (info.flags & IR3_INSTR_A1EN) {
1163 ir3_instr_set_address(sam, addr);
1164 }
1165 if (info.flags & IR3_INSTR_B) {
1166 sam->cat5.tex_base = info.base;
1167 sam->cat5.samp = info.combined_idx;
1168 }
1169 return sam;
1170 }
1171
1172 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1173 static void
1174 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1175 struct ir3_instruction **dst)
1176 {
1177 struct ir3_block *b = ctx->block;
1178 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1179 struct ir3_instruction *sam;
1180 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1181 struct ir3_instruction *coords[4];
1182 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1183 type_t type = ir3_get_type_for_image_intrinsic(intr);
1184
1185 /* hmm, this seems a bit odd, but it is what blob does and (at least
1186 * a5xx) just faults on bogus addresses otherwise:
1187 */
1188 if (flags & IR3_INSTR_3D) {
1189 flags &= ~IR3_INSTR_3D;
1190 flags |= IR3_INSTR_A;
1191 }
1192 info.flags |= flags;
1193
1194 for (unsigned i = 0; i < ncoords; i++)
1195 coords[i] = src0[i];
1196
1197 if (ncoords == 1)
1198 coords[ncoords++] = create_immed(b, 0);
1199
1200 sam = emit_sam(ctx, OPC_ISAM, info, type, 0b1111,
1201 ir3_create_collect(ctx, coords, ncoords), NULL);
1202
1203 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1204 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1205
1206 ir3_split_dest(b, dst, sam, 0, 4);
1207 }
1208
1209 /* A4xx version of image_size, see ir3_a6xx.c for newer resinfo version. */
1210 void
1211 emit_intrinsic_image_size_tex(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1212 struct ir3_instruction **dst)
1213 {
1214 struct ir3_block *b = ctx->block;
1215 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1216 struct ir3_instruction *sam, *lod;
1217 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1218 type_t dst_type = nir_dest_bit_size(intr->dest) == 16 ?
1219 TYPE_U16 : TYPE_U32;
1220
1221 info.flags |= flags;
1222 lod = create_immed(b, 0);
1223 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
1224
1225 /* Array size actually ends up in .w rather than .z. This doesn't
1226 * matter for miplevel 0, but for higher mips the value in z is
1227 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1228 * returned, which means that we have to add 1 to it for arrays for
1229 * a3xx.
1230 *
1231 * Note use a temporary dst and then copy, since the size of the dst
1232 * array that is passed in is based on nir's understanding of the
1233 * result size, not the hardware's
1234 */
1235 struct ir3_instruction *tmp[4];
1236
1237 ir3_split_dest(b, tmp, sam, 0, 4);
1238
1239 /* get_size instruction returns size in bytes instead of texels
1240 * for imageBuffer, so we need to divide it by the pixel size
1241 * of the image format.
1242 *
1243 * TODO: This is at least true on a5xx. Check other gens.
1244 */
1245 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF) {
1246 /* Since all the possible values the divisor can take are
1247 * power-of-two (4, 8, or 16), the division is implemented
1248 * as a shift-right.
1249 * During shader setup, the log2 of the image format's
1250 * bytes-per-pixel should have been emitted in 2nd slot of
1251 * image_dims. See ir3_shader::emit_image_dims().
1252 */
1253 const struct ir3_const_state *const_state =
1254 ir3_const_state(ctx->so);
1255 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1256 const_state->image_dims.off[nir_src_as_uint(intr->src[0])];
1257 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1258
1259 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1260 }
1261
1262 for (unsigned i = 0; i < ncoords; i++)
1263 dst[i] = tmp[i];
1264
1265 if (flags & IR3_INSTR_A) {
1266 if (ctx->compiler->levels_add_one) {
1267 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1268 } else {
1269 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1270 }
1271 }
1272 }
1273
1274 static void
1275 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1276 {
1277 struct ir3_block *b = ctx->block;
1278 struct ir3_instruction *barrier;
1279
1280 switch (intr->intrinsic) {
1281 case nir_intrinsic_control_barrier:
1282 barrier = ir3_BAR(b);
1283 barrier->cat7.g = true;
1284 barrier->cat7.l = true;
1285 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1286 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1287 break;
1288 case nir_intrinsic_memory_barrier:
1289 barrier = ir3_FENCE(b);
1290 barrier->cat7.g = true;
1291 barrier->cat7.r = true;
1292 barrier->cat7.w = true;
1293 barrier->cat7.l = true;
1294 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1295 IR3_BARRIER_BUFFER_W;
1296 barrier->barrier_conflict =
1297 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1298 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1299 break;
1300 case nir_intrinsic_memory_barrier_buffer:
1301 barrier = ir3_FENCE(b);
1302 barrier->cat7.g = true;
1303 barrier->cat7.r = true;
1304 barrier->cat7.w = true;
1305 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1306 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1307 IR3_BARRIER_BUFFER_W;
1308 break;
1309 case nir_intrinsic_memory_barrier_image:
1310 // TODO double check if this should have .g set
1311 barrier = ir3_FENCE(b);
1312 barrier->cat7.g = true;
1313 barrier->cat7.r = true;
1314 barrier->cat7.w = true;
1315 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1316 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1317 IR3_BARRIER_IMAGE_W;
1318 break;
1319 case nir_intrinsic_memory_barrier_shared:
1320 barrier = ir3_FENCE(b);
1321 barrier->cat7.g = true;
1322 barrier->cat7.l = true;
1323 barrier->cat7.r = true;
1324 barrier->cat7.w = true;
1325 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1326 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1327 IR3_BARRIER_SHARED_W;
1328 break;
1329 case nir_intrinsic_group_memory_barrier:
1330 barrier = ir3_FENCE(b);
1331 barrier->cat7.g = true;
1332 barrier->cat7.l = true;
1333 barrier->cat7.r = true;
1334 barrier->cat7.w = true;
1335 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1336 IR3_BARRIER_IMAGE_W |
1337 IR3_BARRIER_BUFFER_W;
1338 barrier->barrier_conflict =
1339 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1340 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1341 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1342 break;
1343 default:
1344 unreachable("boo");
1345 }
1346
1347 /* make sure barrier doesn't get DCE'd */
1348 array_insert(b, b->keeps, barrier);
1349 }
1350
1351 static void add_sysval_input_compmask(struct ir3_context *ctx,
1352 gl_system_value slot, unsigned compmask,
1353 struct ir3_instruction *instr)
1354 {
1355 struct ir3_shader_variant *so = ctx->so;
1356 unsigned n = so->inputs_count++;
1357
1358 assert(instr->opc == OPC_META_INPUT);
1359 instr->input.inidx = n;
1360 instr->input.sysval = slot;
1361
1362 so->inputs[n].sysval = true;
1363 so->inputs[n].slot = slot;
1364 so->inputs[n].compmask = compmask;
1365 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1366 so->total_in++;
1367 }
1368
1369 static struct ir3_instruction *
1370 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1371 unsigned compmask)
1372 {
1373 assert(compmask);
1374 struct ir3_instruction *sysval = create_input(ctx, compmask);
1375 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1376 return sysval;
1377 }
1378
1379 static struct ir3_instruction *
1380 get_barycentric(struct ir3_context *ctx, enum ir3_bary bary)
1381 {
1382 static const gl_system_value sysval_base = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
1383
1384 STATIC_ASSERT(sysval_base + IJ_PERSP_PIXEL == SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
1385 STATIC_ASSERT(sysval_base + IJ_PERSP_SAMPLE == SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
1386 STATIC_ASSERT(sysval_base + IJ_PERSP_CENTROID == SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
1387 STATIC_ASSERT(sysval_base + IJ_PERSP_SIZE == SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
1388 STATIC_ASSERT(sysval_base + IJ_LINEAR_PIXEL == SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL);
1389 STATIC_ASSERT(sysval_base + IJ_LINEAR_CENTROID == SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID);
1390 STATIC_ASSERT(sysval_base + IJ_LINEAR_SAMPLE == SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE);
1391
1392 if (!ctx->ij[bary]) {
1393 struct ir3_instruction *xy[2];
1394 struct ir3_instruction *ij;
1395
1396 ij = create_sysval_input(ctx, sysval_base + bary, 0x3);
1397 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1398
1399 ctx->ij[bary] = ir3_create_collect(ctx, xy, 2);
1400 }
1401
1402 return ctx->ij[bary];
1403 }
1404
1405 /* TODO: make this a common NIR helper?
1406 * there is a nir_system_value_from_intrinsic but it takes nir_intrinsic_op so it
1407 * can't be extended to work with this
1408 */
1409 static gl_system_value
1410 nir_intrinsic_barycentric_sysval(nir_intrinsic_instr *intr)
1411 {
1412 enum glsl_interp_mode interp_mode = nir_intrinsic_interp_mode(intr);
1413 gl_system_value sysval;
1414
1415 switch (intr->intrinsic) {
1416 case nir_intrinsic_load_barycentric_pixel:
1417 if (interp_mode == INTERP_MODE_NOPERSPECTIVE)
1418 sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL;
1419 else
1420 sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
1421 break;
1422 case nir_intrinsic_load_barycentric_centroid:
1423 if (interp_mode == INTERP_MODE_NOPERSPECTIVE)
1424 sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID;
1425 else
1426 sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID;
1427 break;
1428 case nir_intrinsic_load_barycentric_sample:
1429 if (interp_mode == INTERP_MODE_NOPERSPECTIVE)
1430 sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE;
1431 else
1432 sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE;
1433 break;
1434 default:
1435 unreachable("invalid barycentric intrinsic");
1436 }
1437
1438 return sysval;
1439 }
1440
1441 static void
1442 emit_intrinsic_barycentric(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1443 struct ir3_instruction **dst)
1444 {
1445 gl_system_value sysval = nir_intrinsic_barycentric_sysval(intr);
1446
1447 if (!ctx->so->key.msaa) {
1448 if (sysval == SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE)
1449 sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
1450 if (sysval == SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE)
1451 sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL;
1452 }
1453
1454 enum ir3_bary bary = sysval - SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
1455
1456 struct ir3_instruction *ij = get_barycentric(ctx, bary);
1457 ir3_split_dest(ctx->block, dst, ij, 0, 2);
1458 }
1459
1460 static struct ir3_instruction *
1461 get_frag_coord(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1462 {
1463 if (!ctx->frag_coord) {
1464 struct ir3_block *b = ctx->in_block;
1465 struct ir3_instruction *xyzw[4];
1466 struct ir3_instruction *hw_frag_coord;
1467
1468 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1469 ir3_split_dest(b, xyzw, hw_frag_coord, 0, 4);
1470
1471 /* for frag_coord.xy, we get unsigned values.. we need
1472 * to subtract (integer) 8 and divide by 16 (right-
1473 * shift by 4) then convert to float:
1474 *
1475 * sub.s tmp, src, 8
1476 * shr.b tmp, tmp, 4
1477 * mov.u32f32 dst, tmp
1478 *
1479 */
1480 for (int i = 0; i < 2; i++) {
1481 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1482 xyzw[i] = ir3_MUL_F(b, xyzw[i], 0, create_immed(b, fui(1.0 / 16.0)), 0);
1483 }
1484
1485 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1486 }
1487
1488 ctx->so->fragcoord_compmask |=
1489 nir_ssa_def_components_read(&intr->dest.ssa);
1490
1491 return ctx->frag_coord;
1492 }
1493
1494 static void
1495 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1496 {
1497 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1498 struct ir3_instruction **dst;
1499 struct ir3_instruction * const *src;
1500 struct ir3_block *b = ctx->block;
1501 unsigned dest_components = nir_intrinsic_dest_components(intr);
1502 int idx, comp;
1503
1504 if (info->has_dest) {
1505 dst = ir3_get_dst(ctx, &intr->dest, dest_components);
1506 } else {
1507 dst = NULL;
1508 }
1509
1510 const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
1511 const unsigned primitive_param = const_state->offsets.primitive_param * 4;
1512 const unsigned primitive_map = const_state->offsets.primitive_map * 4;
1513
1514 switch (intr->intrinsic) {
1515 case nir_intrinsic_load_uniform:
1516 idx = nir_intrinsic_base(intr);
1517 if (nir_src_is_const(intr->src[0])) {
1518 idx += nir_src_as_uint(intr->src[0]);
1519 for (int i = 0; i < dest_components; i++) {
1520 dst[i] = create_uniform_typed(b, idx + i,
1521 nir_dest_bit_size(intr->dest) == 16 ? TYPE_F16 : TYPE_F32);
1522 }
1523 } else {
1524 src = ir3_get_src(ctx, &intr->src[0]);
1525 for (int i = 0; i < dest_components; i++) {
1526 dst[i] = create_uniform_indirect(b, idx + i,
1527 nir_dest_bit_size(intr->dest) == 16 ? TYPE_F16 : TYPE_F32,
1528 ir3_get_addr0(ctx, src[0], 1));
1529 }
1530 /* NOTE: if relative addressing is used, we set
1531 * constlen in the compiler (to worst-case value)
1532 * since we don't know in the assembler what the max
1533 * addr reg value can be:
1534 */
1535 ctx->so->constlen = MAX2(ctx->so->constlen,
1536 const_state->ubo_state.size / 16);
1537 }
1538 break;
1539
1540 case nir_intrinsic_load_vs_primitive_stride_ir3:
1541 dst[0] = create_uniform(b, primitive_param + 0);
1542 break;
1543 case nir_intrinsic_load_vs_vertex_stride_ir3:
1544 dst[0] = create_uniform(b, primitive_param + 1);
1545 break;
1546 case nir_intrinsic_load_hs_patch_stride_ir3:
1547 dst[0] = create_uniform(b, primitive_param + 2);
1548 break;
1549 case nir_intrinsic_load_patch_vertices_in:
1550 dst[0] = create_uniform(b, primitive_param + 3);
1551 break;
1552 case nir_intrinsic_load_tess_param_base_ir3:
1553 dst[0] = create_uniform(b, primitive_param + 4);
1554 dst[1] = create_uniform(b, primitive_param + 5);
1555 break;
1556 case nir_intrinsic_load_tess_factor_base_ir3:
1557 dst[0] = create_uniform(b, primitive_param + 6);
1558 dst[1] = create_uniform(b, primitive_param + 7);
1559 break;
1560
1561 case nir_intrinsic_load_primitive_location_ir3:
1562 idx = nir_intrinsic_driver_location(intr);
1563 dst[0] = create_uniform(b, primitive_map + idx);
1564 break;
1565
1566 case nir_intrinsic_load_gs_header_ir3:
1567 dst[0] = ctx->gs_header;
1568 break;
1569 case nir_intrinsic_load_tcs_header_ir3:
1570 dst[0] = ctx->tcs_header;
1571 break;
1572
1573 case nir_intrinsic_load_primitive_id:
1574 dst[0] = ctx->primitive_id;
1575 break;
1576
1577 case nir_intrinsic_load_tess_coord:
1578 if (!ctx->tess_coord) {
1579 ctx->tess_coord =
1580 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1581 }
1582 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1583
1584 /* Unused, but ir3_put_dst() below wants to free something */
1585 dst[2] = create_immed(b, 0);
1586 break;
1587
1588 case nir_intrinsic_end_patch_ir3:
1589 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1590 struct ir3_instruction *end = ir3_PREDE(b);
1591 array_insert(b, b->keeps, end);
1592
1593 end->barrier_class = IR3_BARRIER_EVERYTHING;
1594 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1595 break;
1596
1597 case nir_intrinsic_store_global_ir3: {
1598 struct ir3_instruction *value, *addr, *offset;
1599 unsigned ncomp = nir_intrinsic_src_components(intr, 0);
1600
1601 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1602 ir3_get_src(ctx, &intr->src[1])[0],
1603 ir3_get_src(ctx, &intr->src[1])[1]
1604 }, 2);
1605
1606 offset = ir3_get_src(ctx, &intr->src[2])[0];
1607
1608 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp);
1609
1610 struct ir3_instruction *stg =
1611 ir3_STG_G(ctx->block, addr, 0, value, 0,
1612 create_immed(ctx->block, ncomp), 0, offset, 0);
1613 stg->cat6.type = TYPE_U32;
1614 stg->cat6.iim_val = 1;
1615
1616 array_insert(b, b->keeps, stg);
1617
1618 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1619 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1620 break;
1621 }
1622
1623 case nir_intrinsic_load_global_ir3: {
1624 struct ir3_instruction *addr, *offset;
1625
1626 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1627 ir3_get_src(ctx, &intr->src[0])[0],
1628 ir3_get_src(ctx, &intr->src[0])[1]
1629 }, 2);
1630
1631 offset = ir3_get_src(ctx, &intr->src[1])[0];
1632
1633 struct ir3_instruction *load =
1634 ir3_LDG(b, addr, 0, create_immed(ctx->block, dest_components),
1635 0, offset, 0);
1636 load->cat6.type = TYPE_U32;
1637 load->regs[0]->wrmask = MASK(dest_components);
1638
1639 load->barrier_class = IR3_BARRIER_BUFFER_R;
1640 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1641
1642 ir3_split_dest(b, dst, load, 0, dest_components);
1643 break;
1644 }
1645
1646 case nir_intrinsic_load_ubo:
1647 emit_intrinsic_load_ubo(ctx, intr, dst);
1648 break;
1649 case nir_intrinsic_load_ubo_ir3:
1650 emit_intrinsic_load_ubo_ldc(ctx, intr, dst);
1651 break;
1652 case nir_intrinsic_load_frag_coord:
1653 ir3_split_dest(b, dst, get_frag_coord(ctx, intr), 0, 4);
1654 break;
1655 case nir_intrinsic_load_sample_pos_from_id: {
1656 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1657 * but that doesn't seem necessary.
1658 */
1659 struct ir3_instruction *offset =
1660 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1661 offset->regs[0]->wrmask = 0x3;
1662 offset->cat5.type = TYPE_F32;
1663
1664 ir3_split_dest(b, dst, offset, 0, 2);
1665
1666 break;
1667 }
1668 case nir_intrinsic_load_size_ir3:
1669 if (!ctx->ij[IJ_PERSP_SIZE]) {
1670 ctx->ij[IJ_PERSP_SIZE] =
1671 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, 0x1);
1672 }
1673 dst[0] = ctx->ij[IJ_PERSP_SIZE];
1674 break;
1675 case nir_intrinsic_load_barycentric_centroid:
1676 case nir_intrinsic_load_barycentric_sample:
1677 case nir_intrinsic_load_barycentric_pixel:
1678 emit_intrinsic_barycentric(ctx, intr, dst);
1679 break;
1680 case nir_intrinsic_load_interpolated_input:
1681 idx = nir_intrinsic_base(intr);
1682 comp = nir_intrinsic_component(intr);
1683 src = ir3_get_src(ctx, &intr->src[0]);
1684 if (nir_src_is_const(intr->src[1])) {
1685 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1686 idx += nir_src_as_uint(intr->src[1]);
1687 for (int i = 0; i < dest_components; i++) {
1688 unsigned inloc = idx * 4 + i + comp;
1689 if (ctx->so->inputs[idx].bary &&
1690 !ctx->so->inputs[idx].use_ldlv) {
1691 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1692 } else {
1693 /* for non-varyings use the pre-setup input, since
1694 * that is easier than mapping things back to a
1695 * nir_variable to figure out what it is.
1696 */
1697 dst[i] = ctx->inputs[inloc];
1698 compile_assert(ctx, dst[i]);
1699 }
1700 }
1701 } else {
1702 ir3_context_error(ctx, "unhandled");
1703 }
1704 break;
1705 case nir_intrinsic_load_input:
1706 idx = nir_intrinsic_base(intr);
1707 comp = nir_intrinsic_component(intr);
1708 if (nir_src_is_const(intr->src[0])) {
1709 idx += nir_src_as_uint(intr->src[0]);
1710 for (int i = 0; i < dest_components; i++) {
1711 unsigned n = idx * 4 + i + comp;
1712 dst[i] = ctx->inputs[n];
1713 compile_assert(ctx, ctx->inputs[n]);
1714 }
1715 } else {
1716 src = ir3_get_src(ctx, &intr->src[0]);
1717 struct ir3_instruction *collect =
1718 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1719 struct ir3_instruction *addr = ir3_get_addr0(ctx, src[0], 4);
1720 for (int i = 0; i < dest_components; i++) {
1721 unsigned n = idx * 4 + i + comp;
1722 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1723 n, addr, collect);
1724 }
1725 }
1726 break;
1727 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1728 * pass and replaced by an ir3-specifc version that adds the
1729 * dword-offset in the last source.
1730 */
1731 case nir_intrinsic_load_ssbo_ir3:
1732 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1733 break;
1734 case nir_intrinsic_store_ssbo_ir3:
1735 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1736 !ctx->s->info.fs.early_fragment_tests)
1737 ctx->so->no_earlyz = true;
1738 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1739 break;
1740 case nir_intrinsic_get_buffer_size:
1741 emit_intrinsic_ssbo_size(ctx, intr, dst);
1742 break;
1743 case nir_intrinsic_ssbo_atomic_add_ir3:
1744 case nir_intrinsic_ssbo_atomic_imin_ir3:
1745 case nir_intrinsic_ssbo_atomic_umin_ir3:
1746 case nir_intrinsic_ssbo_atomic_imax_ir3:
1747 case nir_intrinsic_ssbo_atomic_umax_ir3:
1748 case nir_intrinsic_ssbo_atomic_and_ir3:
1749 case nir_intrinsic_ssbo_atomic_or_ir3:
1750 case nir_intrinsic_ssbo_atomic_xor_ir3:
1751 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1752 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1753 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1754 !ctx->s->info.fs.early_fragment_tests)
1755 ctx->so->no_earlyz = true;
1756 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1757 break;
1758 case nir_intrinsic_load_shared:
1759 emit_intrinsic_load_shared(ctx, intr, dst);
1760 break;
1761 case nir_intrinsic_store_shared:
1762 emit_intrinsic_store_shared(ctx, intr);
1763 break;
1764 case nir_intrinsic_shared_atomic_add:
1765 case nir_intrinsic_shared_atomic_imin:
1766 case nir_intrinsic_shared_atomic_umin:
1767 case nir_intrinsic_shared_atomic_imax:
1768 case nir_intrinsic_shared_atomic_umax:
1769 case nir_intrinsic_shared_atomic_and:
1770 case nir_intrinsic_shared_atomic_or:
1771 case nir_intrinsic_shared_atomic_xor:
1772 case nir_intrinsic_shared_atomic_exchange:
1773 case nir_intrinsic_shared_atomic_comp_swap:
1774 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1775 break;
1776 case nir_intrinsic_image_load:
1777 emit_intrinsic_load_image(ctx, intr, dst);
1778 break;
1779 case nir_intrinsic_bindless_image_load:
1780 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1781 * so using isam doesn't work.
1782 *
1783 * TODO: can we use isam if we fill out more fields?
1784 */
1785 ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
1786 break;
1787 case nir_intrinsic_image_store:
1788 case nir_intrinsic_bindless_image_store:
1789 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1790 !ctx->s->info.fs.early_fragment_tests)
1791 ctx->so->no_earlyz = true;
1792 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1793 break;
1794 case nir_intrinsic_image_size:
1795 case nir_intrinsic_bindless_image_size:
1796 ctx->funcs->emit_intrinsic_image_size(ctx, intr, dst);
1797 break;
1798 case nir_intrinsic_image_atomic_add:
1799 case nir_intrinsic_bindless_image_atomic_add:
1800 case nir_intrinsic_image_atomic_imin:
1801 case nir_intrinsic_bindless_image_atomic_imin:
1802 case nir_intrinsic_image_atomic_umin:
1803 case nir_intrinsic_bindless_image_atomic_umin:
1804 case nir_intrinsic_image_atomic_imax:
1805 case nir_intrinsic_bindless_image_atomic_imax:
1806 case nir_intrinsic_image_atomic_umax:
1807 case nir_intrinsic_bindless_image_atomic_umax:
1808 case nir_intrinsic_image_atomic_and:
1809 case nir_intrinsic_bindless_image_atomic_and:
1810 case nir_intrinsic_image_atomic_or:
1811 case nir_intrinsic_bindless_image_atomic_or:
1812 case nir_intrinsic_image_atomic_xor:
1813 case nir_intrinsic_bindless_image_atomic_xor:
1814 case nir_intrinsic_image_atomic_exchange:
1815 case nir_intrinsic_bindless_image_atomic_exchange:
1816 case nir_intrinsic_image_atomic_comp_swap:
1817 case nir_intrinsic_bindless_image_atomic_comp_swap:
1818 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1819 !ctx->s->info.fs.early_fragment_tests)
1820 ctx->so->no_earlyz = true;
1821 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1822 break;
1823 case nir_intrinsic_control_barrier:
1824 case nir_intrinsic_memory_barrier:
1825 case nir_intrinsic_group_memory_barrier:
1826 case nir_intrinsic_memory_barrier_buffer:
1827 case nir_intrinsic_memory_barrier_image:
1828 case nir_intrinsic_memory_barrier_shared:
1829 emit_intrinsic_barrier(ctx, intr);
1830 /* note that blk ptr no longer valid, make that obvious: */
1831 b = NULL;
1832 break;
1833 case nir_intrinsic_store_output:
1834 idx = nir_intrinsic_base(intr);
1835 comp = nir_intrinsic_component(intr);
1836 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1837 idx += nir_src_as_uint(intr->src[1]);
1838
1839 src = ir3_get_src(ctx, &intr->src[0]);
1840 for (int i = 0; i < nir_intrinsic_src_components(intr, 0); i++) {
1841 unsigned n = idx * 4 + i + comp;
1842 ctx->outputs[n] = src[i];
1843 }
1844 break;
1845 case nir_intrinsic_load_base_vertex:
1846 case nir_intrinsic_load_first_vertex:
1847 if (!ctx->basevertex) {
1848 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1849 }
1850 dst[0] = ctx->basevertex;
1851 break;
1852 case nir_intrinsic_load_draw_id:
1853 if (!ctx->draw_id) {
1854 ctx->draw_id = create_driver_param(ctx, IR3_DP_DRAWID);
1855 }
1856 dst[0] = ctx->draw_id;
1857 break;
1858 case nir_intrinsic_load_base_instance:
1859 if (!ctx->base_instance) {
1860 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1861 }
1862 dst[0] = ctx->base_instance;
1863 break;
1864 case nir_intrinsic_load_vertex_id_zero_base:
1865 case nir_intrinsic_load_vertex_id:
1866 if (!ctx->vertex_id) {
1867 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1868 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1869 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1870 }
1871 dst[0] = ctx->vertex_id;
1872 break;
1873 case nir_intrinsic_load_instance_id:
1874 if (!ctx->instance_id) {
1875 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1876 }
1877 dst[0] = ctx->instance_id;
1878 break;
1879 case nir_intrinsic_load_sample_id:
1880 ctx->so->per_samp = true;
1881 /* fall-thru */
1882 case nir_intrinsic_load_sample_id_no_per_sample:
1883 if (!ctx->samp_id) {
1884 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1885 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1886 }
1887 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1888 break;
1889 case nir_intrinsic_load_sample_mask_in:
1890 if (!ctx->samp_mask_in) {
1891 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1892 }
1893 dst[0] = ctx->samp_mask_in;
1894 break;
1895 case nir_intrinsic_load_user_clip_plane:
1896 idx = nir_intrinsic_ucp_id(intr);
1897 for (int i = 0; i < dest_components; i++) {
1898 unsigned n = idx * 4 + i;
1899 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1900 }
1901 break;
1902 case nir_intrinsic_load_front_face:
1903 if (!ctx->frag_face) {
1904 ctx->so->frag_face = true;
1905 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1906 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1907 }
1908 /* for fragface, we get -1 for back and 0 for front. However this is
1909 * the inverse of what nir expects (where ~0 is true).
1910 */
1911 dst[0] = ir3_CMPS_S(b,
1912 ctx->frag_face, 0,
1913 create_immed_typed(b, 0, TYPE_U16), 0);
1914 dst[0]->cat2.condition = IR3_COND_EQ;
1915 break;
1916 case nir_intrinsic_load_local_invocation_id:
1917 if (!ctx->local_invocation_id) {
1918 ctx->local_invocation_id =
1919 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1920 }
1921 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1922 break;
1923 case nir_intrinsic_load_work_group_id:
1924 if (!ctx->work_group_id) {
1925 ctx->work_group_id =
1926 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1927 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1928 }
1929 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1930 break;
1931 case nir_intrinsic_load_num_work_groups:
1932 for (int i = 0; i < dest_components; i++) {
1933 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1934 }
1935 break;
1936 case nir_intrinsic_load_local_group_size:
1937 for (int i = 0; i < dest_components; i++) {
1938 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1939 }
1940 break;
1941 case nir_intrinsic_discard_if:
1942 case nir_intrinsic_discard: {
1943 struct ir3_instruction *cond, *kill;
1944
1945 if (intr->intrinsic == nir_intrinsic_discard_if) {
1946 /* conditional discard: */
1947 src = ir3_get_src(ctx, &intr->src[0]);
1948 cond = src[0];
1949 } else {
1950 /* unconditional discard: */
1951 cond = create_immed(b, 1);
1952 }
1953
1954 /* NOTE: only cmps.*.* can write p0.x: */
1955 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1956 cond->cat2.condition = IR3_COND_NE;
1957
1958 /* condition always goes in predicate register: */
1959 cond->regs[0]->num = regid(REG_P0, 0);
1960 cond->regs[0]->flags &= ~IR3_REG_SSA;
1961
1962 kill = ir3_KILL(b, cond, 0);
1963 kill->regs[1]->num = regid(REG_P0, 0);
1964 array_insert(ctx->ir, ctx->ir->predicates, kill);
1965
1966 array_insert(b, b->keeps, kill);
1967 ctx->so->has_kill = true;
1968
1969 break;
1970 }
1971
1972 case nir_intrinsic_cond_end_ir3: {
1973 struct ir3_instruction *cond, *kill;
1974
1975 src = ir3_get_src(ctx, &intr->src[0]);
1976 cond = src[0];
1977
1978 /* NOTE: only cmps.*.* can write p0.x: */
1979 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1980 cond->cat2.condition = IR3_COND_NE;
1981
1982 /* condition always goes in predicate register: */
1983 cond->regs[0]->num = regid(REG_P0, 0);
1984
1985 kill = ir3_PREDT(b, cond, 0);
1986
1987 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1988 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1989
1990 array_insert(ctx->ir, ctx->ir->predicates, kill);
1991 array_insert(b, b->keeps, kill);
1992 break;
1993 }
1994
1995 case nir_intrinsic_load_shared_ir3:
1996 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1997 break;
1998 case nir_intrinsic_store_shared_ir3:
1999 emit_intrinsic_store_shared_ir3(ctx, intr);
2000 break;
2001 case nir_intrinsic_bindless_resource_ir3:
2002 dst[0] = ir3_get_src(ctx, &intr->src[0])[0];
2003 break;
2004 default:
2005 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
2006 nir_intrinsic_infos[intr->intrinsic].name);
2007 break;
2008 }
2009
2010 if (info->has_dest)
2011 ir3_put_dst(ctx, &intr->dest);
2012 }
2013
2014 static void
2015 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
2016 {
2017 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
2018 instr->def.num_components);
2019
2020 if (instr->def.bit_size == 16) {
2021 for (int i = 0; i < instr->def.num_components; i++)
2022 dst[i] = create_immed_typed(ctx->block,
2023 instr->value[i].u16,
2024 TYPE_U16);
2025 } else {
2026 for (int i = 0; i < instr->def.num_components; i++)
2027 dst[i] = create_immed_typed(ctx->block,
2028 instr->value[i].u32,
2029 TYPE_U32);
2030 }
2031
2032 }
2033
2034 static void
2035 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
2036 {
2037 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
2038 undef->def.num_components);
2039 type_t type = (undef->def.bit_size == 16) ? TYPE_U16 : TYPE_U32;
2040
2041 /* backend doesn't want undefined instructions, so just plug
2042 * in 0.0..
2043 */
2044 for (int i = 0; i < undef->def.num_components; i++)
2045 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
2046 }
2047
2048 /*
2049 * texture fetch/sample instructions:
2050 */
2051
2052 static type_t
2053 get_tex_dest_type(nir_tex_instr *tex)
2054 {
2055 type_t type;
2056
2057 switch (nir_alu_type_get_base_type(tex->dest_type)) {
2058 case nir_type_invalid:
2059 case nir_type_float:
2060 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_F16 : TYPE_F32;
2061 break;
2062 case nir_type_int:
2063 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_S16 : TYPE_S32;
2064 break;
2065 case nir_type_uint:
2066 case nir_type_bool:
2067 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_U16 : TYPE_U32;
2068 break;
2069 default:
2070 unreachable("bad dest_type");
2071 }
2072
2073 return type;
2074 }
2075
2076 static void
2077 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
2078 {
2079 unsigned coords = glsl_get_sampler_dim_coordinate_components(tex->sampler_dim);
2080 unsigned flags = 0;
2081
2082 /* note: would use tex->coord_components.. except txs.. also,
2083 * since array index goes after shadow ref, we don't want to
2084 * count it:
2085 */
2086 if (coords == 3)
2087 flags |= IR3_INSTR_3D;
2088
2089 if (tex->is_shadow && tex->op != nir_texop_lod)
2090 flags |= IR3_INSTR_S;
2091
2092 if (tex->is_array && tex->op != nir_texop_lod)
2093 flags |= IR3_INSTR_A;
2094
2095 *flagsp = flags;
2096 *coordsp = coords;
2097 }
2098
2099 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2100 * or immediate (in which case it will get lowered later to a non .s2en
2101 * version of the tex instruction which encode tex/samp as immediates:
2102 */
2103 static struct tex_src_info
2104 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
2105 {
2106 struct ir3_block *b = ctx->block;
2107 struct tex_src_info info = { 0 };
2108 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_handle);
2109 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_handle);
2110 struct ir3_instruction *texture, *sampler;
2111
2112 if (texture_idx >= 0 || sampler_idx >= 0) {
2113 /* Bindless case */
2114 info.flags |= IR3_INSTR_B;
2115
2116 /* Gather information required to determine which encoding to
2117 * choose as well as for prefetch.
2118 */
2119 nir_intrinsic_instr *bindless_tex = NULL;
2120 bool tex_const;
2121 if (texture_idx >= 0) {
2122 ctx->so->bindless_tex = true;
2123 bindless_tex = ir3_bindless_resource(tex->src[texture_idx].src);
2124 assert(bindless_tex);
2125 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
2126 tex_const = nir_src_is_const(bindless_tex->src[0]);
2127 if (tex_const)
2128 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
2129 } else {
2130 /* To simplify some of the logic below, assume the index is
2131 * constant 0 when it's not enabled.
2132 */
2133 tex_const = true;
2134 info.tex_idx = 0;
2135 }
2136 nir_intrinsic_instr *bindless_samp = NULL;
2137 bool samp_const;
2138 if (sampler_idx >= 0) {
2139 ctx->so->bindless_samp = true;
2140 bindless_samp = ir3_bindless_resource(tex->src[sampler_idx].src);
2141 assert(bindless_samp);
2142 info.samp_base = nir_intrinsic_desc_set(bindless_samp);
2143 samp_const = nir_src_is_const(bindless_samp->src[0]);
2144 if (samp_const)
2145 info.samp_idx = nir_src_as_uint(bindless_samp->src[0]);
2146 } else {
2147 samp_const = true;
2148 info.samp_idx = 0;
2149 }
2150
2151 /* Choose encoding. */
2152 if (tex_const && samp_const && info.tex_idx < 256 && info.samp_idx < 256) {
2153 if (info.tex_idx < 16 && info.samp_idx < 16 &&
2154 (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base)) {
2155 /* Everything fits within the instruction */
2156 info.base = info.tex_base;
2157 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
2158 } else {
2159 info.base = info.tex_base;
2160 info.a1_val = info.tex_idx << 3 | info.samp_base;
2161 info.combined_idx = info.samp_idx;
2162 info.flags |= IR3_INSTR_A1EN;
2163 }
2164 info.samp_tex = NULL;
2165 } else {
2166 info.flags |= IR3_INSTR_S2EN;
2167 /* In the indirect case, we only use a1.x to store the sampler
2168 * base if it differs from the texture base.
2169 */
2170 if (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base) {
2171 info.base = info.tex_base;
2172 } else {
2173 info.base = info.tex_base;
2174 info.a1_val = info.samp_base;
2175 info.flags |= IR3_INSTR_A1EN;
2176 }
2177
2178 /* Note: the indirect source is now a vec2 instead of hvec2, and
2179 * for some reason the texture and sampler are swapped.
2180 */
2181 struct ir3_instruction *texture, *sampler;
2182
2183 if (bindless_tex) {
2184 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2185 } else {
2186 texture = create_immed(b, 0);
2187 }
2188
2189 if (bindless_samp) {
2190 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2191 } else {
2192 sampler = create_immed(b, 0);
2193 }
2194 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2195 texture,
2196 sampler,
2197 }, 2);
2198 }
2199 } else {
2200 info.flags |= IR3_INSTR_S2EN;
2201 texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
2202 sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
2203 if (texture_idx >= 0) {
2204 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2205 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
2206 } else {
2207 /* TODO what to do for dynamic case? I guess we only need the
2208 * max index for astc srgb workaround so maybe not a problem
2209 * to worry about if we don't enable indirect samplers for
2210 * a4xx?
2211 */
2212 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
2213 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
2214 info.tex_idx = tex->texture_index;
2215 }
2216
2217 if (sampler_idx >= 0) {
2218 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2219 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
2220 } else {
2221 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
2222 info.samp_idx = tex->texture_index;
2223 }
2224
2225 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2226 sampler,
2227 texture,
2228 }, 2);
2229 }
2230
2231 return info;
2232 }
2233
2234 static void
2235 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
2236 {
2237 struct ir3_block *b = ctx->block;
2238 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
2239 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
2240 struct ir3_instruction *lod, *compare, *proj, *sample_index;
2241 struct tex_src_info info = { 0 };
2242 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
2243 unsigned i, coords, flags, ncomp;
2244 unsigned nsrc0 = 0, nsrc1 = 0;
2245 type_t type;
2246 opc_t opc = 0;
2247
2248 ncomp = nir_dest_num_components(tex->dest);
2249
2250 coord = off = ddx = ddy = NULL;
2251 lod = proj = compare = sample_index = NULL;
2252
2253 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
2254
2255 for (unsigned i = 0; i < tex->num_srcs; i++) {
2256 switch (tex->src[i].src_type) {
2257 case nir_tex_src_coord:
2258 coord = ir3_get_src(ctx, &tex->src[i].src);
2259 break;
2260 case nir_tex_src_bias:
2261 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2262 has_bias = true;
2263 break;
2264 case nir_tex_src_lod:
2265 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2266 has_lod = true;
2267 break;
2268 case nir_tex_src_comparator: /* shadow comparator */
2269 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
2270 break;
2271 case nir_tex_src_projector:
2272 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2273 has_proj = true;
2274 break;
2275 case nir_tex_src_offset:
2276 off = ir3_get_src(ctx, &tex->src[i].src);
2277 has_off = true;
2278 break;
2279 case nir_tex_src_ddx:
2280 ddx = ir3_get_src(ctx, &tex->src[i].src);
2281 break;
2282 case nir_tex_src_ddy:
2283 ddy = ir3_get_src(ctx, &tex->src[i].src);
2284 break;
2285 case nir_tex_src_ms_index:
2286 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2287 break;
2288 case nir_tex_src_texture_offset:
2289 case nir_tex_src_sampler_offset:
2290 case nir_tex_src_texture_handle:
2291 case nir_tex_src_sampler_handle:
2292 /* handled in get_tex_samp_src() */
2293 break;
2294 default:
2295 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2296 tex->src[i].src_type);
2297 return;
2298 }
2299 }
2300
2301 switch (tex->op) {
2302 case nir_texop_tex_prefetch:
2303 compile_assert(ctx, !has_bias);
2304 compile_assert(ctx, !has_lod);
2305 compile_assert(ctx, !compare);
2306 compile_assert(ctx, !has_proj);
2307 compile_assert(ctx, !has_off);
2308 compile_assert(ctx, !ddx);
2309 compile_assert(ctx, !ddy);
2310 compile_assert(ctx, !sample_index);
2311 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2312 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2313
2314 if (ctx->so->num_sampler_prefetch < ctx->prefetch_limit) {
2315 opc = OPC_META_TEX_PREFETCH;
2316 ctx->so->num_sampler_prefetch++;
2317 break;
2318 }
2319 /* fallthru */
2320 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2321 case nir_texop_txb: opc = OPC_SAMB; break;
2322 case nir_texop_txl: opc = OPC_SAML; break;
2323 case nir_texop_txd: opc = OPC_SAMGQ; break;
2324 case nir_texop_txf: opc = OPC_ISAML; break;
2325 case nir_texop_lod: opc = OPC_GETLOD; break;
2326 case nir_texop_tg4:
2327 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2328 * what blob does, seems gather is broken?), and a3xx did
2329 * not support it (but probably could also emulate).
2330 */
2331 switch (tex->component) {
2332 case 0: opc = OPC_GATHER4R; break;
2333 case 1: opc = OPC_GATHER4G; break;
2334 case 2: opc = OPC_GATHER4B; break;
2335 case 3: opc = OPC_GATHER4A; break;
2336 }
2337 break;
2338 case nir_texop_txf_ms_fb:
2339 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2340 default:
2341 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2342 return;
2343 }
2344
2345 tex_info(tex, &flags, &coords);
2346
2347 /*
2348 * lay out the first argument in the proper order:
2349 * - actual coordinates first
2350 * - shadow reference
2351 * - array index
2352 * - projection w
2353 * - starting at offset 4, dpdx.xy, dpdy.xy
2354 *
2355 * bias/lod go into the second arg
2356 */
2357
2358 /* insert tex coords: */
2359 for (i = 0; i < coords; i++)
2360 src0[i] = coord[i];
2361
2362 nsrc0 = i;
2363
2364 /* scale up integer coords for TXF based on the LOD */
2365 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2366 assert(has_lod);
2367 for (i = 0; i < coords; i++)
2368 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2369 }
2370
2371 if (coords == 1) {
2372 /* hw doesn't do 1d, so we treat it as 2d with
2373 * height of 1, and patch up the y coord.
2374 */
2375 if (is_isam(opc)) {
2376 src0[nsrc0++] = create_immed(b, 0);
2377 } else {
2378 src0[nsrc0++] = create_immed(b, fui(0.5));
2379 }
2380 }
2381
2382 if (tex->is_shadow && tex->op != nir_texop_lod)
2383 src0[nsrc0++] = compare;
2384
2385 if (tex->is_array && tex->op != nir_texop_lod) {
2386 struct ir3_instruction *idx = coord[coords];
2387
2388 /* the array coord for cube arrays needs 0.5 added to it */
2389 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2390 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2391
2392 src0[nsrc0++] = idx;
2393 }
2394
2395 if (has_proj) {
2396 src0[nsrc0++] = proj;
2397 flags |= IR3_INSTR_P;
2398 }
2399
2400 /* pad to 4, then ddx/ddy: */
2401 if (tex->op == nir_texop_txd) {
2402 while (nsrc0 < 4)
2403 src0[nsrc0++] = create_immed(b, fui(0.0));
2404 for (i = 0; i < coords; i++)
2405 src0[nsrc0++] = ddx[i];
2406 if (coords < 2)
2407 src0[nsrc0++] = create_immed(b, fui(0.0));
2408 for (i = 0; i < coords; i++)
2409 src0[nsrc0++] = ddy[i];
2410 if (coords < 2)
2411 src0[nsrc0++] = create_immed(b, fui(0.0));
2412 }
2413
2414 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2415 * with scaled x coord according to requested sample:
2416 */
2417 if (opc == OPC_ISAMM) {
2418 if (ctx->compiler->txf_ms_with_isaml) {
2419 /* the samples are laid out in x dimension as
2420 * 0 1 2 3
2421 * x_ms = (x << ms) + sample_index;
2422 */
2423 struct ir3_instruction *ms;
2424 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2425
2426 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2427 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2428
2429 opc = OPC_ISAML;
2430 } else {
2431 src0[nsrc0++] = sample_index;
2432 }
2433 }
2434
2435 /*
2436 * second argument (if applicable):
2437 * - offsets
2438 * - lod
2439 * - bias
2440 */
2441 if (has_off | has_lod | has_bias) {
2442 if (has_off) {
2443 unsigned off_coords = coords;
2444 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2445 off_coords--;
2446 for (i = 0; i < off_coords; i++)
2447 src1[nsrc1++] = off[i];
2448 if (off_coords < 2)
2449 src1[nsrc1++] = create_immed(b, fui(0.0));
2450 flags |= IR3_INSTR_O;
2451 }
2452
2453 if (has_lod | has_bias)
2454 src1[nsrc1++] = lod;
2455 }
2456
2457 type = get_tex_dest_type(tex);
2458
2459 if (opc == OPC_GETLOD)
2460 type = TYPE_S32;
2461
2462
2463 if (tex->op == nir_texop_txf_ms_fb) {
2464 /* only expect a single txf_ms_fb per shader: */
2465 compile_assert(ctx, !ctx->so->fb_read);
2466 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2467
2468 ctx->so->fb_read = true;
2469 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2470 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2471 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2472 }, 2);
2473 info.flags = IR3_INSTR_S2EN;
2474
2475 ctx->so->num_samp++;
2476 } else {
2477 info = get_tex_samp_tex_src(ctx, tex);
2478 }
2479
2480 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2481 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2482
2483 if (opc == OPC_META_TEX_PREFETCH) {
2484 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2485
2486 compile_assert(ctx, tex->src[idx].src.is_ssa);
2487
2488 sam = ir3_META_TEX_PREFETCH(b);
2489 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2490 __ssa_src(sam, get_barycentric(ctx, IJ_PERSP_PIXEL), 0);
2491 sam->prefetch.input_offset =
2492 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2493 /* make sure not to add irrelevant flags like S2EN */
2494 sam->flags = flags | (info.flags & IR3_INSTR_B);
2495 sam->prefetch.tex = info.tex_idx;
2496 sam->prefetch.samp = info.samp_idx;
2497 sam->prefetch.tex_base = info.tex_base;
2498 sam->prefetch.samp_base = info.samp_base;
2499 } else {
2500 info.flags |= flags;
2501 sam = emit_sam(ctx, opc, info, type, MASK(ncomp), col0, col1);
2502 }
2503
2504 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2505 assert(opc != OPC_META_TEX_PREFETCH);
2506
2507 /* only need first 3 components: */
2508 sam->regs[0]->wrmask = 0x7;
2509 ir3_split_dest(b, dst, sam, 0, 3);
2510
2511 /* we need to sample the alpha separately with a non-ASTC
2512 * texture state:
2513 */
2514 sam = ir3_SAM(b, opc, type, 0b1000, flags | info.flags,
2515 info.samp_tex, col0, col1);
2516
2517 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2518
2519 /* fixup .w component: */
2520 ir3_split_dest(b, &dst[3], sam, 3, 1);
2521 } else {
2522 /* normal (non-workaround) case: */
2523 ir3_split_dest(b, dst, sam, 0, ncomp);
2524 }
2525
2526 /* GETLOD returns results in 4.8 fixed point */
2527 if (opc == OPC_GETLOD) {
2528 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2529
2530 compile_assert(ctx, tex->dest_type == nir_type_float);
2531 for (i = 0; i < 2; i++) {
2532 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2533 factor, 0);
2534 }
2535 }
2536
2537 ir3_put_dst(ctx, &tex->dest);
2538 }
2539
2540 static void
2541 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2542 {
2543 struct ir3_block *b = ctx->block;
2544 struct ir3_instruction **dst, *sam;
2545 type_t dst_type = get_tex_dest_type(tex);
2546 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2547
2548 dst = ir3_get_dst(ctx, &tex->dest, 1);
2549
2550 sam = emit_sam(ctx, OPC_GETINFO, info, dst_type, 1 << idx, NULL, NULL);
2551
2552 /* even though there is only one component, since it ends
2553 * up in .y/.z/.w rather than .x, we need a split_dest()
2554 */
2555 ir3_split_dest(b, dst, sam, idx, 1);
2556
2557 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2558 * the value in TEX_CONST_0 is zero-based.
2559 */
2560 if (ctx->compiler->levels_add_one)
2561 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2562
2563 ir3_put_dst(ctx, &tex->dest);
2564 }
2565
2566 static void
2567 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2568 {
2569 struct ir3_block *b = ctx->block;
2570 struct ir3_instruction **dst, *sam;
2571 struct ir3_instruction *lod;
2572 unsigned flags, coords;
2573 type_t dst_type = get_tex_dest_type(tex);
2574 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2575
2576 tex_info(tex, &flags, &coords);
2577 info.flags |= flags;
2578
2579 /* Actually we want the number of dimensions, not coordinates. This
2580 * distinction only matters for cubes.
2581 */
2582 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2583 coords = 2;
2584
2585 dst = ir3_get_dst(ctx, &tex->dest, 4);
2586
2587 int lod_idx = nir_tex_instr_src_index(tex, nir_tex_src_lod);
2588 compile_assert(ctx, lod_idx >= 0);
2589
2590 lod = ir3_get_src(ctx, &tex->src[lod_idx].src)[0];
2591
2592 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
2593 ir3_split_dest(b, dst, sam, 0, 4);
2594
2595 /* Array size actually ends up in .w rather than .z. This doesn't
2596 * matter for miplevel 0, but for higher mips the value in z is
2597 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2598 * returned, which means that we have to add 1 to it for arrays.
2599 */
2600 if (tex->is_array) {
2601 if (ctx->compiler->levels_add_one) {
2602 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2603 } else {
2604 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2605 }
2606 }
2607
2608 ir3_put_dst(ctx, &tex->dest);
2609 }
2610
2611 static void
2612 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2613 {
2614 switch (jump->type) {
2615 case nir_jump_break:
2616 case nir_jump_continue:
2617 case nir_jump_return:
2618 /* I *think* we can simply just ignore this, and use the
2619 * successor block link to figure out where we need to
2620 * jump to for break/continue
2621 */
2622 break;
2623 default:
2624 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2625 break;
2626 }
2627 }
2628
2629 static void
2630 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2631 {
2632 switch (instr->type) {
2633 case nir_instr_type_alu:
2634 emit_alu(ctx, nir_instr_as_alu(instr));
2635 break;
2636 case nir_instr_type_deref:
2637 /* ignored, handled as part of the intrinsic they are src to */
2638 break;
2639 case nir_instr_type_intrinsic:
2640 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2641 break;
2642 case nir_instr_type_load_const:
2643 emit_load_const(ctx, nir_instr_as_load_const(instr));
2644 break;
2645 case nir_instr_type_ssa_undef:
2646 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2647 break;
2648 case nir_instr_type_tex: {
2649 nir_tex_instr *tex = nir_instr_as_tex(instr);
2650 /* couple tex instructions get special-cased:
2651 */
2652 switch (tex->op) {
2653 case nir_texop_txs:
2654 emit_tex_txs(ctx, tex);
2655 break;
2656 case nir_texop_query_levels:
2657 emit_tex_info(ctx, tex, 2);
2658 break;
2659 case nir_texop_texture_samples:
2660 emit_tex_info(ctx, tex, 3);
2661 break;
2662 default:
2663 emit_tex(ctx, tex);
2664 break;
2665 }
2666 break;
2667 }
2668 case nir_instr_type_jump:
2669 emit_jump(ctx, nir_instr_as_jump(instr));
2670 break;
2671 case nir_instr_type_phi:
2672 /* we have converted phi webs to regs in NIR by now */
2673 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2674 break;
2675 case nir_instr_type_call:
2676 case nir_instr_type_parallel_copy:
2677 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2678 break;
2679 }
2680 }
2681
2682 static struct ir3_block *
2683 get_block(struct ir3_context *ctx, const nir_block *nblock)
2684 {
2685 struct ir3_block *block;
2686 struct hash_entry *hentry;
2687
2688 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2689 if (hentry)
2690 return hentry->data;
2691
2692 block = ir3_block_create(ctx->ir);
2693 block->nblock = nblock;
2694 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2695
2696 set_foreach(nblock->predecessors, sentry) {
2697 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2698 }
2699
2700 return block;
2701 }
2702
2703 static void
2704 emit_block(struct ir3_context *ctx, nir_block *nblock)
2705 {
2706 struct ir3_block *block = get_block(ctx, nblock);
2707
2708 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2709 if (nblock->successors[i]) {
2710 block->successors[i] =
2711 get_block(ctx, nblock->successors[i]);
2712 }
2713 }
2714
2715 ctx->block = block;
2716 list_addtail(&block->node, &ctx->ir->block_list);
2717
2718 /* re-emit addr register in each block if needed: */
2719 for (int i = 0; i < ARRAY_SIZE(ctx->addr0_ht); i++) {
2720 _mesa_hash_table_destroy(ctx->addr0_ht[i], NULL);
2721 ctx->addr0_ht[i] = NULL;
2722 }
2723
2724 _mesa_hash_table_u64_destroy(ctx->addr1_ht, NULL);
2725 ctx->addr1_ht = NULL;
2726
2727 nir_foreach_instr (instr, nblock) {
2728 ctx->cur_instr = instr;
2729 emit_instr(ctx, instr);
2730 ctx->cur_instr = NULL;
2731 if (ctx->error)
2732 return;
2733 }
2734
2735 _mesa_hash_table_clear(ctx->sel_cond_conversions, NULL);
2736 }
2737
2738 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2739
2740 static void
2741 emit_if(struct ir3_context *ctx, nir_if *nif)
2742 {
2743 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2744
2745 ctx->block->condition = ir3_get_predicate(ctx, condition);
2746
2747 emit_cf_list(ctx, &nif->then_list);
2748 emit_cf_list(ctx, &nif->else_list);
2749 }
2750
2751 static void
2752 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2753 {
2754 emit_cf_list(ctx, &nloop->body);
2755 ctx->so->loops++;
2756 }
2757
2758 static void
2759 stack_push(struct ir3_context *ctx)
2760 {
2761 ctx->stack++;
2762 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2763 }
2764
2765 static void
2766 stack_pop(struct ir3_context *ctx)
2767 {
2768 compile_assert(ctx, ctx->stack > 0);
2769 ctx->stack--;
2770 }
2771
2772 static void
2773 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2774 {
2775 foreach_list_typed (nir_cf_node, node, node, list) {
2776 switch (node->type) {
2777 case nir_cf_node_block:
2778 emit_block(ctx, nir_cf_node_as_block(node));
2779 break;
2780 case nir_cf_node_if:
2781 stack_push(ctx);
2782 emit_if(ctx, nir_cf_node_as_if(node));
2783 stack_pop(ctx);
2784 break;
2785 case nir_cf_node_loop:
2786 stack_push(ctx);
2787 emit_loop(ctx, nir_cf_node_as_loop(node));
2788 stack_pop(ctx);
2789 break;
2790 case nir_cf_node_function:
2791 ir3_context_error(ctx, "TODO\n");
2792 break;
2793 }
2794 }
2795 }
2796
2797 /* emit stream-out code. At this point, the current block is the original
2798 * (nir) end block, and nir ensures that all flow control paths terminate
2799 * into the end block. We re-purpose the original end block to generate
2800 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2801 * block holding stream-out write instructions, followed by the new end
2802 * block:
2803 *
2804 * blockOrigEnd {
2805 * p0.x = (vtxcnt < maxvtxcnt)
2806 * // succs: blockStreamOut, blockNewEnd
2807 * }
2808 * blockStreamOut {
2809 * // preds: blockOrigEnd
2810 * ... stream-out instructions ...
2811 * // succs: blockNewEnd
2812 * }
2813 * blockNewEnd {
2814 * // preds: blockOrigEnd, blockStreamOut
2815 * }
2816 */
2817 static void
2818 emit_stream_out(struct ir3_context *ctx)
2819 {
2820 struct ir3 *ir = ctx->ir;
2821 struct ir3_stream_output_info *strmout =
2822 &ctx->so->shader->stream_output;
2823 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2824 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2825 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2826
2827 /* create vtxcnt input in input block at top of shader,
2828 * so that it is seen as live over the entire duration
2829 * of the shader:
2830 */
2831 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2832 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2833
2834 /* at this point, we are at the original 'end' block,
2835 * re-purpose this block to stream-out condition, then
2836 * append stream-out block and new-end block
2837 */
2838 orig_end_block = ctx->block;
2839
2840 // maybe w/ store_global intrinsic, we could do this
2841 // stuff in nir->nir pass
2842
2843 stream_out_block = ir3_block_create(ir);
2844 list_addtail(&stream_out_block->node, &ir->block_list);
2845
2846 new_end_block = ir3_block_create(ir);
2847 list_addtail(&new_end_block->node, &ir->block_list);
2848
2849 orig_end_block->successors[0] = stream_out_block;
2850 orig_end_block->successors[1] = new_end_block;
2851
2852 stream_out_block->successors[0] = new_end_block;
2853 _mesa_set_add(stream_out_block->predecessors, orig_end_block);
2854
2855 _mesa_set_add(new_end_block->predecessors, orig_end_block);
2856 _mesa_set_add(new_end_block->predecessors, stream_out_block);
2857
2858 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2859 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2860 cond->regs[0]->num = regid(REG_P0, 0);
2861 cond->regs[0]->flags &= ~IR3_REG_SSA;
2862 cond->cat2.condition = IR3_COND_LT;
2863
2864 /* condition goes on previous block to the conditional,
2865 * since it is used to pick which of the two successor
2866 * paths to take:
2867 */
2868 orig_end_block->condition = cond;
2869
2870 /* switch to stream_out_block to generate the stream-out
2871 * instructions:
2872 */
2873 ctx->block = stream_out_block;
2874
2875 /* Calculate base addresses based on vtxcnt. Instructions
2876 * generated for bases not used in following loop will be
2877 * stripped out in the backend.
2878 */
2879 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2880 const struct ir3_const_state *const_state =
2881 ir3_const_state(ctx->so);
2882 unsigned stride = strmout->stride[i];
2883 struct ir3_instruction *base, *off;
2884
2885 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2886
2887 /* 24-bit should be enough: */
2888 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2889 create_immed(ctx->block, stride * 4), 0);
2890
2891 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2892 }
2893
2894 /* Generate the per-output store instructions: */
2895 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2896 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2897 unsigned c = j + strmout->output[i].start_component;
2898 struct ir3_instruction *base, *out, *stg;
2899
2900 base = bases[strmout->output[i].output_buffer];
2901 out = ctx->outputs[regid(strmout->output[i].register_index, c)];
2902
2903 stg = ir3_STG(ctx->block, base, 0, out, 0,
2904 create_immed(ctx->block, 1), 0);
2905 stg->cat6.type = TYPE_U32;
2906 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2907
2908 array_insert(ctx->block, ctx->block->keeps, stg);
2909 }
2910 }
2911
2912 /* and finally switch to the new_end_block: */
2913 ctx->block = new_end_block;
2914 }
2915
2916 static void
2917 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2918 {
2919 nir_metadata_require(impl, nir_metadata_block_index);
2920
2921 compile_assert(ctx, ctx->stack == 0);
2922
2923 emit_cf_list(ctx, &impl->body);
2924 emit_block(ctx, impl->end_block);
2925
2926 compile_assert(ctx, ctx->stack == 0);
2927
2928 /* at this point, we should have a single empty block,
2929 * into which we emit the 'end' instruction.
2930 */
2931 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2932
2933 /* If stream-out (aka transform-feedback) enabled, emit the
2934 * stream-out instructions, followed by a new empty block (into
2935 * which the 'end' instruction lands).
2936 *
2937 * NOTE: it is done in this order, rather than inserting before
2938 * we emit end_block, because NIR guarantees that all blocks
2939 * flow into end_block, and that end_block has no successors.
2940 * So by re-purposing end_block as the first block of stream-
2941 * out, we guarantee that all exit paths flow into the stream-
2942 * out instructions.
2943 */
2944 if ((ctx->compiler->gpu_id < 500) &&
2945 (ctx->so->shader->stream_output.num_outputs > 0) &&
2946 !ctx->so->binning_pass) {
2947 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2948 emit_stream_out(ctx);
2949 }
2950
2951 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2952 * NOP and has an epilogue that writes the VS outputs to local storage, to
2953 * be read by the HS. Then it resets execution mask (chmask) and chains
2954 * to the next shader (chsh).
2955 */
2956 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2957 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2958 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2959 struct ir3_instruction *chmask =
2960 ir3_CHMASK(ctx->block);
2961 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2962 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2963
2964 struct ir3_instruction *chsh =
2965 ir3_CHSH(ctx->block);
2966 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2967 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2968 } else {
2969 ir3_END(ctx->block);
2970 }
2971 }
2972
2973 static void
2974 setup_input(struct ir3_context *ctx, nir_variable *in)
2975 {
2976 struct ir3_shader_variant *so = ctx->so;
2977 unsigned ncomp = glsl_get_components(in->type);
2978 unsigned n = in->data.driver_location;
2979 unsigned frac = in->data.location_frac;
2980 unsigned slot = in->data.location;
2981
2982 /* Inputs are loaded using ldlw or ldg for these stages. */
2983 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2984 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2985 ctx->so->type == MESA_SHADER_GEOMETRY)
2986 return;
2987
2988 /* skip unread inputs, we could end up with (for example), unsplit
2989 * matrix/etc inputs in the case they are not read, so just silently
2990 * skip these.
2991 */
2992 if (ncomp > 4)
2993 return;
2994
2995 so->inputs[n].slot = slot;
2996 so->inputs[n].compmask |= (1 << (ncomp + frac)) - 1;
2997 so->inputs_count = MAX2(so->inputs_count, n + 1);
2998 so->inputs[n].interpolate = in->data.interpolation;
2999
3000 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3001
3002 /* if any varyings have 'sample' qualifer, that triggers us
3003 * to run in per-sample mode:
3004 */
3005 so->per_samp |= in->data.sample;
3006
3007 for (int i = 0; i < ncomp; i++) {
3008 struct ir3_instruction *instr = NULL;
3009 unsigned idx = (n * 4) + i + frac;
3010
3011 if (slot == VARYING_SLOT_POS) {
3012 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
3013 } else {
3014 /* detect the special case for front/back colors where
3015 * we need to do flat vs smooth shading depending on
3016 * rast state:
3017 */
3018 if (in->data.interpolation == INTERP_MODE_NONE) {
3019 switch (slot) {
3020 case VARYING_SLOT_COL0:
3021 case VARYING_SLOT_COL1:
3022 case VARYING_SLOT_BFC0:
3023 case VARYING_SLOT_BFC1:
3024 so->inputs[n].rasterflat = true;
3025 break;
3026 default:
3027 break;
3028 }
3029 }
3030
3031 if (ctx->compiler->flat_bypass) {
3032 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
3033 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
3034 so->inputs[n].use_ldlv = true;
3035 }
3036
3037 so->inputs[n].bary = true;
3038
3039 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
3040 }
3041
3042 compile_assert(ctx, idx < ctx->ninputs);
3043
3044 ctx->inputs[idx] = instr;
3045 }
3046 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
3047 struct ir3_instruction *input = NULL;
3048 struct ir3_instruction *components[4];
3049 /* input as setup as frac=0 with "ncomp + frac" components,
3050 * this avoids getting a sparse writemask
3051 */
3052 unsigned mask = (1 << (ncomp + frac)) - 1;
3053
3054 foreach_input (in, ctx->ir) {
3055 if (in->input.inidx == n) {
3056 input = in;
3057 break;
3058 }
3059 }
3060
3061 if (!input) {
3062 input = create_input(ctx, mask);
3063 input->input.inidx = n;
3064 } else {
3065 /* For aliased inputs, just append to the wrmask.. ie. if we
3066 * first see a vec2 index at slot N, and then later a vec4,
3067 * the wrmask of the resulting overlapped vec2 and vec4 is 0xf
3068 *
3069 * If the new input that aliases a previously processed input
3070 * sets no new bits, then just bail as there is nothing to see
3071 * here.
3072 */
3073 if (!(mask & ~input->regs[0]->wrmask))
3074 return;
3075 input->regs[0]->wrmask |= mask;
3076 }
3077
3078 ir3_split_dest(ctx->block, components, input, 0, ncomp + frac);
3079
3080 for (int i = 0; i < ncomp + frac; i++) {
3081 unsigned idx = (n * 4) + i;
3082 compile_assert(ctx, idx < ctx->ninputs);
3083
3084 /* With aliased inputs, since we add to the wrmask above, we
3085 * can end up with stale meta:split instructions in the inputs
3086 * table. This is basically harmless, since eventually they
3087 * will get swept away by DCE, but the mismatch wrmask (since
3088 * they would be using the previous wrmask before we OR'd in
3089 * more bits) angers ir3_validate. So just preemptively clean
3090 * them up. See:
3091 *
3092 * dEQP-GLES2.functional.attribute_location.bind_aliasing.cond_vec2
3093 *
3094 * Note however that split_dest() will return the src if it is
3095 * scalar, so the previous ctx->inputs[idx] could be the input
3096 * itself (which we don't want to remove)
3097 */
3098 if (ctx->inputs[idx] && (ctx->inputs[idx] != input)) {
3099 list_del(&ctx->inputs[idx]->node);
3100 }
3101
3102 ctx->inputs[idx] = components[i];
3103 }
3104 } else {
3105 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3106 }
3107
3108 /* note: this can be wrong for sparse vertex inputs, this happens with
3109 * vulkan, only a3xx/a4xx use this value for VS, so it shouldn't matter
3110 */
3111 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
3112 so->total_in += ncomp;
3113 }
3114 }
3115
3116 /* Initially we assign non-packed inloc's for varyings, as we don't really
3117 * know up-front which components will be unused. After all the compilation
3118 * stages we scan the shader to see which components are actually used, and
3119 * re-pack the inlocs to eliminate unneeded varyings.
3120 */
3121 static void
3122 pack_inlocs(struct ir3_context *ctx)
3123 {
3124 struct ir3_shader_variant *so = ctx->so;
3125 uint8_t used_components[so->inputs_count];
3126
3127 memset(used_components, 0, sizeof(used_components));
3128
3129 /*
3130 * First Step: scan shader to find which bary.f/ldlv remain:
3131 */
3132
3133 foreach_block (block, &ctx->ir->block_list) {
3134 foreach_instr (instr, &block->instr_list) {
3135 if (is_input(instr)) {
3136 unsigned inloc = instr->regs[1]->iim_val;
3137 unsigned i = inloc / 4;
3138 unsigned j = inloc % 4;
3139
3140 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
3141 compile_assert(ctx, i < so->inputs_count);
3142
3143 used_components[i] |= 1 << j;
3144 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3145 for (int n = 0; n < 2; n++) {
3146 unsigned inloc = instr->prefetch.input_offset + n;
3147 unsigned i = inloc / 4;
3148 unsigned j = inloc % 4;
3149
3150 compile_assert(ctx, i < so->inputs_count);
3151
3152 used_components[i] |= 1 << j;
3153 }
3154 }
3155 }
3156 }
3157
3158 /*
3159 * Second Step: reassign varying inloc/slots:
3160 */
3161
3162 unsigned actual_in = 0;
3163 unsigned inloc = 0;
3164
3165 for (unsigned i = 0; i < so->inputs_count; i++) {
3166 unsigned compmask = 0, maxcomp = 0;
3167
3168 so->inputs[i].inloc = inloc;
3169 so->inputs[i].bary = false;
3170
3171 for (unsigned j = 0; j < 4; j++) {
3172 if (!(used_components[i] & (1 << j)))
3173 continue;
3174
3175 compmask |= (1 << j);
3176 actual_in++;
3177 maxcomp = j + 1;
3178
3179 /* at this point, since used_components[i] mask is only
3180 * considering varyings (ie. not sysvals) we know this
3181 * is a varying:
3182 */
3183 so->inputs[i].bary = true;
3184 }
3185
3186 if (so->inputs[i].bary) {
3187 so->varying_in++;
3188 so->inputs[i].compmask = (1 << maxcomp) - 1;
3189 inloc += maxcomp;
3190 }
3191 }
3192
3193 /*
3194 * Third Step: reassign packed inloc's:
3195 */
3196
3197 foreach_block (block, &ctx->ir->block_list) {
3198 foreach_instr (instr, &block->instr_list) {
3199 if (is_input(instr)) {
3200 unsigned inloc = instr->regs[1]->iim_val;
3201 unsigned i = inloc / 4;
3202 unsigned j = inloc % 4;
3203
3204 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
3205 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3206 unsigned i = instr->prefetch.input_offset / 4;
3207 unsigned j = instr->prefetch.input_offset % 4;
3208 instr->prefetch.input_offset = so->inputs[i].inloc + j;
3209 }
3210 }
3211 }
3212 }
3213
3214 static void
3215 setup_output(struct ir3_context *ctx, nir_variable *out)
3216 {
3217 struct ir3_shader_variant *so = ctx->so;
3218 unsigned slots = glsl_count_vec4_slots(out->type, false, false);
3219 unsigned ncomp = glsl_get_components(glsl_without_array(out->type));
3220 unsigned n = out->data.driver_location;
3221 unsigned frac = out->data.location_frac;
3222 unsigned slot = out->data.location;
3223
3224 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3225 switch (slot) {
3226 case FRAG_RESULT_DEPTH:
3227 so->writes_pos = true;
3228 break;
3229 case FRAG_RESULT_COLOR:
3230 so->color0_mrt = 1;
3231 break;
3232 case FRAG_RESULT_SAMPLE_MASK:
3233 so->writes_smask = true;
3234 break;
3235 case FRAG_RESULT_STENCIL:
3236 so->writes_stencilref = true;
3237 break;
3238 default:
3239 slot += out->data.index; /* For dual-src blend */
3240 if (slot >= FRAG_RESULT_DATA0)
3241 break;
3242 ir3_context_error(ctx, "unknown FS output name: %s\n",
3243 gl_frag_result_name(slot));
3244 }
3245 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
3246 ctx->so->type == MESA_SHADER_TESS_EVAL ||
3247 ctx->so->type == MESA_SHADER_GEOMETRY) {
3248 switch (slot) {
3249 case VARYING_SLOT_POS:
3250 so->writes_pos = true;
3251 break;
3252 case VARYING_SLOT_PSIZ:
3253 so->writes_psize = true;
3254 break;
3255 case VARYING_SLOT_PRIMITIVE_ID:
3256 case VARYING_SLOT_LAYER:
3257 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
3258 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
3259 /* fall through */
3260 case VARYING_SLOT_COL0:
3261 case VARYING_SLOT_COL1:
3262 case VARYING_SLOT_BFC0:
3263 case VARYING_SLOT_BFC1:
3264 case VARYING_SLOT_FOGC:
3265 case VARYING_SLOT_CLIP_DIST0:
3266 case VARYING_SLOT_CLIP_DIST1:
3267 case VARYING_SLOT_CLIP_VERTEX:
3268 break;
3269 default:
3270 if (slot >= VARYING_SLOT_VAR0)
3271 break;
3272 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
3273 break;
3274 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
3275 _mesa_shader_stage_to_string(ctx->so->type),
3276 gl_varying_slot_name(slot));
3277 }
3278 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
3279 /* output lowered to buffer writes. */
3280 return;
3281 } else {
3282 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3283 }
3284
3285
3286 so->outputs_count = out->data.driver_location + slots;
3287 compile_assert(ctx, so->outputs_count < ARRAY_SIZE(so->outputs));
3288
3289 for (int i = 0; i < slots; i++) {
3290 int slot_base = n + i;
3291 so->outputs[slot_base].slot = slot + i;
3292
3293 for (int i = 0; i < ncomp; i++) {
3294 unsigned idx = (slot_base * 4) + i + frac;
3295 compile_assert(ctx, idx < ctx->noutputs);
3296 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3297 }
3298
3299 /* if varying packing doesn't happen, we could end up in a situation
3300 * with "holes" in the output, and since the per-generation code that
3301 * sets up varying linkage registers doesn't expect to have more than
3302 * one varying per vec4 slot, pad the holes.
3303 *
3304 * Note that this should probably generate a performance warning of
3305 * some sort.
3306 */
3307 for (int i = 0; i < frac; i++) {
3308 unsigned idx = (slot_base * 4) + i;
3309 if (!ctx->outputs[idx]) {
3310 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3311 }
3312 }
3313 }
3314 }
3315
3316 static void
3317 emit_instructions(struct ir3_context *ctx)
3318 {
3319 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
3320
3321 ctx->ninputs = ctx->s->num_inputs * 4;
3322 ctx->noutputs = ctx->s->num_outputs * 4;
3323 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3324 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3325
3326 ctx->ir = ir3_create(ctx->compiler, ctx->so);
3327
3328 /* Create inputs in first block: */
3329 ctx->block = get_block(ctx, nir_start_block(fxn));
3330 ctx->in_block = ctx->block;
3331
3332 /* for fragment shader, the vcoord input register is used as the
3333 * base for bary.f varying fetch instrs:
3334 *
3335 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3336 * until emit_intrinsic when we know they are actually needed.
3337 * For now, we defer creating ctx->ij_centroid, etc, since we
3338 * only need ij_pixel for "old style" varying inputs (ie.
3339 * tgsi_to_nir)
3340 */
3341 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3342 ctx->ij[IJ_PERSP_PIXEL] = create_input(ctx, 0x3);
3343 }
3344
3345 /* Setup inputs: */
3346 nir_foreach_shader_in_variable (var, ctx->s) {
3347 setup_input(ctx, var);
3348 }
3349
3350 /* Defer add_sysval_input() stuff until after setup_inputs(),
3351 * because sysvals need to be appended after varyings:
3352 */
3353 if (ctx->ij[IJ_PERSP_PIXEL]) {
3354 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL,
3355 0x3, ctx->ij[IJ_PERSP_PIXEL]);
3356 }
3357
3358
3359 /* Tesselation shaders always need primitive ID for indexing the
3360 * BO. Geometry shaders don't always need it but when they do it has be
3361 * delivered and unclobbered in the VS. To make things easy, we always
3362 * make room for it in VS/DS.
3363 */
3364 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3365 bool has_gs = ctx->so->key.has_gs;
3366 switch (ctx->so->type) {
3367 case MESA_SHADER_VERTEX:
3368 if (has_tess) {
3369 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3370 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3371 } else if (has_gs) {
3372 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3373 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3374 }
3375 break;
3376 case MESA_SHADER_TESS_CTRL:
3377 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3378 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3379 break;
3380 case MESA_SHADER_TESS_EVAL:
3381 if (has_gs)
3382 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3383 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3384 break;
3385 case MESA_SHADER_GEOMETRY:
3386 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3387 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3388 break;
3389 default:
3390 break;
3391 }
3392
3393 /* Setup outputs: */
3394 nir_foreach_shader_out_variable (var, ctx->s) {
3395 setup_output(ctx, var);
3396 }
3397
3398 /* Find # of samplers. Just assume that we'll be reading from images.. if
3399 * it is write-only we don't have to count it, but after lowering derefs
3400 * is too late to compact indices for that.
3401 */
3402 ctx->so->num_samp = util_last_bit(ctx->s->info.textures_used) + ctx->s->info.num_images;
3403
3404 /* NOTE: need to do something more clever when we support >1 fxn */
3405 nir_foreach_register (reg, &fxn->registers) {
3406 ir3_declare_array(ctx, reg);
3407 }
3408 /* And emit the body: */
3409 ctx->impl = fxn;
3410 emit_function(ctx, fxn);
3411 }
3412
3413 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3414 * need to assign the tex state indexes for these after we know the
3415 * max tex index.
3416 */
3417 static void
3418 fixup_astc_srgb(struct ir3_context *ctx)
3419 {
3420 struct ir3_shader_variant *so = ctx->so;
3421 /* indexed by original tex idx, value is newly assigned alpha sampler
3422 * state tex idx. Zero is invalid since there is at least one sampler
3423 * if we get here.
3424 */
3425 unsigned alt_tex_state[16] = {0};
3426 unsigned tex_idx = ctx->max_texture_index + 1;
3427 unsigned idx = 0;
3428
3429 so->astc_srgb.base = tex_idx;
3430
3431 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3432 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3433
3434 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3435
3436 if (alt_tex_state[sam->cat5.tex] == 0) {
3437 /* assign new alternate/alpha tex state slot: */
3438 alt_tex_state[sam->cat5.tex] = tex_idx++;
3439 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3440 so->astc_srgb.count++;
3441 }
3442
3443 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3444 }
3445 }
3446
3447 static void
3448 fixup_binning_pass(struct ir3_context *ctx)
3449 {
3450 struct ir3_shader_variant *so = ctx->so;
3451 struct ir3 *ir = ctx->ir;
3452 unsigned i, j;
3453
3454 /* first pass, remove unused outputs from the IR level outputs: */
3455 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3456 struct ir3_instruction *out = ir->outputs[i];
3457 assert(out->opc == OPC_META_COLLECT);
3458 unsigned outidx = out->collect.outidx;
3459 unsigned slot = so->outputs[outidx].slot;
3460
3461 /* throw away everything but first position/psize */
3462 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3463 ir->outputs[j] = ir->outputs[i];
3464 j++;
3465 }
3466 }
3467 ir->outputs_count = j;
3468
3469 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3470 * table:
3471 */
3472 for (i = 0, j = 0; i < so->outputs_count; i++) {
3473 unsigned slot = so->outputs[i].slot;
3474
3475 /* throw away everything but first position/psize */
3476 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3477 so->outputs[j] = so->outputs[i];
3478
3479 /* fixup outidx to point to new output table entry: */
3480 foreach_output (out, ir) {
3481 if (out->collect.outidx == i) {
3482 out->collect.outidx = j;
3483 break;
3484 }
3485 }
3486
3487 j++;
3488 }
3489 }
3490 so->outputs_count = j;
3491 }
3492
3493 static void
3494 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3495 {
3496 unsigned idx = 0;
3497
3498 /* Collect sampling instructions eligible for pre-dispatch. */
3499 foreach_block (block, &ir->block_list) {
3500 foreach_instr_safe (instr, &block->instr_list) {
3501 if (instr->opc == OPC_META_TEX_PREFETCH) {
3502 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3503 struct ir3_sampler_prefetch *fetch =
3504 &ctx->so->sampler_prefetch[idx];
3505 idx++;
3506
3507 if (instr->flags & IR3_INSTR_B) {
3508 fetch->cmd = IR3_SAMPLER_BINDLESS_PREFETCH_CMD;
3509 /* In bindless mode, the index is actually the base */
3510 fetch->tex_id = instr->prefetch.tex_base;
3511 fetch->samp_id = instr->prefetch.samp_base;
3512 fetch->tex_bindless_id = instr->prefetch.tex;
3513 fetch->samp_bindless_id = instr->prefetch.samp;
3514 } else {
3515 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3516 fetch->tex_id = instr->prefetch.tex;
3517 fetch->samp_id = instr->prefetch.samp;
3518 }
3519 fetch->wrmask = instr->regs[0]->wrmask;
3520 fetch->dst = instr->regs[0]->num;
3521 fetch->src = instr->prefetch.input_offset;
3522
3523 /* These are the limits on a5xx/a6xx, we might need to
3524 * revisit if SP_FS_PREFETCH[n] changes on later gens:
3525 */
3526 assert(fetch->dst <= 0x3f);
3527 assert(fetch->tex_id <= 0x1f);
3528 assert(fetch->samp_id < 0xf);
3529
3530 ctx->so->total_in =
3531 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3532
3533 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3534
3535 /* Remove the prefetch placeholder instruction: */
3536 list_delinit(&instr->node);
3537 }
3538 }
3539 }
3540 }
3541
3542 int
3543 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3544 struct ir3_shader_variant *so)
3545 {
3546 struct ir3_context *ctx;
3547 struct ir3 *ir;
3548 int ret = 0, max_bary;
3549 bool progress;
3550
3551 assert(!so->ir);
3552
3553 ctx = ir3_context_init(compiler, so);
3554 if (!ctx) {
3555 DBG("INIT failed!");
3556 ret = -1;
3557 goto out;
3558 }
3559
3560 emit_instructions(ctx);
3561
3562 if (ctx->error) {
3563 DBG("EMIT failed!");
3564 ret = -1;
3565 goto out;
3566 }
3567
3568 ir = so->ir = ctx->ir;
3569
3570 assert((ctx->noutputs % 4) == 0);
3571
3572 /* Setup IR level outputs, which are "collects" that gather
3573 * the scalar components of outputs.
3574 */
3575 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3576 unsigned ncomp = 0;
3577 /* figure out the # of components written:
3578 *
3579 * TODO do we need to handle holes, ie. if .x and .z
3580 * components written, but .y component not written?
3581 */
3582 for (unsigned j = 0; j < 4; j++) {
3583 if (!ctx->outputs[i + j])
3584 break;
3585 ncomp++;
3586 }
3587
3588 /* Note that in some stages, like TCS, store_output is
3589 * lowered to memory writes, so no components of the
3590 * are "written" from the PoV of traditional store-
3591 * output instructions:
3592 */
3593 if (!ncomp)
3594 continue;
3595
3596 struct ir3_instruction *out =
3597 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3598
3599 int outidx = i / 4;
3600 assert(outidx < so->outputs_count);
3601
3602 /* stash index into so->outputs[] so we can map the
3603 * output back to slot/etc later:
3604 */
3605 out->collect.outidx = outidx;
3606
3607 array_insert(ir, ir->outputs, out);
3608 }
3609
3610 /* Set up the gs header as an output for the vertex shader so it won't
3611 * clobber it for the tess ctrl shader.
3612 *
3613 * TODO this could probably be done more cleanly in a nir pass.
3614 */
3615 if (ctx->so->type == MESA_SHADER_VERTEX ||
3616 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3617 if (ctx->primitive_id) {
3618 unsigned n = so->outputs_count++;
3619 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3620
3621 struct ir3_instruction *out =
3622 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3623 out->collect.outidx = n;
3624 array_insert(ir, ir->outputs, out);
3625 }
3626
3627 if (ctx->gs_header) {
3628 unsigned n = so->outputs_count++;
3629 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3630 struct ir3_instruction *out =
3631 ir3_create_collect(ctx, &ctx->gs_header, 1);
3632 out->collect.outidx = n;
3633 array_insert(ir, ir->outputs, out);
3634 }
3635
3636 if (ctx->tcs_header) {
3637 unsigned n = so->outputs_count++;
3638 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3639 struct ir3_instruction *out =
3640 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3641 out->collect.outidx = n;
3642 array_insert(ir, ir->outputs, out);
3643 }
3644 }
3645
3646 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3647 * need to make sure not to remove any inputs that are used by
3648 * the nonbinning VS.
3649 */
3650 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3651 so->type == MESA_SHADER_VERTEX) {
3652 for (int i = 0; i < ctx->ninputs; i++) {
3653 struct ir3_instruction *in = ctx->inputs[i];
3654
3655 if (!in)
3656 continue;
3657
3658 unsigned n = i / 4;
3659 unsigned c = i % 4;
3660
3661 debug_assert(n < so->nonbinning->inputs_count);
3662
3663 if (so->nonbinning->inputs[n].sysval)
3664 continue;
3665
3666 /* be sure to keep inputs, even if only used in VS */
3667 if (so->nonbinning->inputs[n].compmask & (1 << c))
3668 array_insert(in->block, in->block->keeps, in);
3669 }
3670 }
3671
3672 /* at this point, for binning pass, throw away unneeded outputs: */
3673 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3674 fixup_binning_pass(ctx);
3675
3676 ir3_debug_print(ir, "AFTER: nir->ir3");
3677 ir3_validate(ir);
3678
3679 do {
3680 progress = false;
3681
3682 progress |= IR3_PASS(ir, ir3_cf);
3683 progress |= IR3_PASS(ir, ir3_cp, so);
3684 progress |= IR3_PASS(ir, ir3_dce, so);
3685 } while (progress);
3686
3687 /* at this point, for binning pass, throw away unneeded outputs:
3688 * Note that for a6xx and later, we do this after ir3_cp to ensure
3689 * that the uniform/constant layout for BS and VS matches, so that
3690 * we can re-use same VS_CONST state group.
3691 */
3692 if (so->binning_pass && (ctx->compiler->gpu_id >= 600)) {
3693 fixup_binning_pass(ctx);
3694 /* cleanup the result of removing unneeded outputs: */
3695 while (IR3_PASS(ir, ir3_dce, so)) {}
3696 }
3697
3698 IR3_PASS(ir, ir3_sched_add_deps);
3699
3700 /* Group left/right neighbors, inserting mov's where needed to
3701 * solve conflicts:
3702 */
3703 IR3_PASS(ir, ir3_group);
3704
3705 /* At this point, all the dead code should be long gone: */
3706 assert(!IR3_PASS(ir, ir3_dce, so));
3707
3708 ret = ir3_sched(ir);
3709 if (ret) {
3710 DBG("SCHED failed!");
3711 goto out;
3712 }
3713
3714 ir3_debug_print(ir, "AFTER: ir3_sched");
3715
3716 if (IR3_PASS(ir, ir3_cp_postsched)) {
3717 /* cleanup the result of removing unneeded mov's: */
3718 while (IR3_PASS(ir, ir3_dce, so)) {}
3719 }
3720
3721 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3722 * with draw pass VS, so binning and draw pass can both use the
3723 * same VBO state.
3724 *
3725 * Note that VS inputs are expected to be full precision.
3726 */
3727 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3728 (ir->type == MESA_SHADER_VERTEX) &&
3729 so->binning_pass;
3730
3731 if (pre_assign_inputs) {
3732 for (unsigned i = 0; i < ctx->ninputs; i++) {
3733 struct ir3_instruction *instr = ctx->inputs[i];
3734
3735 if (!instr)
3736 continue;
3737
3738 unsigned n = i / 4;
3739 unsigned c = i % 4;
3740 unsigned regid = so->nonbinning->inputs[n].regid + c;
3741
3742 instr->regs[0]->num = regid;
3743 }
3744
3745 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3746 } else if (ctx->tcs_header) {
3747 /* We need to have these values in the same registers between VS and TCS
3748 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3749 */
3750
3751 ctx->tcs_header->regs[0]->num = regid(0, 0);
3752 ctx->primitive_id->regs[0]->num = regid(0, 1);
3753 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3754 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3755 } else if (ctx->gs_header) {
3756 /* We need to have these values in the same registers between producer
3757 * (VS or DS) and GS since the producer chains to GS and doesn't get
3758 * the sysvals redelivered.
3759 */
3760
3761 ctx->gs_header->regs[0]->num = regid(0, 0);
3762 ctx->primitive_id->regs[0]->num = regid(0, 1);
3763 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3764 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3765 } else if (so->num_sampler_prefetch) {
3766 assert(so->type == MESA_SHADER_FRAGMENT);
3767 struct ir3_instruction *precolor[2];
3768 int idx = 0;
3769
3770 foreach_input (instr, ir) {
3771 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
3772 continue;
3773
3774 assert(idx < ARRAY_SIZE(precolor));
3775
3776 precolor[idx] = instr;
3777 instr->regs[0]->num = idx;
3778
3779 idx++;
3780 }
3781 ret = ir3_ra(so, precolor, idx);
3782 } else {
3783 ret = ir3_ra(so, NULL, 0);
3784 }
3785
3786 if (ret) {
3787 DBG("RA failed!");
3788 goto out;
3789 }
3790
3791 IR3_PASS(ir, ir3_postsched, so);
3792
3793 if (compiler->gpu_id >= 600) {
3794 IR3_PASS(ir, ir3_a6xx_fixup_atomic_dests, so);
3795 }
3796
3797 if (so->type == MESA_SHADER_FRAGMENT)
3798 pack_inlocs(ctx);
3799
3800 /*
3801 * Fixup inputs/outputs to point to the actual registers assigned:
3802 *
3803 * 1) initialize to r63.x (invalid/unused)
3804 * 2) iterate IR level inputs/outputs and update the variants
3805 * inputs/outputs table based on the assigned registers for
3806 * the remaining inputs/outputs.
3807 */
3808
3809 for (unsigned i = 0; i < so->inputs_count; i++)
3810 so->inputs[i].regid = INVALID_REG;
3811 for (unsigned i = 0; i < so->outputs_count; i++)
3812 so->outputs[i].regid = INVALID_REG;
3813
3814 foreach_output (out, ir) {
3815 assert(out->opc == OPC_META_COLLECT);
3816 unsigned outidx = out->collect.outidx;
3817
3818 so->outputs[outidx].regid = out->regs[0]->num;
3819 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3820 }
3821
3822 foreach_input (in, ir) {
3823 assert(in->opc == OPC_META_INPUT);
3824 unsigned inidx = in->input.inidx;
3825
3826 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3827 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3828 compile_assert(ctx, in->regs[0]->num ==
3829 so->nonbinning->inputs[inidx].regid);
3830 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3831 so->nonbinning->inputs[inidx].half);
3832 }
3833 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3834 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3835 } else {
3836 so->inputs[inidx].regid = in->regs[0]->num;
3837 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3838 }
3839 }
3840
3841 if (ctx->astc_srgb)
3842 fixup_astc_srgb(ctx);
3843
3844 /* We need to do legalize after (for frag shader's) the "bary.f"
3845 * offsets (inloc) have been assigned.
3846 */
3847 IR3_PASS(ir, ir3_legalize, so, &max_bary);
3848
3849 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3850 * know what we might have to wait on when coming in from VS chsh.
3851 */
3852 if (so->type == MESA_SHADER_TESS_CTRL ||
3853 so->type == MESA_SHADER_GEOMETRY ) {
3854 foreach_block (block, &ir->block_list) {
3855 foreach_instr (instr, &block->instr_list) {
3856 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3857 break;
3858 }
3859 }
3860 }
3861
3862 so->branchstack = ctx->max_stack;
3863
3864 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3865 if (so->type == MESA_SHADER_FRAGMENT)
3866 so->total_in = max_bary + 1;
3867
3868 /* Collect sampling instructions eligible for pre-dispatch. */
3869 collect_tex_prefetches(ctx, ir);
3870
3871 if (so->type == MESA_SHADER_FRAGMENT &&
3872 ctx->s->info.fs.needs_helper_invocations)
3873 so->need_pixlod = true;
3874
3875 out:
3876 if (ret) {
3877 if (so->ir)
3878 ir3_destroy(so->ir);
3879 so->ir = NULL;
3880 }
3881 ir3_context_free(ctx);
3882
3883 return ret;
3884 }