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freedreno: Include binning shaders in shader-db.
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 ir3_reg_create(mov, 0, 0);
55 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
56 src->instr = collect;
57 src->size = arrsz;
58 src->array.offset = n;
59
60 ir3_instr_set_address(mov, address);
61
62 return mov;
63 }
64
65 static struct ir3_instruction *
66 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
67 {
68 struct ir3_instruction *in;
69
70 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
71 in->inout.block = ctx->in_block;
72 ir3_reg_create(in, n, 0);
73
74 in->regs[0]->wrmask = compmask;
75
76 return in;
77 }
78
79 static struct ir3_instruction *
80 create_input(struct ir3_context *ctx, unsigned n)
81 {
82 return create_input_compmask(ctx, n, 0x1);
83 }
84
85 static struct ir3_instruction *
86 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
87 {
88 struct ir3_block *block = ctx->block;
89 struct ir3_instruction *instr;
90 /* packed inloc is fixed up later: */
91 struct ir3_instruction *inloc = create_immed(block, n);
92
93 if (use_ldlv) {
94 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
95 instr->cat6.type = TYPE_U32;
96 instr->cat6.iim_val = 1;
97 } else {
98 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
99 instr->regs[2]->wrmask = 0x3;
100 }
101
102 return instr;
103 }
104
105 static struct ir3_instruction *
106 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
107 {
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
111 unsigned n = const_state->offsets.driver_param;
112 unsigned r = regid(n + dp / 4, dp % 4);
113 return create_uniform(ctx->block, r);
114 }
115
116 /*
117 * Adreno uses uint rather than having dedicated bool type,
118 * which (potentially) requires some conversion, in particular
119 * when using output of an bool instr to int input, or visa
120 * versa.
121 *
122 * | Adreno | NIR |
123 * -------+---------+-------+-
124 * true | 1 | ~0 |
125 * false | 0 | 0 |
126 *
127 * To convert from an adreno bool (uint) to nir, use:
128 *
129 * absneg.s dst, (neg)src
130 *
131 * To convert back in the other direction:
132 *
133 * absneg.s dst, (abs)arc
134 *
135 * The CP step can clean up the absneg.s that cancel each other
136 * out, and with a slight bit of extra cleverness (to recognize
137 * the instructions which produce either a 0 or 1) can eliminate
138 * the absneg.s's completely when an instruction that wants
139 * 0/1 consumes the result. For example, when a nir 'bcsel'
140 * consumes the result of 'feq'. So we should be able to get by
141 * without a boolean resolve step, and without incuring any
142 * extra penalty in instruction count.
143 */
144
145 /* NIR bool -> native (adreno): */
146 static struct ir3_instruction *
147 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
150 }
151
152 /* native (adreno) -> NIR bool: */
153 static struct ir3_instruction *
154 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
155 {
156 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
157 }
158
159 /*
160 * alu/sfu instructions:
161 */
162
163 static struct ir3_instruction *
164 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
165 unsigned src_bitsize, nir_op op)
166 {
167 type_t src_type, dst_type;
168
169 switch (op) {
170 case nir_op_f2f32:
171 case nir_op_f2f16_rtne:
172 case nir_op_f2f16_rtz:
173 case nir_op_f2f16:
174 case nir_op_f2i32:
175 case nir_op_f2i16:
176 case nir_op_f2i8:
177 case nir_op_f2u32:
178 case nir_op_f2u16:
179 case nir_op_f2u8:
180 switch (src_bitsize) {
181 case 32:
182 src_type = TYPE_F32;
183 break;
184 case 16:
185 src_type = TYPE_F16;
186 break;
187 default:
188 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
189 }
190 break;
191
192 case nir_op_i2f32:
193 case nir_op_i2f16:
194 case nir_op_i2i32:
195 case nir_op_i2i16:
196 case nir_op_i2i8:
197 switch (src_bitsize) {
198 case 32:
199 src_type = TYPE_S32;
200 break;
201 case 16:
202 src_type = TYPE_S16;
203 break;
204 case 8:
205 src_type = TYPE_S8;
206 break;
207 default:
208 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
209 }
210 break;
211
212 case nir_op_u2f32:
213 case nir_op_u2f16:
214 case nir_op_u2u32:
215 case nir_op_u2u16:
216 case nir_op_u2u8:
217 switch (src_bitsize) {
218 case 32:
219 src_type = TYPE_U32;
220 break;
221 case 16:
222 src_type = TYPE_U16;
223 break;
224 case 8:
225 src_type = TYPE_U8;
226 break;
227 default:
228 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
229 }
230 break;
231
232 default:
233 ir3_context_error(ctx, "invalid conversion op: %u", op);
234 }
235
236 switch (op) {
237 case nir_op_f2f32:
238 case nir_op_i2f32:
239 case nir_op_u2f32:
240 dst_type = TYPE_F32;
241 break;
242
243 case nir_op_f2f16_rtne:
244 case nir_op_f2f16_rtz:
245 case nir_op_f2f16:
246 /* TODO how to handle rounding mode? */
247 case nir_op_i2f16:
248 case nir_op_u2f16:
249 dst_type = TYPE_F16;
250 break;
251
252 case nir_op_f2i32:
253 case nir_op_i2i32:
254 dst_type = TYPE_S32;
255 break;
256
257 case nir_op_f2i16:
258 case nir_op_i2i16:
259 dst_type = TYPE_S16;
260 break;
261
262 case nir_op_f2i8:
263 case nir_op_i2i8:
264 dst_type = TYPE_S8;
265 break;
266
267 case nir_op_f2u32:
268 case nir_op_u2u32:
269 dst_type = TYPE_U32;
270 break;
271
272 case nir_op_f2u16:
273 case nir_op_u2u16:
274 dst_type = TYPE_U16;
275 break;
276
277 case nir_op_f2u8:
278 case nir_op_u2u8:
279 dst_type = TYPE_U8;
280 break;
281
282 default:
283 ir3_context_error(ctx, "invalid conversion op: %u", op);
284 }
285
286 return ir3_COV(ctx->block, src, src_type, dst_type);
287 }
288
289 static void
290 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
291 {
292 const nir_op_info *info = &nir_op_infos[alu->op];
293 struct ir3_instruction **dst, *src[info->num_inputs];
294 unsigned bs[info->num_inputs]; /* bit size */
295 struct ir3_block *b = ctx->block;
296 unsigned dst_sz, wrmask;
297 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
298 TYPE_U16 : TYPE_U32;
299
300 if (alu->dest.dest.is_ssa) {
301 dst_sz = alu->dest.dest.ssa.num_components;
302 wrmask = (1 << dst_sz) - 1;
303 } else {
304 dst_sz = alu->dest.dest.reg.reg->num_components;
305 wrmask = alu->dest.write_mask;
306 }
307
308 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
309
310 /* Vectors are special in that they have non-scalarized writemasks,
311 * and just take the first swizzle channel for each argument in
312 * order into each writemask channel.
313 */
314 if ((alu->op == nir_op_vec2) ||
315 (alu->op == nir_op_vec3) ||
316 (alu->op == nir_op_vec4)) {
317
318 for (int i = 0; i < info->num_inputs; i++) {
319 nir_alu_src *asrc = &alu->src[i];
320
321 compile_assert(ctx, !asrc->abs);
322 compile_assert(ctx, !asrc->negate);
323
324 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
325 if (!src[i])
326 src[i] = create_immed_typed(ctx->block, 0, dst_type);
327 dst[i] = ir3_MOV(b, src[i], dst_type);
328 }
329
330 ir3_put_dst(ctx, &alu->dest.dest);
331 return;
332 }
333
334 /* We also get mov's with more than one component for mov's so
335 * handle those specially:
336 */
337 if (alu->op == nir_op_mov) {
338 nir_alu_src *asrc = &alu->src[0];
339 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
340
341 for (unsigned i = 0; i < dst_sz; i++) {
342 if (wrmask & (1 << i)) {
343 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
344 } else {
345 dst[i] = NULL;
346 }
347 }
348
349 ir3_put_dst(ctx, &alu->dest.dest);
350 return;
351 }
352
353 /* General case: We can just grab the one used channel per src. */
354 for (int i = 0; i < info->num_inputs; i++) {
355 unsigned chan = ffs(alu->dest.write_mask) - 1;
356 nir_alu_src *asrc = &alu->src[i];
357
358 compile_assert(ctx, !asrc->abs);
359 compile_assert(ctx, !asrc->negate);
360
361 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
362 bs[i] = nir_src_bit_size(asrc->src);
363
364 compile_assert(ctx, src[i]);
365 }
366
367 switch (alu->op) {
368 case nir_op_f2f32:
369 case nir_op_f2f16_rtne:
370 case nir_op_f2f16_rtz:
371 case nir_op_f2f16:
372 case nir_op_f2i32:
373 case nir_op_f2i16:
374 case nir_op_f2i8:
375 case nir_op_f2u32:
376 case nir_op_f2u16:
377 case nir_op_f2u8:
378 case nir_op_i2f32:
379 case nir_op_i2f16:
380 case nir_op_i2i32:
381 case nir_op_i2i16:
382 case nir_op_i2i8:
383 case nir_op_u2f32:
384 case nir_op_u2f16:
385 case nir_op_u2u32:
386 case nir_op_u2u16:
387 case nir_op_u2u8:
388 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
389 break;
390 case nir_op_f2b32:
391 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
392 dst[0]->cat2.condition = IR3_COND_NE;
393 dst[0] = ir3_n2b(b, dst[0]);
394 break;
395 case nir_op_b2f16:
396 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
397 break;
398 case nir_op_b2f32:
399 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
400 break;
401 case nir_op_b2i8:
402 case nir_op_b2i16:
403 case nir_op_b2i32:
404 dst[0] = ir3_b2n(b, src[0]);
405 break;
406 case nir_op_i2b32:
407 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
408 dst[0]->cat2.condition = IR3_COND_NE;
409 dst[0] = ir3_n2b(b, dst[0]);
410 break;
411
412 case nir_op_fneg:
413 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
414 break;
415 case nir_op_fabs:
416 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
417 break;
418 case nir_op_fmax:
419 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
420 break;
421 case nir_op_fmin:
422 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
423 break;
424 case nir_op_fsat:
425 /* if there is just a single use of the src, and it supports
426 * (sat) bit, we can just fold the (sat) flag back to the
427 * src instruction and create a mov. This is easier for cp
428 * to eliminate.
429 *
430 * TODO probably opc_cat==4 is ok too
431 */
432 if (alu->src[0].src.is_ssa &&
433 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
434 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
435 src[0]->flags |= IR3_INSTR_SAT;
436 dst[0] = ir3_MOV(b, src[0], dst_type);
437 } else {
438 /* otherwise generate a max.f that saturates.. blob does
439 * similar (generating a cat2 mov using max.f)
440 */
441 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
442 dst[0]->flags |= IR3_INSTR_SAT;
443 }
444 break;
445 case nir_op_fmul:
446 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
447 break;
448 case nir_op_fadd:
449 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
450 break;
451 case nir_op_fsub:
452 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
453 break;
454 case nir_op_ffma:
455 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
456 break;
457 case nir_op_fddx:
458 dst[0] = ir3_DSX(b, src[0], 0);
459 dst[0]->cat5.type = TYPE_F32;
460 break;
461 case nir_op_fddy:
462 dst[0] = ir3_DSY(b, src[0], 0);
463 dst[0]->cat5.type = TYPE_F32;
464 break;
465 break;
466 case nir_op_flt32:
467 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
468 dst[0]->cat2.condition = IR3_COND_LT;
469 dst[0] = ir3_n2b(b, dst[0]);
470 break;
471 case nir_op_fge32:
472 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
473 dst[0]->cat2.condition = IR3_COND_GE;
474 dst[0] = ir3_n2b(b, dst[0]);
475 break;
476 case nir_op_feq32:
477 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
478 dst[0]->cat2.condition = IR3_COND_EQ;
479 dst[0] = ir3_n2b(b, dst[0]);
480 break;
481 case nir_op_fne32:
482 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
483 dst[0]->cat2.condition = IR3_COND_NE;
484 dst[0] = ir3_n2b(b, dst[0]);
485 break;
486 case nir_op_fceil:
487 dst[0] = ir3_CEIL_F(b, src[0], 0);
488 break;
489 case nir_op_ffloor:
490 dst[0] = ir3_FLOOR_F(b, src[0], 0);
491 break;
492 case nir_op_ftrunc:
493 dst[0] = ir3_TRUNC_F(b, src[0], 0);
494 break;
495 case nir_op_fround_even:
496 dst[0] = ir3_RNDNE_F(b, src[0], 0);
497 break;
498 case nir_op_fsign:
499 dst[0] = ir3_SIGN_F(b, src[0], 0);
500 break;
501
502 case nir_op_fsin:
503 dst[0] = ir3_SIN(b, src[0], 0);
504 break;
505 case nir_op_fcos:
506 dst[0] = ir3_COS(b, src[0], 0);
507 break;
508 case nir_op_frsq:
509 dst[0] = ir3_RSQ(b, src[0], 0);
510 break;
511 case nir_op_frcp:
512 dst[0] = ir3_RCP(b, src[0], 0);
513 break;
514 case nir_op_flog2:
515 dst[0] = ir3_LOG2(b, src[0], 0);
516 break;
517 case nir_op_fexp2:
518 dst[0] = ir3_EXP2(b, src[0], 0);
519 break;
520 case nir_op_fsqrt:
521 dst[0] = ir3_SQRT(b, src[0], 0);
522 break;
523
524 case nir_op_iabs:
525 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
526 break;
527 case nir_op_iadd:
528 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
529 break;
530 case nir_op_iand:
531 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
532 break;
533 case nir_op_imax:
534 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
535 break;
536 case nir_op_umax:
537 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
538 break;
539 case nir_op_imin:
540 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
541 break;
542 case nir_op_umin:
543 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
544 break;
545 case nir_op_umul_low:
546 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
547 break;
548 case nir_op_imadsh_mix16:
549 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
550 break;
551 case nir_op_ineg:
552 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
553 break;
554 case nir_op_inot:
555 dst[0] = ir3_NOT_B(b, src[0], 0);
556 break;
557 case nir_op_ior:
558 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
559 break;
560 case nir_op_ishl:
561 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
562 break;
563 case nir_op_ishr:
564 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_isub:
567 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
568 break;
569 case nir_op_ixor:
570 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
571 break;
572 case nir_op_ushr:
573 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
574 break;
575 case nir_op_ilt32:
576 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
577 dst[0]->cat2.condition = IR3_COND_LT;
578 dst[0] = ir3_n2b(b, dst[0]);
579 break;
580 case nir_op_ige32:
581 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
582 dst[0]->cat2.condition = IR3_COND_GE;
583 dst[0] = ir3_n2b(b, dst[0]);
584 break;
585 case nir_op_ieq32:
586 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
587 dst[0]->cat2.condition = IR3_COND_EQ;
588 dst[0] = ir3_n2b(b, dst[0]);
589 break;
590 case nir_op_ine32:
591 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
592 dst[0]->cat2.condition = IR3_COND_NE;
593 dst[0] = ir3_n2b(b, dst[0]);
594 break;
595 case nir_op_ult32:
596 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
597 dst[0]->cat2.condition = IR3_COND_LT;
598 dst[0] = ir3_n2b(b, dst[0]);
599 break;
600 case nir_op_uge32:
601 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
602 dst[0]->cat2.condition = IR3_COND_GE;
603 dst[0] = ir3_n2b(b, dst[0]);
604 break;
605
606 case nir_op_b32csel: {
607 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
608 compile_assert(ctx, bs[1] == bs[2]);
609 /* the boolean condition is 32b even if src[1] and src[2] are
610 * half-precision, but sel.b16 wants all three src's to be the
611 * same type.
612 */
613 if (bs[1] < 32)
614 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
615 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
616 break;
617 }
618 case nir_op_bit_count: {
619 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
620 // double check on earlier gen's. Once half-precision support is
621 // in place, this should probably move to a NIR lowering pass:
622 struct ir3_instruction *hi, *lo;
623
624 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
625 TYPE_U32, TYPE_U16);
626 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
627
628 hi = ir3_CBITS_B(b, hi, 0);
629 lo = ir3_CBITS_B(b, lo, 0);
630
631 // TODO maybe the builders should default to making dst half-precision
632 // if the src's were half precision, to make this less awkward.. otoh
633 // we should probably just do this lowering in NIR.
634 hi->regs[0]->flags |= IR3_REG_HALF;
635 lo->regs[0]->flags |= IR3_REG_HALF;
636
637 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
638 dst[0]->regs[0]->flags |= IR3_REG_HALF;
639 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
640 break;
641 }
642 case nir_op_ifind_msb: {
643 struct ir3_instruction *cmp;
644 dst[0] = ir3_CLZ_S(b, src[0], 0);
645 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
646 cmp->cat2.condition = IR3_COND_GE;
647 dst[0] = ir3_SEL_B32(b,
648 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
649 cmp, 0, dst[0], 0);
650 break;
651 }
652 case nir_op_ufind_msb:
653 dst[0] = ir3_CLZ_B(b, src[0], 0);
654 dst[0] = ir3_SEL_B32(b,
655 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
656 src[0], 0, dst[0], 0);
657 break;
658 case nir_op_find_lsb:
659 dst[0] = ir3_BFREV_B(b, src[0], 0);
660 dst[0] = ir3_CLZ_B(b, dst[0], 0);
661 break;
662 case nir_op_bitfield_reverse:
663 dst[0] = ir3_BFREV_B(b, src[0], 0);
664 break;
665
666 default:
667 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
668 nir_op_infos[alu->op].name);
669 break;
670 }
671
672 ir3_put_dst(ctx, &alu->dest.dest);
673 }
674
675 /* handles direct/indirect UBO reads: */
676 static void
677 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
678 struct ir3_instruction **dst)
679 {
680 struct ir3_block *b = ctx->block;
681 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
682 /* UBO addresses are the first driver params, but subtract 2 here to
683 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
684 * is the uniforms: */
685 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
686 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
687 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
688
689 int off = 0;
690
691 /* First src is ubo index, which could either be an immed or not: */
692 src0 = ir3_get_src(ctx, &intr->src[0])[0];
693 if (is_same_type_mov(src0) &&
694 (src0->regs[1]->flags & IR3_REG_IMMED)) {
695 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
696 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
697 } else {
698 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
699 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
700
701 /* NOTE: since relative addressing is used, make sure constlen is
702 * at least big enough to cover all the UBO addresses, since the
703 * assembler won't know what the max address reg is.
704 */
705 ctx->so->constlen = MAX2(ctx->so->constlen,
706 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
707 }
708
709 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
710 addr = base_lo;
711
712 if (nir_src_is_const(intr->src[1])) {
713 off += nir_src_as_uint(intr->src[1]);
714 } else {
715 /* For load_ubo_indirect, second src is indirect offset: */
716 src1 = ir3_get_src(ctx, &intr->src[1])[0];
717
718 /* and add offset to addr: */
719 addr = ir3_ADD_S(b, addr, 0, src1, 0);
720 }
721
722 /* if offset is to large to encode in the ldg, split it out: */
723 if ((off + (intr->num_components * 4)) > 1024) {
724 /* split out the minimal amount to improve the odds that
725 * cp can fit the immediate in the add.s instruction:
726 */
727 unsigned off2 = off + (intr->num_components * 4) - 1024;
728 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
729 off -= off2;
730 }
731
732 if (ptrsz == 2) {
733 struct ir3_instruction *carry;
734
735 /* handle 32b rollover, ie:
736 * if (addr < base_lo)
737 * base_hi++
738 */
739 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
740 carry->cat2.condition = IR3_COND_LT;
741 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
742
743 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
744 }
745
746 for (int i = 0; i < intr->num_components; i++) {
747 struct ir3_instruction *load =
748 ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
749 load->cat6.type = TYPE_U32;
750 load->cat6.src_offset = off + i * 4; /* byte offset */
751 dst[i] = load;
752 }
753 }
754
755 /* src[] = { block_index } */
756 static void
757 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
758 struct ir3_instruction **dst)
759 {
760 /* SSBO size stored as a const starting at ssbo_sizes: */
761 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
762 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
763 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
764 const_state->ssbo_size.off[blk_idx];
765
766 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
767
768 dst[0] = create_uniform(ctx->block, idx);
769 }
770
771 /* src[] = { offset }. const_index[] = { base } */
772 static void
773 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
774 struct ir3_instruction **dst)
775 {
776 struct ir3_block *b = ctx->block;
777 struct ir3_instruction *ldl, *offset;
778 unsigned base;
779
780 offset = ir3_get_src(ctx, &intr->src[0])[0];
781 base = nir_intrinsic_base(intr);
782
783 ldl = ir3_LDL(b, offset, 0, create_immed(b, intr->num_components), 0);
784 ldl->cat6.src_offset = base;
785 ldl->cat6.type = utype_dst(intr->dest);
786 ldl->regs[0]->wrmask = MASK(intr->num_components);
787
788 ldl->barrier_class = IR3_BARRIER_SHARED_R;
789 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
790
791 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
792 }
793
794 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
795 static void
796 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
797 {
798 struct ir3_block *b = ctx->block;
799 struct ir3_instruction *stl, *offset;
800 struct ir3_instruction * const *value;
801 unsigned base, wrmask;
802
803 value = ir3_get_src(ctx, &intr->src[0]);
804 offset = ir3_get_src(ctx, &intr->src[1])[0];
805
806 base = nir_intrinsic_base(intr);
807 wrmask = nir_intrinsic_write_mask(intr);
808
809 /* Combine groups of consecutive enabled channels in one write
810 * message. We use ffs to find the first enabled channel and then ffs on
811 * the bit-inverse, down-shifted writemask to determine the length of
812 * the block of enabled bits.
813 *
814 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
815 */
816 while (wrmask) {
817 unsigned first_component = ffs(wrmask) - 1;
818 unsigned length = ffs(~(wrmask >> first_component)) - 1;
819
820 stl = ir3_STL(b, offset, 0,
821 ir3_create_collect(ctx, &value[first_component], length), 0,
822 create_immed(b, length), 0);
823 stl->cat6.dst_offset = first_component + base;
824 stl->cat6.type = utype_src(intr->src[0]);
825 stl->barrier_class = IR3_BARRIER_SHARED_W;
826 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
827
828 array_insert(b, b->keeps, stl);
829
830 /* Clear the bits in the writemask that we just wrote, then try
831 * again to see if more channels are left.
832 */
833 wrmask &= (15 << (first_component + length));
834 }
835 }
836
837 /*
838 * CS shared variable atomic intrinsics
839 *
840 * All of the shared variable atomic memory operations read a value from
841 * memory, compute a new value using one of the operations below, write the
842 * new value to memory, and return the original value read.
843 *
844 * All operations take 2 sources except CompSwap that takes 3. These
845 * sources represent:
846 *
847 * 0: The offset into the shared variable storage region that the atomic
848 * operation will operate on.
849 * 1: The data parameter to the atomic function (i.e. the value to add
850 * in shared_atomic_add, etc).
851 * 2: For CompSwap only: the second data parameter.
852 */
853 static struct ir3_instruction *
854 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
855 {
856 struct ir3_block *b = ctx->block;
857 struct ir3_instruction *atomic, *src0, *src1;
858 type_t type = TYPE_U32;
859
860 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
861 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
862
863 switch (intr->intrinsic) {
864 case nir_intrinsic_shared_atomic_add:
865 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
866 break;
867 case nir_intrinsic_shared_atomic_imin:
868 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
869 type = TYPE_S32;
870 break;
871 case nir_intrinsic_shared_atomic_umin:
872 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
873 break;
874 case nir_intrinsic_shared_atomic_imax:
875 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
876 type = TYPE_S32;
877 break;
878 case nir_intrinsic_shared_atomic_umax:
879 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
880 break;
881 case nir_intrinsic_shared_atomic_and:
882 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
883 break;
884 case nir_intrinsic_shared_atomic_or:
885 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
886 break;
887 case nir_intrinsic_shared_atomic_xor:
888 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
889 break;
890 case nir_intrinsic_shared_atomic_exchange:
891 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
892 break;
893 case nir_intrinsic_shared_atomic_comp_swap:
894 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
895 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
896 ir3_get_src(ctx, &intr->src[2])[0],
897 src1,
898 }, 2);
899 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
900 break;
901 default:
902 unreachable("boo");
903 }
904
905 atomic->cat6.iim_val = 1;
906 atomic->cat6.d = 1;
907 atomic->cat6.type = type;
908 atomic->barrier_class = IR3_BARRIER_SHARED_W;
909 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
910
911 /* even if nothing consume the result, we can't DCE the instruction: */
912 array_insert(b, b->keeps, atomic);
913
914 return atomic;
915 }
916
917 /* TODO handle actual indirect/dynamic case.. which is going to be weird
918 * to handle with the image_mapping table..
919 */
920 static struct ir3_instruction *
921 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
922 {
923 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
924 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
925 struct ir3_instruction *texture, *sampler;
926
927 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
928 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
929
930 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
931 sampler,
932 texture,
933 }, 2);
934 }
935
936 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
937 static void
938 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
939 struct ir3_instruction **dst)
940 {
941 struct ir3_block *b = ctx->block;
942 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
943 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
944 struct ir3_instruction *sam;
945 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
946 struct ir3_instruction *coords[4];
947 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
948 type_t type = ir3_get_image_type(var);
949
950 /* hmm, this seems a bit odd, but it is what blob does and (at least
951 * a5xx) just faults on bogus addresses otherwise:
952 */
953 if (flags & IR3_INSTR_3D) {
954 flags &= ~IR3_INSTR_3D;
955 flags |= IR3_INSTR_A;
956 }
957
958 for (unsigned i = 0; i < ncoords; i++)
959 coords[i] = src0[i];
960
961 if (ncoords == 1)
962 coords[ncoords++] = create_immed(b, 0);
963
964 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
965 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
966
967 sam->barrier_class = IR3_BARRIER_IMAGE_R;
968 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
969
970 ir3_split_dest(b, dst, sam, 0, 4);
971 }
972
973 static void
974 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
975 struct ir3_instruction **dst)
976 {
977 struct ir3_block *b = ctx->block;
978 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
979 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
980 struct ir3_instruction *sam, *lod;
981 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
982
983 lod = create_immed(b, 0);
984 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
985 samp_tex, lod, NULL);
986
987 /* Array size actually ends up in .w rather than .z. This doesn't
988 * matter for miplevel 0, but for higher mips the value in z is
989 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
990 * returned, which means that we have to add 1 to it for arrays for
991 * a3xx.
992 *
993 * Note use a temporary dst and then copy, since the size of the dst
994 * array that is passed in is based on nir's understanding of the
995 * result size, not the hardware's
996 */
997 struct ir3_instruction *tmp[4];
998
999 ir3_split_dest(b, tmp, sam, 0, 4);
1000
1001 /* get_size instruction returns size in bytes instead of texels
1002 * for imageBuffer, so we need to divide it by the pixel size
1003 * of the image format.
1004 *
1005 * TODO: This is at least true on a5xx. Check other gens.
1006 */
1007 enum glsl_sampler_dim dim =
1008 glsl_get_sampler_dim(glsl_without_array(var->type));
1009 if (dim == GLSL_SAMPLER_DIM_BUF) {
1010 /* Since all the possible values the divisor can take are
1011 * power-of-two (4, 8, or 16), the division is implemented
1012 * as a shift-right.
1013 * During shader setup, the log2 of the image format's
1014 * bytes-per-pixel should have been emitted in 2nd slot of
1015 * image_dims. See ir3_shader::emit_image_dims().
1016 */
1017 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1018 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1019 const_state->image_dims.off[var->data.driver_location];
1020 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1021
1022 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1023 }
1024
1025 for (unsigned i = 0; i < ncoords; i++)
1026 dst[i] = tmp[i];
1027
1028 if (flags & IR3_INSTR_A) {
1029 if (ctx->compiler->levels_add_one) {
1030 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1031 } else {
1032 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1033 }
1034 }
1035 }
1036
1037 static void
1038 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1039 {
1040 struct ir3_block *b = ctx->block;
1041 struct ir3_instruction *barrier;
1042
1043 switch (intr->intrinsic) {
1044 case nir_intrinsic_barrier:
1045 barrier = ir3_BAR(b);
1046 barrier->cat7.g = true;
1047 barrier->cat7.l = true;
1048 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1049 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1050 break;
1051 case nir_intrinsic_memory_barrier:
1052 barrier = ir3_FENCE(b);
1053 barrier->cat7.g = true;
1054 barrier->cat7.r = true;
1055 barrier->cat7.w = true;
1056 barrier->cat7.l = true;
1057 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1058 IR3_BARRIER_BUFFER_W;
1059 barrier->barrier_conflict =
1060 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1061 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1062 break;
1063 case nir_intrinsic_memory_barrier_atomic_counter:
1064 case nir_intrinsic_memory_barrier_buffer:
1065 barrier = ir3_FENCE(b);
1066 barrier->cat7.g = true;
1067 barrier->cat7.r = true;
1068 barrier->cat7.w = true;
1069 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1070 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1071 IR3_BARRIER_BUFFER_W;
1072 break;
1073 case nir_intrinsic_memory_barrier_image:
1074 // TODO double check if this should have .g set
1075 barrier = ir3_FENCE(b);
1076 barrier->cat7.g = true;
1077 barrier->cat7.r = true;
1078 barrier->cat7.w = true;
1079 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1080 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1081 IR3_BARRIER_IMAGE_W;
1082 break;
1083 case nir_intrinsic_memory_barrier_shared:
1084 barrier = ir3_FENCE(b);
1085 barrier->cat7.g = true;
1086 barrier->cat7.l = true;
1087 barrier->cat7.r = true;
1088 barrier->cat7.w = true;
1089 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1090 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1091 IR3_BARRIER_SHARED_W;
1092 break;
1093 case nir_intrinsic_group_memory_barrier:
1094 barrier = ir3_FENCE(b);
1095 barrier->cat7.g = true;
1096 barrier->cat7.l = true;
1097 barrier->cat7.r = true;
1098 barrier->cat7.w = true;
1099 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1100 IR3_BARRIER_IMAGE_W |
1101 IR3_BARRIER_BUFFER_W;
1102 barrier->barrier_conflict =
1103 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1104 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1105 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1106 break;
1107 default:
1108 unreachable("boo");
1109 }
1110
1111 /* make sure barrier doesn't get DCE'd */
1112 array_insert(b, b->keeps, barrier);
1113 }
1114
1115 static void add_sysval_input_compmask(struct ir3_context *ctx,
1116 gl_system_value slot, unsigned compmask,
1117 struct ir3_instruction *instr)
1118 {
1119 struct ir3_shader_variant *so = ctx->so;
1120 unsigned r = regid(so->inputs_count, 0);
1121 unsigned n = so->inputs_count++;
1122
1123 so->inputs[n].sysval = true;
1124 so->inputs[n].slot = slot;
1125 so->inputs[n].compmask = compmask;
1126 so->inputs[n].regid = r;
1127 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1128 so->total_in++;
1129
1130 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1131 ctx->ir->inputs[r] = instr;
1132 }
1133
1134 static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1135 struct ir3_instruction *instr)
1136 {
1137 add_sysval_input_compmask(ctx, slot, 0x1, instr);
1138 }
1139
1140 static struct ir3_instruction *
1141 get_barycentric_centroid(struct ir3_context *ctx)
1142 {
1143 if (!ctx->ij_centroid) {
1144 struct ir3_instruction *xy[2];
1145 struct ir3_instruction *ij;
1146
1147 ij = create_input_compmask(ctx, 0, 0x3);
1148 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1149
1150 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1151
1152 add_sysval_input_compmask(ctx,
1153 SYSTEM_VALUE_BARYCENTRIC_CENTROID,
1154 0x3, ij);
1155 }
1156
1157 return ctx->ij_centroid;
1158 }
1159
1160 static struct ir3_instruction *
1161 get_barycentric_sample(struct ir3_context *ctx)
1162 {
1163 if (!ctx->ij_sample) {
1164 struct ir3_instruction *xy[2];
1165 struct ir3_instruction *ij;
1166
1167 ij = create_input_compmask(ctx, 0, 0x3);
1168 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1169
1170 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1171
1172 add_sysval_input_compmask(ctx,
1173 SYSTEM_VALUE_BARYCENTRIC_SAMPLE,
1174 0x3, ij);
1175 }
1176
1177 return ctx->ij_sample;
1178 }
1179
1180 static struct ir3_instruction *
1181 get_barycentric_pixel(struct ir3_context *ctx)
1182 {
1183 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1184 * this to create ij_pixel only on demand:
1185 */
1186 return ctx->ij_pixel;
1187 }
1188
1189 static struct ir3_instruction *
1190 get_frag_coord(struct ir3_context *ctx)
1191 {
1192 if (!ctx->frag_coord) {
1193 struct ir3_block *b = ctx->block;
1194 struct ir3_instruction *xyzw[4];
1195 struct ir3_instruction *hw_frag_coord;
1196
1197 hw_frag_coord = create_input_compmask(ctx, 0, 0xf);
1198 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1199
1200 /* for frag_coord.xy, we get unsigned values.. we need
1201 * to subtract (integer) 8 and divide by 16 (right-
1202 * shift by 4) then convert to float:
1203 *
1204 * sub.s tmp, src, 8
1205 * shr.b tmp, tmp, 4
1206 * mov.u32f32 dst, tmp
1207 *
1208 */
1209 for (int i = 0; i < 2; i++) {
1210 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1211 create_immed(b, 8), 0);
1212 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1213 create_immed(b, 4), 0);
1214 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1215 }
1216
1217 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1218
1219 add_sysval_input_compmask(ctx,
1220 SYSTEM_VALUE_FRAG_COORD,
1221 0xf, hw_frag_coord);
1222
1223 ctx->so->frag_coord = true;
1224 }
1225
1226 return ctx->frag_coord;
1227 }
1228
1229 static void
1230 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1231 {
1232 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1233 struct ir3_instruction **dst;
1234 struct ir3_instruction * const *src;
1235 struct ir3_block *b = ctx->block;
1236 int idx, comp;
1237
1238 if (info->has_dest) {
1239 unsigned n = nir_intrinsic_dest_components(intr);
1240 dst = ir3_get_dst(ctx, &intr->dest, n);
1241 } else {
1242 dst = NULL;
1243 }
1244
1245 switch (intr->intrinsic) {
1246 case nir_intrinsic_load_uniform:
1247 idx = nir_intrinsic_base(intr);
1248 if (nir_src_is_const(intr->src[0])) {
1249 idx += nir_src_as_uint(intr->src[0]);
1250 for (int i = 0; i < intr->num_components; i++) {
1251 dst[i] = create_uniform_typed(b, idx + i,
1252 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1253 }
1254 } else {
1255 src = ir3_get_src(ctx, &intr->src[0]);
1256 for (int i = 0; i < intr->num_components; i++) {
1257 dst[i] = create_uniform_indirect(b, idx + i,
1258 ir3_get_addr(ctx, src[0], 1));
1259 }
1260 /* NOTE: if relative addressing is used, we set
1261 * constlen in the compiler (to worst-case value)
1262 * since we don't know in the assembler what the max
1263 * addr reg value can be:
1264 */
1265 ctx->so->constlen = MAX2(ctx->so->constlen, ctx->s->num_uniforms);
1266 }
1267 break;
1268 case nir_intrinsic_load_ubo:
1269 emit_intrinsic_load_ubo(ctx, intr, dst);
1270 break;
1271 case nir_intrinsic_load_frag_coord:
1272 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1273 break;
1274 case nir_intrinsic_load_sample_pos_from_id: {
1275 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1276 * but that doesn't seem necessary.
1277 */
1278 struct ir3_instruction *offset =
1279 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1280 offset->regs[0]->wrmask = 0x3;
1281 offset->cat5.type = TYPE_F32;
1282
1283 ir3_split_dest(b, dst, offset, 0, 2);
1284
1285 break;
1286 }
1287 case nir_intrinsic_load_size_ir3:
1288 if (!ctx->ij_size) {
1289 ctx->ij_size = create_input(ctx, 0);
1290
1291 add_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SIZE,
1292 ctx->ij_size);
1293 }
1294 dst[0] = ctx->ij_size;
1295 break;
1296 case nir_intrinsic_load_barycentric_centroid:
1297 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1298 break;
1299 case nir_intrinsic_load_barycentric_sample:
1300 if (ctx->so->key.msaa) {
1301 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1302 } else {
1303 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1304 }
1305 break;
1306 case nir_intrinsic_load_barycentric_pixel:
1307 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1308 break;
1309 case nir_intrinsic_load_interpolated_input:
1310 idx = nir_intrinsic_base(intr);
1311 comp = nir_intrinsic_component(intr);
1312 src = ir3_get_src(ctx, &intr->src[0]);
1313 if (nir_src_is_const(intr->src[1])) {
1314 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1315 idx += nir_src_as_uint(intr->src[1]);
1316 for (int i = 0; i < intr->num_components; i++) {
1317 unsigned inloc = idx * 4 + i + comp;
1318 if (ctx->so->inputs[idx].bary &&
1319 !ctx->so->inputs[idx].use_ldlv) {
1320 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1321 } else {
1322 /* for non-varyings use the pre-setup input, since
1323 * that is easier than mapping things back to a
1324 * nir_variable to figure out what it is.
1325 */
1326 dst[i] = ctx->ir->inputs[inloc];
1327 }
1328 }
1329 } else {
1330 ir3_context_error(ctx, "unhandled");
1331 }
1332 break;
1333 case nir_intrinsic_load_input:
1334 idx = nir_intrinsic_base(intr);
1335 comp = nir_intrinsic_component(intr);
1336 if (nir_src_is_const(intr->src[0])) {
1337 idx += nir_src_as_uint(intr->src[0]);
1338 for (int i = 0; i < intr->num_components; i++) {
1339 unsigned n = idx * 4 + i + comp;
1340 dst[i] = ctx->ir->inputs[n];
1341 compile_assert(ctx, ctx->ir->inputs[n]);
1342 }
1343 } else {
1344 src = ir3_get_src(ctx, &intr->src[0]);
1345 struct ir3_instruction *collect =
1346 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1347 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1348 for (int i = 0; i < intr->num_components; i++) {
1349 unsigned n = idx * 4 + i + comp;
1350 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1351 n, addr, collect);
1352 }
1353 }
1354 break;
1355 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1356 * pass and replaced by an ir3-specifc version that adds the
1357 * dword-offset in the last source.
1358 */
1359 case nir_intrinsic_load_ssbo_ir3:
1360 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1361 break;
1362 case nir_intrinsic_store_ssbo_ir3:
1363 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1364 !ctx->s->info.fs.early_fragment_tests)
1365 ctx->so->no_earlyz = true;
1366 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1367 break;
1368 case nir_intrinsic_get_buffer_size:
1369 emit_intrinsic_ssbo_size(ctx, intr, dst);
1370 break;
1371 case nir_intrinsic_ssbo_atomic_add_ir3:
1372 case nir_intrinsic_ssbo_atomic_imin_ir3:
1373 case nir_intrinsic_ssbo_atomic_umin_ir3:
1374 case nir_intrinsic_ssbo_atomic_imax_ir3:
1375 case nir_intrinsic_ssbo_atomic_umax_ir3:
1376 case nir_intrinsic_ssbo_atomic_and_ir3:
1377 case nir_intrinsic_ssbo_atomic_or_ir3:
1378 case nir_intrinsic_ssbo_atomic_xor_ir3:
1379 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1380 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1381 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1382 !ctx->s->info.fs.early_fragment_tests)
1383 ctx->so->no_earlyz = true;
1384 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1385 break;
1386 case nir_intrinsic_load_shared:
1387 emit_intrinsic_load_shared(ctx, intr, dst);
1388 break;
1389 case nir_intrinsic_store_shared:
1390 emit_intrinsic_store_shared(ctx, intr);
1391 break;
1392 case nir_intrinsic_shared_atomic_add:
1393 case nir_intrinsic_shared_atomic_imin:
1394 case nir_intrinsic_shared_atomic_umin:
1395 case nir_intrinsic_shared_atomic_imax:
1396 case nir_intrinsic_shared_atomic_umax:
1397 case nir_intrinsic_shared_atomic_and:
1398 case nir_intrinsic_shared_atomic_or:
1399 case nir_intrinsic_shared_atomic_xor:
1400 case nir_intrinsic_shared_atomic_exchange:
1401 case nir_intrinsic_shared_atomic_comp_swap:
1402 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1403 break;
1404 case nir_intrinsic_image_deref_load:
1405 emit_intrinsic_load_image(ctx, intr, dst);
1406 break;
1407 case nir_intrinsic_image_deref_store:
1408 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1409 !ctx->s->info.fs.early_fragment_tests)
1410 ctx->so->no_earlyz = true;
1411 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1412 break;
1413 case nir_intrinsic_image_deref_size:
1414 emit_intrinsic_image_size(ctx, intr, dst);
1415 break;
1416 case nir_intrinsic_image_deref_atomic_add:
1417 case nir_intrinsic_image_deref_atomic_min:
1418 case nir_intrinsic_image_deref_atomic_max:
1419 case nir_intrinsic_image_deref_atomic_and:
1420 case nir_intrinsic_image_deref_atomic_or:
1421 case nir_intrinsic_image_deref_atomic_xor:
1422 case nir_intrinsic_image_deref_atomic_exchange:
1423 case nir_intrinsic_image_deref_atomic_comp_swap:
1424 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1425 !ctx->s->info.fs.early_fragment_tests)
1426 ctx->so->no_earlyz = true;
1427 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1428 break;
1429 case nir_intrinsic_barrier:
1430 case nir_intrinsic_memory_barrier:
1431 case nir_intrinsic_group_memory_barrier:
1432 case nir_intrinsic_memory_barrier_atomic_counter:
1433 case nir_intrinsic_memory_barrier_buffer:
1434 case nir_intrinsic_memory_barrier_image:
1435 case nir_intrinsic_memory_barrier_shared:
1436 emit_intrinsic_barrier(ctx, intr);
1437 /* note that blk ptr no longer valid, make that obvious: */
1438 b = NULL;
1439 break;
1440 case nir_intrinsic_store_output:
1441 idx = nir_intrinsic_base(intr);
1442 comp = nir_intrinsic_component(intr);
1443 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1444 idx += nir_src_as_uint(intr->src[1]);
1445
1446 src = ir3_get_src(ctx, &intr->src[0]);
1447 for (int i = 0; i < intr->num_components; i++) {
1448 unsigned n = idx * 4 + i + comp;
1449 ctx->ir->outputs[n] = src[i];
1450 }
1451 break;
1452 case nir_intrinsic_load_base_vertex:
1453 case nir_intrinsic_load_first_vertex:
1454 if (!ctx->basevertex) {
1455 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1456 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex);
1457 }
1458 dst[0] = ctx->basevertex;
1459 break;
1460 case nir_intrinsic_load_vertex_id_zero_base:
1461 case nir_intrinsic_load_vertex_id:
1462 if (!ctx->vertex_id) {
1463 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1464 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1465 ctx->vertex_id = create_input(ctx, 0);
1466 add_sysval_input(ctx, sv, ctx->vertex_id);
1467 }
1468 dst[0] = ctx->vertex_id;
1469 break;
1470 case nir_intrinsic_load_instance_id:
1471 if (!ctx->instance_id) {
1472 ctx->instance_id = create_input(ctx, 0);
1473 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID,
1474 ctx->instance_id);
1475 }
1476 dst[0] = ctx->instance_id;
1477 break;
1478 case nir_intrinsic_load_sample_id:
1479 ctx->so->per_samp = true;
1480 /* fall-thru */
1481 case nir_intrinsic_load_sample_id_no_per_sample:
1482 if (!ctx->samp_id) {
1483 ctx->samp_id = create_input(ctx, 0);
1484 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1485 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID,
1486 ctx->samp_id);
1487 }
1488 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1489 break;
1490 case nir_intrinsic_load_sample_mask_in:
1491 if (!ctx->samp_mask_in) {
1492 ctx->samp_mask_in = create_input(ctx, 0);
1493 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN,
1494 ctx->samp_mask_in);
1495 }
1496 dst[0] = ctx->samp_mask_in;
1497 break;
1498 case nir_intrinsic_load_user_clip_plane:
1499 idx = nir_intrinsic_ucp_id(intr);
1500 for (int i = 0; i < intr->num_components; i++) {
1501 unsigned n = idx * 4 + i;
1502 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1503 }
1504 break;
1505 case nir_intrinsic_load_front_face:
1506 if (!ctx->frag_face) {
1507 ctx->so->frag_face = true;
1508 ctx->frag_face = create_input(ctx, 0);
1509 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face);
1510 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1511 }
1512 /* for fragface, we get -1 for back and 0 for front. However this is
1513 * the inverse of what nir expects (where ~0 is true).
1514 */
1515 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1516 dst[0] = ir3_NOT_B(b, dst[0], 0);
1517 break;
1518 case nir_intrinsic_load_local_invocation_id:
1519 if (!ctx->local_invocation_id) {
1520 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7);
1521 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID,
1522 0x7, ctx->local_invocation_id);
1523 }
1524 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1525 break;
1526 case nir_intrinsic_load_work_group_id:
1527 if (!ctx->work_group_id) {
1528 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7);
1529 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID,
1530 0x7, ctx->work_group_id);
1531 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1532 }
1533 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1534 break;
1535 case nir_intrinsic_load_num_work_groups:
1536 for (int i = 0; i < intr->num_components; i++) {
1537 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1538 }
1539 break;
1540 case nir_intrinsic_load_local_group_size:
1541 for (int i = 0; i < intr->num_components; i++) {
1542 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1543 }
1544 break;
1545 case nir_intrinsic_discard_if:
1546 case nir_intrinsic_discard: {
1547 struct ir3_instruction *cond, *kill;
1548
1549 if (intr->intrinsic == nir_intrinsic_discard_if) {
1550 /* conditional discard: */
1551 src = ir3_get_src(ctx, &intr->src[0]);
1552 cond = ir3_b2n(b, src[0]);
1553 } else {
1554 /* unconditional discard: */
1555 cond = create_immed(b, 1);
1556 }
1557
1558 /* NOTE: only cmps.*.* can write p0.x: */
1559 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1560 cond->cat2.condition = IR3_COND_NE;
1561
1562 /* condition always goes in predicate register: */
1563 cond->regs[0]->num = regid(REG_P0, 0);
1564
1565 kill = ir3_KILL(b, cond, 0);
1566 array_insert(ctx->ir, ctx->ir->predicates, kill);
1567
1568 array_insert(b, b->keeps, kill);
1569 ctx->so->no_earlyz = true;
1570
1571 break;
1572 }
1573 default:
1574 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1575 nir_intrinsic_infos[intr->intrinsic].name);
1576 break;
1577 }
1578
1579 if (info->has_dest)
1580 ir3_put_dst(ctx, &intr->dest);
1581 }
1582
1583 static void
1584 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1585 {
1586 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1587 instr->def.num_components);
1588
1589 if (instr->def.bit_size < 32) {
1590 for (int i = 0; i < instr->def.num_components; i++)
1591 dst[i] = create_immed_typed(ctx->block,
1592 instr->value[i].u16,
1593 TYPE_U16);
1594 } else {
1595 for (int i = 0; i < instr->def.num_components; i++)
1596 dst[i] = create_immed_typed(ctx->block,
1597 instr->value[i].u32,
1598 TYPE_U32);
1599 }
1600
1601 }
1602
1603 static void
1604 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1605 {
1606 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1607 undef->def.num_components);
1608 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1609
1610 /* backend doesn't want undefined instructions, so just plug
1611 * in 0.0..
1612 */
1613 for (int i = 0; i < undef->def.num_components; i++)
1614 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1615 }
1616
1617 /*
1618 * texture fetch/sample instructions:
1619 */
1620
1621 static void
1622 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1623 {
1624 unsigned coords, flags = 0;
1625
1626 /* note: would use tex->coord_components.. except txs.. also,
1627 * since array index goes after shadow ref, we don't want to
1628 * count it:
1629 */
1630 switch (tex->sampler_dim) {
1631 case GLSL_SAMPLER_DIM_1D:
1632 case GLSL_SAMPLER_DIM_BUF:
1633 coords = 1;
1634 break;
1635 case GLSL_SAMPLER_DIM_2D:
1636 case GLSL_SAMPLER_DIM_RECT:
1637 case GLSL_SAMPLER_DIM_EXTERNAL:
1638 case GLSL_SAMPLER_DIM_MS:
1639 coords = 2;
1640 break;
1641 case GLSL_SAMPLER_DIM_3D:
1642 case GLSL_SAMPLER_DIM_CUBE:
1643 coords = 3;
1644 flags |= IR3_INSTR_3D;
1645 break;
1646 default:
1647 unreachable("bad sampler_dim");
1648 }
1649
1650 if (tex->is_shadow && tex->op != nir_texop_lod)
1651 flags |= IR3_INSTR_S;
1652
1653 if (tex->is_array && tex->op != nir_texop_lod)
1654 flags |= IR3_INSTR_A;
1655
1656 *flagsp = flags;
1657 *coordsp = coords;
1658 }
1659
1660 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1661 * or immediate (in which case it will get lowered later to a non .s2en
1662 * version of the tex instruction which encode tex/samp as immediates:
1663 */
1664 static struct ir3_instruction *
1665 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1666 {
1667 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1668 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1669 struct ir3_instruction *texture, *sampler;
1670
1671 if (texture_idx >= 0) {
1672 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1673 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1674 } else {
1675 /* TODO what to do for dynamic case? I guess we only need the
1676 * max index for astc srgb workaround so maybe not a problem
1677 * to worry about if we don't enable indirect samplers for
1678 * a4xx?
1679 */
1680 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1681 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1682 }
1683
1684 if (sampler_idx >= 0) {
1685 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1686 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1687 } else {
1688 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1689 }
1690
1691 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1692 sampler,
1693 texture,
1694 }, 2);
1695 }
1696
1697 static void
1698 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1699 {
1700 struct ir3_block *b = ctx->block;
1701 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1702 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1703 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1704 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1705 unsigned i, coords, flags, ncomp;
1706 unsigned nsrc0 = 0, nsrc1 = 0;
1707 type_t type;
1708 opc_t opc = 0;
1709
1710 ncomp = nir_dest_num_components(tex->dest);
1711
1712 coord = off = ddx = ddy = NULL;
1713 lod = proj = compare = sample_index = NULL;
1714
1715 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1716
1717 for (unsigned i = 0; i < tex->num_srcs; i++) {
1718 switch (tex->src[i].src_type) {
1719 case nir_tex_src_coord:
1720 coord = ir3_get_src(ctx, &tex->src[i].src);
1721 break;
1722 case nir_tex_src_bias:
1723 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1724 has_bias = true;
1725 break;
1726 case nir_tex_src_lod:
1727 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1728 has_lod = true;
1729 break;
1730 case nir_tex_src_comparator: /* shadow comparator */
1731 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1732 break;
1733 case nir_tex_src_projector:
1734 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1735 has_proj = true;
1736 break;
1737 case nir_tex_src_offset:
1738 off = ir3_get_src(ctx, &tex->src[i].src);
1739 has_off = true;
1740 break;
1741 case nir_tex_src_ddx:
1742 ddx = ir3_get_src(ctx, &tex->src[i].src);
1743 break;
1744 case nir_tex_src_ddy:
1745 ddy = ir3_get_src(ctx, &tex->src[i].src);
1746 break;
1747 case nir_tex_src_ms_index:
1748 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1749 break;
1750 case nir_tex_src_texture_offset:
1751 case nir_tex_src_sampler_offset:
1752 /* handled in get_tex_samp_src() */
1753 break;
1754 default:
1755 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1756 tex->src[i].src_type);
1757 return;
1758 }
1759 }
1760
1761 switch (tex->op) {
1762 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1763 case nir_texop_txb: opc = OPC_SAMB; break;
1764 case nir_texop_txl: opc = OPC_SAML; break;
1765 case nir_texop_txd: opc = OPC_SAMGQ; break;
1766 case nir_texop_txf: opc = OPC_ISAML; break;
1767 case nir_texop_lod: opc = OPC_GETLOD; break;
1768 case nir_texop_tg4:
1769 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1770 * what blob does, seems gather is broken?), and a3xx did
1771 * not support it (but probably could also emulate).
1772 */
1773 switch (tex->component) {
1774 case 0: opc = OPC_GATHER4R; break;
1775 case 1: opc = OPC_GATHER4G; break;
1776 case 2: opc = OPC_GATHER4B; break;
1777 case 3: opc = OPC_GATHER4A; break;
1778 }
1779 break;
1780 case nir_texop_txf_ms_fb:
1781 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
1782 default:
1783 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1784 return;
1785 }
1786
1787 tex_info(tex, &flags, &coords);
1788
1789 /*
1790 * lay out the first argument in the proper order:
1791 * - actual coordinates first
1792 * - shadow reference
1793 * - array index
1794 * - projection w
1795 * - starting at offset 4, dpdx.xy, dpdy.xy
1796 *
1797 * bias/lod go into the second arg
1798 */
1799
1800 /* insert tex coords: */
1801 for (i = 0; i < coords; i++)
1802 src0[i] = coord[i];
1803
1804 nsrc0 = i;
1805
1806 /* scale up integer coords for TXF based on the LOD */
1807 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
1808 assert(has_lod);
1809 for (i = 0; i < coords; i++)
1810 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
1811 }
1812
1813 if (coords == 1) {
1814 /* hw doesn't do 1d, so we treat it as 2d with
1815 * height of 1, and patch up the y coord.
1816 */
1817 if (is_isam(opc)) {
1818 src0[nsrc0++] = create_immed(b, 0);
1819 } else {
1820 src0[nsrc0++] = create_immed(b, fui(0.5));
1821 }
1822 }
1823
1824 if (tex->is_shadow && tex->op != nir_texop_lod)
1825 src0[nsrc0++] = compare;
1826
1827 if (tex->is_array && tex->op != nir_texop_lod) {
1828 struct ir3_instruction *idx = coord[coords];
1829
1830 /* the array coord for cube arrays needs 0.5 added to it */
1831 if (ctx->compiler->array_index_add_half && !is_isam(opc))
1832 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
1833
1834 src0[nsrc0++] = idx;
1835 }
1836
1837 if (has_proj) {
1838 src0[nsrc0++] = proj;
1839 flags |= IR3_INSTR_P;
1840 }
1841
1842 /* pad to 4, then ddx/ddy: */
1843 if (tex->op == nir_texop_txd) {
1844 while (nsrc0 < 4)
1845 src0[nsrc0++] = create_immed(b, fui(0.0));
1846 for (i = 0; i < coords; i++)
1847 src0[nsrc0++] = ddx[i];
1848 if (coords < 2)
1849 src0[nsrc0++] = create_immed(b, fui(0.0));
1850 for (i = 0; i < coords; i++)
1851 src0[nsrc0++] = ddy[i];
1852 if (coords < 2)
1853 src0[nsrc0++] = create_immed(b, fui(0.0));
1854 }
1855
1856 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1857 * with scaled x coord according to requested sample:
1858 */
1859 if (opc == OPC_ISAMM) {
1860 if (ctx->compiler->txf_ms_with_isaml) {
1861 /* the samples are laid out in x dimension as
1862 * 0 1 2 3
1863 * x_ms = (x << ms) + sample_index;
1864 */
1865 struct ir3_instruction *ms;
1866 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
1867
1868 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
1869 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
1870
1871 opc = OPC_ISAML;
1872 } else {
1873 src0[nsrc0++] = sample_index;
1874 }
1875 }
1876
1877 /*
1878 * second argument (if applicable):
1879 * - offsets
1880 * - lod
1881 * - bias
1882 */
1883 if (has_off | has_lod | has_bias) {
1884 if (has_off) {
1885 unsigned off_coords = coords;
1886 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
1887 off_coords--;
1888 for (i = 0; i < off_coords; i++)
1889 src1[nsrc1++] = off[i];
1890 if (off_coords < 2)
1891 src1[nsrc1++] = create_immed(b, fui(0.0));
1892 flags |= IR3_INSTR_O;
1893 }
1894
1895 if (has_lod | has_bias)
1896 src1[nsrc1++] = lod;
1897 }
1898
1899 switch (tex->dest_type) {
1900 case nir_type_invalid:
1901 case nir_type_float:
1902 type = TYPE_F32;
1903 break;
1904 case nir_type_int:
1905 type = TYPE_S32;
1906 break;
1907 case nir_type_uint:
1908 case nir_type_bool:
1909 type = TYPE_U32;
1910 break;
1911 default:
1912 unreachable("bad dest_type");
1913 }
1914
1915 if (opc == OPC_GETLOD)
1916 type = TYPE_U32;
1917
1918 struct ir3_instruction *samp_tex;
1919
1920 if (tex->op == nir_texop_txf_ms_fb) {
1921 /* only expect a single txf_ms_fb per shader: */
1922 compile_assert(ctx, !ctx->so->fb_read);
1923 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
1924
1925 ctx->so->fb_read = true;
1926 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1927 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
1928 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
1929 }, 2);
1930
1931 ctx->so->num_samp++;
1932 } else {
1933 samp_tex = get_tex_samp_tex_src(ctx, tex);
1934 }
1935
1936 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
1937 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
1938
1939 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
1940 samp_tex, col0, col1);
1941
1942 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
1943 /* only need first 3 components: */
1944 sam->regs[0]->wrmask = 0x7;
1945 ir3_split_dest(b, dst, sam, 0, 3);
1946
1947 /* we need to sample the alpha separately with a non-ASTC
1948 * texture state:
1949 */
1950 sam = ir3_SAM(b, opc, type, 0b1000, flags,
1951 samp_tex, col0, col1);
1952
1953 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
1954
1955 /* fixup .w component: */
1956 ir3_split_dest(b, &dst[3], sam, 3, 1);
1957 } else {
1958 /* normal (non-workaround) case: */
1959 ir3_split_dest(b, dst, sam, 0, ncomp);
1960 }
1961
1962 /* GETLOD returns results in 4.8 fixed point */
1963 if (opc == OPC_GETLOD) {
1964 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
1965
1966 compile_assert(ctx, tex->dest_type == nir_type_float);
1967 for (i = 0; i < 2; i++) {
1968 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_U32, TYPE_F32), 0,
1969 factor, 0);
1970 }
1971 }
1972
1973 ir3_put_dst(ctx, &tex->dest);
1974 }
1975
1976 static void
1977 emit_tex_query_levels(struct ir3_context *ctx, nir_tex_instr *tex)
1978 {
1979 struct ir3_block *b = ctx->block;
1980 struct ir3_instruction **dst, *sam;
1981
1982 dst = ir3_get_dst(ctx, &tex->dest, 1);
1983
1984 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 0b0100, 0,
1985 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
1986
1987 /* even though there is only one component, since it ends
1988 * up in .z rather than .x, we need a split_dest()
1989 */
1990 ir3_split_dest(b, dst, sam, 0, 3);
1991
1992 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1993 * the value in TEX_CONST_0 is zero-based.
1994 */
1995 if (ctx->compiler->levels_add_one)
1996 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
1997
1998 ir3_put_dst(ctx, &tex->dest);
1999 }
2000
2001 static void
2002 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2003 {
2004 struct ir3_block *b = ctx->block;
2005 struct ir3_instruction **dst, *sam;
2006 struct ir3_instruction *lod;
2007 unsigned flags, coords;
2008
2009 tex_info(tex, &flags, &coords);
2010
2011 /* Actually we want the number of dimensions, not coordinates. This
2012 * distinction only matters for cubes.
2013 */
2014 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2015 coords = 2;
2016
2017 dst = ir3_get_dst(ctx, &tex->dest, 4);
2018
2019 compile_assert(ctx, tex->num_srcs == 1);
2020 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2021
2022 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2023
2024 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
2025 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2026
2027 ir3_split_dest(b, dst, sam, 0, 4);
2028
2029 /* Array size actually ends up in .w rather than .z. This doesn't
2030 * matter for miplevel 0, but for higher mips the value in z is
2031 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2032 * returned, which means that we have to add 1 to it for arrays.
2033 */
2034 if (tex->is_array) {
2035 if (ctx->compiler->levels_add_one) {
2036 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2037 } else {
2038 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2039 }
2040 }
2041
2042 ir3_put_dst(ctx, &tex->dest);
2043 }
2044
2045 static void
2046 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2047 {
2048 switch (jump->type) {
2049 case nir_jump_break:
2050 case nir_jump_continue:
2051 case nir_jump_return:
2052 /* I *think* we can simply just ignore this, and use the
2053 * successor block link to figure out where we need to
2054 * jump to for break/continue
2055 */
2056 break;
2057 default:
2058 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2059 break;
2060 }
2061 }
2062
2063 static void
2064 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2065 {
2066 switch (instr->type) {
2067 case nir_instr_type_alu:
2068 emit_alu(ctx, nir_instr_as_alu(instr));
2069 break;
2070 case nir_instr_type_deref:
2071 /* ignored, handled as part of the intrinsic they are src to */
2072 break;
2073 case nir_instr_type_intrinsic:
2074 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2075 break;
2076 case nir_instr_type_load_const:
2077 emit_load_const(ctx, nir_instr_as_load_const(instr));
2078 break;
2079 case nir_instr_type_ssa_undef:
2080 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2081 break;
2082 case nir_instr_type_tex: {
2083 nir_tex_instr *tex = nir_instr_as_tex(instr);
2084 /* couple tex instructions get special-cased:
2085 */
2086 switch (tex->op) {
2087 case nir_texop_txs:
2088 emit_tex_txs(ctx, tex);
2089 break;
2090 case nir_texop_query_levels:
2091 emit_tex_query_levels(ctx, tex);
2092 break;
2093 default:
2094 emit_tex(ctx, tex);
2095 break;
2096 }
2097 break;
2098 }
2099 case nir_instr_type_jump:
2100 emit_jump(ctx, nir_instr_as_jump(instr));
2101 break;
2102 case nir_instr_type_phi:
2103 /* we have converted phi webs to regs in NIR by now */
2104 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2105 break;
2106 case nir_instr_type_call:
2107 case nir_instr_type_parallel_copy:
2108 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2109 break;
2110 }
2111 }
2112
2113 static struct ir3_block *
2114 get_block(struct ir3_context *ctx, const nir_block *nblock)
2115 {
2116 struct ir3_block *block;
2117 struct hash_entry *hentry;
2118 unsigned i;
2119
2120 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2121 if (hentry)
2122 return hentry->data;
2123
2124 block = ir3_block_create(ctx->ir);
2125 block->nblock = nblock;
2126 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2127
2128 block->predecessors_count = nblock->predecessors->entries;
2129 block->predecessors = ralloc_array_size(block,
2130 sizeof(block->predecessors[0]), block->predecessors_count);
2131 i = 0;
2132 set_foreach(nblock->predecessors, sentry) {
2133 block->predecessors[i++] = get_block(ctx, sentry->key);
2134 }
2135
2136 return block;
2137 }
2138
2139 static void
2140 emit_block(struct ir3_context *ctx, nir_block *nblock)
2141 {
2142 struct ir3_block *block = get_block(ctx, nblock);
2143
2144 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2145 if (nblock->successors[i]) {
2146 block->successors[i] =
2147 get_block(ctx, nblock->successors[i]);
2148 }
2149 }
2150
2151 ctx->block = block;
2152 list_addtail(&block->node, &ctx->ir->block_list);
2153
2154 /* re-emit addr register in each block if needed: */
2155 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2156 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2157 ctx->addr_ht[i] = NULL;
2158 }
2159
2160 nir_foreach_instr(instr, nblock) {
2161 ctx->cur_instr = instr;
2162 emit_instr(ctx, instr);
2163 ctx->cur_instr = NULL;
2164 if (ctx->error)
2165 return;
2166 }
2167 }
2168
2169 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2170
2171 static void
2172 emit_if(struct ir3_context *ctx, nir_if *nif)
2173 {
2174 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2175
2176 ctx->block->condition =
2177 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2178
2179 emit_cf_list(ctx, &nif->then_list);
2180 emit_cf_list(ctx, &nif->else_list);
2181 }
2182
2183 static void
2184 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2185 {
2186 emit_cf_list(ctx, &nloop->body);
2187 ctx->so->loops++;
2188 }
2189
2190 static void
2191 stack_push(struct ir3_context *ctx)
2192 {
2193 ctx->stack++;
2194 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2195 }
2196
2197 static void
2198 stack_pop(struct ir3_context *ctx)
2199 {
2200 compile_assert(ctx, ctx->stack > 0);
2201 ctx->stack--;
2202 }
2203
2204 static void
2205 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2206 {
2207 foreach_list_typed(nir_cf_node, node, node, list) {
2208 switch (node->type) {
2209 case nir_cf_node_block:
2210 emit_block(ctx, nir_cf_node_as_block(node));
2211 break;
2212 case nir_cf_node_if:
2213 stack_push(ctx);
2214 emit_if(ctx, nir_cf_node_as_if(node));
2215 stack_pop(ctx);
2216 break;
2217 case nir_cf_node_loop:
2218 stack_push(ctx);
2219 emit_loop(ctx, nir_cf_node_as_loop(node));
2220 stack_pop(ctx);
2221 break;
2222 case nir_cf_node_function:
2223 ir3_context_error(ctx, "TODO\n");
2224 break;
2225 }
2226 }
2227 }
2228
2229 /* emit stream-out code. At this point, the current block is the original
2230 * (nir) end block, and nir ensures that all flow control paths terminate
2231 * into the end block. We re-purpose the original end block to generate
2232 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2233 * block holding stream-out write instructions, followed by the new end
2234 * block:
2235 *
2236 * blockOrigEnd {
2237 * p0.x = (vtxcnt < maxvtxcnt)
2238 * // succs: blockStreamOut, blockNewEnd
2239 * }
2240 * blockStreamOut {
2241 * ... stream-out instructions ...
2242 * // succs: blockNewEnd
2243 * }
2244 * blockNewEnd {
2245 * }
2246 */
2247 static void
2248 emit_stream_out(struct ir3_context *ctx)
2249 {
2250 struct ir3 *ir = ctx->ir;
2251 struct ir3_stream_output_info *strmout =
2252 &ctx->so->shader->stream_output;
2253 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2254 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2255 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2256
2257 /* create vtxcnt input in input block at top of shader,
2258 * so that it is seen as live over the entire duration
2259 * of the shader:
2260 */
2261 vtxcnt = create_input(ctx, 0);
2262 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt);
2263
2264 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2265
2266 /* at this point, we are at the original 'end' block,
2267 * re-purpose this block to stream-out condition, then
2268 * append stream-out block and new-end block
2269 */
2270 orig_end_block = ctx->block;
2271
2272 // TODO these blocks need to update predecessors..
2273 // maybe w/ store_global intrinsic, we could do this
2274 // stuff in nir->nir pass
2275
2276 stream_out_block = ir3_block_create(ir);
2277 list_addtail(&stream_out_block->node, &ir->block_list);
2278
2279 new_end_block = ir3_block_create(ir);
2280 list_addtail(&new_end_block->node, &ir->block_list);
2281
2282 orig_end_block->successors[0] = stream_out_block;
2283 orig_end_block->successors[1] = new_end_block;
2284 stream_out_block->successors[0] = new_end_block;
2285
2286 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2287 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2288 cond->regs[0]->num = regid(REG_P0, 0);
2289 cond->cat2.condition = IR3_COND_LT;
2290
2291 /* condition goes on previous block to the conditional,
2292 * since it is used to pick which of the two successor
2293 * paths to take:
2294 */
2295 orig_end_block->condition = cond;
2296
2297 /* switch to stream_out_block to generate the stream-out
2298 * instructions:
2299 */
2300 ctx->block = stream_out_block;
2301
2302 /* Calculate base addresses based on vtxcnt. Instructions
2303 * generated for bases not used in following loop will be
2304 * stripped out in the backend.
2305 */
2306 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2307 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2308 unsigned stride = strmout->stride[i];
2309 struct ir3_instruction *base, *off;
2310
2311 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2312
2313 /* 24-bit should be enough: */
2314 off = ir3_MUL_U(ctx->block, vtxcnt, 0,
2315 create_immed(ctx->block, stride * 4), 0);
2316
2317 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2318 }
2319
2320 /* Generate the per-output store instructions: */
2321 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2322 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2323 unsigned c = j + strmout->output[i].start_component;
2324 struct ir3_instruction *base, *out, *stg;
2325
2326 base = bases[strmout->output[i].output_buffer];
2327 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2328
2329 stg = ir3_STG(ctx->block, base, 0, out, 0,
2330 create_immed(ctx->block, 1), 0);
2331 stg->cat6.type = TYPE_U32;
2332 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2333
2334 array_insert(ctx->block, ctx->block->keeps, stg);
2335 }
2336 }
2337
2338 /* and finally switch to the new_end_block: */
2339 ctx->block = new_end_block;
2340 }
2341
2342 static void
2343 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2344 {
2345 nir_metadata_require(impl, nir_metadata_block_index);
2346
2347 compile_assert(ctx, ctx->stack == 0);
2348
2349 emit_cf_list(ctx, &impl->body);
2350 emit_block(ctx, impl->end_block);
2351
2352 compile_assert(ctx, ctx->stack == 0);
2353
2354 /* at this point, we should have a single empty block,
2355 * into which we emit the 'end' instruction.
2356 */
2357 compile_assert(ctx, list_empty(&ctx->block->instr_list));
2358
2359 /* If stream-out (aka transform-feedback) enabled, emit the
2360 * stream-out instructions, followed by a new empty block (into
2361 * which the 'end' instruction lands).
2362 *
2363 * NOTE: it is done in this order, rather than inserting before
2364 * we emit end_block, because NIR guarantees that all blocks
2365 * flow into end_block, and that end_block has no successors.
2366 * So by re-purposing end_block as the first block of stream-
2367 * out, we guarantee that all exit paths flow into the stream-
2368 * out instructions.
2369 */
2370 if ((ctx->compiler->gpu_id < 500) &&
2371 (ctx->so->shader->stream_output.num_outputs > 0) &&
2372 !ctx->so->binning_pass) {
2373 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2374 emit_stream_out(ctx);
2375 }
2376
2377 ir3_END(ctx->block);
2378 }
2379
2380 static void
2381 setup_input(struct ir3_context *ctx, nir_variable *in)
2382 {
2383 struct ir3_shader_variant *so = ctx->so;
2384 unsigned ncomp = glsl_get_components(in->type);
2385 unsigned n = in->data.driver_location;
2386 unsigned frac = in->data.location_frac;
2387 unsigned slot = in->data.location;
2388
2389 /* skip unread inputs, we could end up with (for example), unsplit
2390 * matrix/etc inputs in the case they are not read, so just silently
2391 * skip these.
2392 */
2393 if (ncomp > 4)
2394 return;
2395
2396 so->inputs[n].slot = slot;
2397 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2398 so->inputs_count = MAX2(so->inputs_count, n + 1);
2399 so->inputs[n].interpolate = in->data.interpolation;
2400 so->inputs[n].ncomp = ncomp;
2401
2402 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2403
2404 /* if any varyings have 'sample' qualifer, that triggers us
2405 * to run in per-sample mode:
2406 */
2407 so->per_samp |= in->data.sample;
2408
2409 for (int i = 0; i < ncomp; i++) {
2410 struct ir3_instruction *instr = NULL;
2411 unsigned idx = (n * 4) + i + frac;
2412
2413 if (slot == VARYING_SLOT_POS) {
2414 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2415 } else if (slot == VARYING_SLOT_PNTC) {
2416 /* see for example st_nir_fixup_varying_slots().. this is
2417 * maybe a bit mesa/st specific. But we need things to line
2418 * up for this in fdN_program:
2419 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2420 * if (emit->sprite_coord_enable & texmask) {
2421 * ...
2422 * }
2423 */
2424 so->inputs[n].slot = VARYING_SLOT_VAR8;
2425 so->inputs[n].bary = true;
2426 instr = create_frag_input(ctx, false, idx);
2427 } else {
2428 /* detect the special case for front/back colors where
2429 * we need to do flat vs smooth shading depending on
2430 * rast state:
2431 */
2432 if (in->data.interpolation == INTERP_MODE_NONE) {
2433 switch (slot) {
2434 case VARYING_SLOT_COL0:
2435 case VARYING_SLOT_COL1:
2436 case VARYING_SLOT_BFC0:
2437 case VARYING_SLOT_BFC1:
2438 so->inputs[n].rasterflat = true;
2439 break;
2440 default:
2441 break;
2442 }
2443 }
2444
2445 if (ctx->compiler->flat_bypass) {
2446 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2447 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2448 so->inputs[n].use_ldlv = true;
2449 }
2450
2451 so->inputs[n].bary = true;
2452
2453 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2454 }
2455
2456 compile_assert(ctx, idx < ctx->ir->ninputs);
2457
2458 ctx->ir->inputs[idx] = instr;
2459 }
2460 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2461 for (int i = 0; i < ncomp; i++) {
2462 unsigned idx = (n * 4) + i + frac;
2463 compile_assert(ctx, idx < ctx->ir->ninputs);
2464 ctx->ir->inputs[idx] = create_input(ctx, idx);
2465 }
2466 } else {
2467 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2468 }
2469
2470 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2471 so->total_in += ncomp;
2472 }
2473 }
2474
2475 /* Initially we assign non-packed inloc's for varyings, as we don't really
2476 * know up-front which components will be unused. After all the compilation
2477 * stages we scan the shader to see which components are actually used, and
2478 * re-pack the inlocs to eliminate unneeded varyings.
2479 */
2480 static void
2481 pack_inlocs(struct ir3_context *ctx)
2482 {
2483 struct ir3_shader_variant *so = ctx->so;
2484 uint8_t used_components[so->inputs_count];
2485
2486 memset(used_components, 0, sizeof(used_components));
2487
2488 /*
2489 * First Step: scan shader to find which bary.f/ldlv remain:
2490 */
2491
2492 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2493 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2494 if (is_input(instr)) {
2495 unsigned inloc = instr->regs[1]->iim_val;
2496 unsigned i = inloc / 4;
2497 unsigned j = inloc % 4;
2498
2499 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2500 compile_assert(ctx, i < so->inputs_count);
2501
2502 used_components[i] |= 1 << j;
2503 }
2504 }
2505 }
2506
2507 /*
2508 * Second Step: reassign varying inloc/slots:
2509 */
2510
2511 unsigned actual_in = 0;
2512 unsigned inloc = 0;
2513
2514 for (unsigned i = 0; i < so->inputs_count; i++) {
2515 unsigned compmask = 0, maxcomp = 0;
2516
2517 so->inputs[i].ncomp = 0;
2518 so->inputs[i].inloc = inloc;
2519 so->inputs[i].bary = false;
2520
2521 for (unsigned j = 0; j < 4; j++) {
2522 if (!(used_components[i] & (1 << j)))
2523 continue;
2524
2525 compmask |= (1 << j);
2526 actual_in++;
2527 so->inputs[i].ncomp++;
2528 maxcomp = j + 1;
2529
2530 /* at this point, since used_components[i] mask is only
2531 * considering varyings (ie. not sysvals) we know this
2532 * is a varying:
2533 */
2534 so->inputs[i].bary = true;
2535 }
2536
2537 if (so->inputs[i].bary) {
2538 so->varying_in++;
2539 so->inputs[i].compmask = (1 << maxcomp) - 1;
2540 inloc += maxcomp;
2541 }
2542 }
2543
2544 /*
2545 * Third Step: reassign packed inloc's:
2546 */
2547
2548 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2549 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2550 if (is_input(instr)) {
2551 unsigned inloc = instr->regs[1]->iim_val;
2552 unsigned i = inloc / 4;
2553 unsigned j = inloc % 4;
2554
2555 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2556 }
2557 }
2558 }
2559 }
2560
2561 static void
2562 setup_output(struct ir3_context *ctx, nir_variable *out)
2563 {
2564 struct ir3_shader_variant *so = ctx->so;
2565 unsigned ncomp = glsl_get_components(out->type);
2566 unsigned n = out->data.driver_location;
2567 unsigned frac = out->data.location_frac;
2568 unsigned slot = out->data.location;
2569 unsigned comp = 0;
2570
2571 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2572 switch (slot) {
2573 case FRAG_RESULT_DEPTH:
2574 comp = 2; /* tgsi will write to .z component */
2575 so->writes_pos = true;
2576 break;
2577 case FRAG_RESULT_COLOR:
2578 so->color0_mrt = 1;
2579 break;
2580 case FRAG_RESULT_SAMPLE_MASK:
2581 so->writes_smask = true;
2582 break;
2583 default:
2584 if (slot >= FRAG_RESULT_DATA0)
2585 break;
2586 ir3_context_error(ctx, "unknown FS output name: %s\n",
2587 gl_frag_result_name(slot));
2588 }
2589 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2590 switch (slot) {
2591 case VARYING_SLOT_POS:
2592 so->writes_pos = true;
2593 break;
2594 case VARYING_SLOT_PSIZ:
2595 so->writes_psize = true;
2596 break;
2597 case VARYING_SLOT_COL0:
2598 case VARYING_SLOT_COL1:
2599 case VARYING_SLOT_BFC0:
2600 case VARYING_SLOT_BFC1:
2601 case VARYING_SLOT_FOGC:
2602 case VARYING_SLOT_CLIP_DIST0:
2603 case VARYING_SLOT_CLIP_DIST1:
2604 case VARYING_SLOT_CLIP_VERTEX:
2605 break;
2606 default:
2607 if (slot >= VARYING_SLOT_VAR0)
2608 break;
2609 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2610 break;
2611 ir3_context_error(ctx, "unknown VS output name: %s\n",
2612 gl_varying_slot_name(slot));
2613 }
2614 } else {
2615 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2616 }
2617
2618 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2619
2620 so->outputs[n].slot = slot;
2621 so->outputs[n].regid = regid(n, comp);
2622 so->outputs_count = MAX2(so->outputs_count, n + 1);
2623
2624 for (int i = 0; i < ncomp; i++) {
2625 unsigned idx = (n * 4) + i + frac;
2626 compile_assert(ctx, idx < ctx->ir->noutputs);
2627 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2628 }
2629
2630 /* if varying packing doesn't happen, we could end up in a situation
2631 * with "holes" in the output, and since the per-generation code that
2632 * sets up varying linkage registers doesn't expect to have more than
2633 * one varying per vec4 slot, pad the holes.
2634 *
2635 * Note that this should probably generate a performance warning of
2636 * some sort.
2637 */
2638 for (int i = 0; i < frac; i++) {
2639 unsigned idx = (n * 4) + i;
2640 if (!ctx->ir->outputs[idx]) {
2641 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2642 }
2643 }
2644 }
2645
2646 static int
2647 max_drvloc(struct exec_list *vars)
2648 {
2649 int drvloc = -1;
2650 nir_foreach_variable(var, vars) {
2651 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2652 }
2653 return drvloc;
2654 }
2655
2656 static const unsigned max_sysvals[] = {
2657 [MESA_SHADER_FRAGMENT] = 24, // TODO
2658 [MESA_SHADER_VERTEX] = 16,
2659 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2660 [MESA_SHADER_KERNEL] = 16, // TODO how many do we actually need?
2661 };
2662
2663 static void
2664 emit_instructions(struct ir3_context *ctx)
2665 {
2666 unsigned ninputs, noutputs;
2667 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2668
2669 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2670 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2671
2672 /* we need to leave room for sysvals:
2673 */
2674 ninputs += max_sysvals[ctx->so->type];
2675
2676 ctx->ir = ir3_create(ctx->compiler, ctx->so->type, ninputs, noutputs);
2677
2678 /* Create inputs in first block: */
2679 ctx->block = get_block(ctx, nir_start_block(fxn));
2680 ctx->in_block = ctx->block;
2681 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2682
2683 ninputs -= max_sysvals[ctx->so->type];
2684
2685 /* for fragment shader, the vcoord input register is used as the
2686 * base for bary.f varying fetch instrs:
2687 *
2688 * TODO defer creating ctx->ij_pixel and corresponding sysvals
2689 * until emit_intrinsic when we know they are actually needed.
2690 * For now, we defer creating ctx->ij_centroid, etc, since we
2691 * only need ij_pixel for "old style" varying inputs (ie.
2692 * tgsi_to_nir)
2693 */
2694 struct ir3_instruction *vcoord = NULL;
2695 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2696 struct ir3_instruction *xy[2];
2697
2698 vcoord = create_input_compmask(ctx, 0, 0x3);
2699 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2700
2701 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
2702 }
2703
2704 /* Setup inputs: */
2705 nir_foreach_variable(var, &ctx->s->inputs) {
2706 setup_input(ctx, var);
2707 }
2708
2709 /* Defer add_sysval_input() stuff until after setup_inputs(),
2710 * because sysvals need to be appended after varyings:
2711 */
2712 if (vcoord) {
2713 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL,
2714 0x3, vcoord);
2715 }
2716
2717 /* Setup outputs: */
2718 nir_foreach_variable(var, &ctx->s->outputs) {
2719 setup_output(ctx, var);
2720 }
2721
2722 /* Find # of samplers: */
2723 nir_foreach_variable(var, &ctx->s->uniforms) {
2724 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
2725 /* just assume that we'll be reading from images.. if it
2726 * is write-only we don't have to count it, but not sure
2727 * if there is a good way to know?
2728 */
2729 ctx->so->num_samp += glsl_type_get_image_count(var->type);
2730 }
2731
2732 /* NOTE: need to do something more clever when we support >1 fxn */
2733 nir_foreach_register(reg, &fxn->registers) {
2734 ir3_declare_array(ctx, reg);
2735 }
2736 /* And emit the body: */
2737 ctx->impl = fxn;
2738 emit_function(ctx, fxn);
2739 }
2740
2741 /* from NIR perspective, we actually have varying inputs. But the varying
2742 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2743 * only actual inputs are the sysvals.
2744 */
2745 static void
2746 fixup_frag_inputs(struct ir3_context *ctx)
2747 {
2748 struct ir3_shader_variant *so = ctx->so;
2749 struct ir3 *ir = ctx->ir;
2750 unsigned i = 0;
2751
2752 /* sysvals should appear at the end of the inputs, drop everything else: */
2753 while ((i < so->inputs_count) && !so->inputs[i].sysval)
2754 i++;
2755
2756 /* at IR level, inputs are always blocks of 4 scalars: */
2757 i *= 4;
2758
2759 ir->inputs = &ir->inputs[i];
2760 ir->ninputs -= i;
2761 }
2762
2763 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2764 * need to assign the tex state indexes for these after we know the
2765 * max tex index.
2766 */
2767 static void
2768 fixup_astc_srgb(struct ir3_context *ctx)
2769 {
2770 struct ir3_shader_variant *so = ctx->so;
2771 /* indexed by original tex idx, value is newly assigned alpha sampler
2772 * state tex idx. Zero is invalid since there is at least one sampler
2773 * if we get here.
2774 */
2775 unsigned alt_tex_state[16] = {0};
2776 unsigned tex_idx = ctx->max_texture_index + 1;
2777 unsigned idx = 0;
2778
2779 so->astc_srgb.base = tex_idx;
2780
2781 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
2782 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
2783
2784 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
2785
2786 if (alt_tex_state[sam->cat5.tex] == 0) {
2787 /* assign new alternate/alpha tex state slot: */
2788 alt_tex_state[sam->cat5.tex] = tex_idx++;
2789 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
2790 so->astc_srgb.count++;
2791 }
2792
2793 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
2794 }
2795 }
2796
2797 static void
2798 fixup_binning_pass(struct ir3_context *ctx)
2799 {
2800 struct ir3_shader_variant *so = ctx->so;
2801 struct ir3 *ir = ctx->ir;
2802 unsigned i, j;
2803
2804 for (i = 0, j = 0; i < so->outputs_count; i++) {
2805 unsigned slot = so->outputs[i].slot;
2806
2807 /* throw away everything but first position/psize */
2808 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
2809 if (i != j) {
2810 so->outputs[j] = so->outputs[i];
2811 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
2812 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
2813 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
2814 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
2815 }
2816 j++;
2817 }
2818 }
2819 so->outputs_count = j;
2820 ir->noutputs = j * 4;
2821 }
2822
2823 int
2824 ir3_compile_shader_nir(struct ir3_compiler *compiler,
2825 struct ir3_shader_variant *so)
2826 {
2827 struct ir3_context *ctx;
2828 struct ir3 *ir;
2829 struct ir3_instruction **inputs;
2830 unsigned i;
2831 int ret = 0, max_bary;
2832
2833 assert(!so->ir);
2834
2835 ctx = ir3_context_init(compiler, so);
2836 if (!ctx) {
2837 DBG("INIT failed!");
2838 ret = -1;
2839 goto out;
2840 }
2841
2842 emit_instructions(ctx);
2843
2844 if (ctx->error) {
2845 DBG("EMIT failed!");
2846 ret = -1;
2847 goto out;
2848 }
2849
2850 ir = so->ir = ctx->ir;
2851
2852 /* keep track of the inputs from TGSI perspective.. */
2853 inputs = ir->inputs;
2854
2855 /* but fixup actual inputs for frag shader: */
2856 if (so->type == MESA_SHADER_FRAGMENT)
2857 fixup_frag_inputs(ctx);
2858
2859 /* at this point, for binning pass, throw away unneeded outputs: */
2860 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
2861 fixup_binning_pass(ctx);
2862
2863 /* if we want half-precision outputs, mark the output registers
2864 * as half:
2865 */
2866 if (so->key.half_precision) {
2867 for (i = 0; i < ir->noutputs; i++) {
2868 struct ir3_instruction *out = ir->outputs[i];
2869
2870 if (!out)
2871 continue;
2872
2873 /* if frag shader writes z, that needs to be full precision: */
2874 if (so->outputs[i/4].slot == FRAG_RESULT_DEPTH)
2875 continue;
2876
2877 out->regs[0]->flags |= IR3_REG_HALF;
2878 /* output could be a fanout (ie. texture fetch output)
2879 * in which case we need to propagate the half-reg flag
2880 * up to the definer so that RA sees it:
2881 */
2882 if (out->opc == OPC_META_FO) {
2883 out = out->regs[1]->instr;
2884 out->regs[0]->flags |= IR3_REG_HALF;
2885 }
2886
2887 if (out->opc == OPC_MOV) {
2888 out->cat1.dst_type = half_type(out->cat1.dst_type);
2889 }
2890 }
2891 }
2892
2893 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2894 printf("BEFORE CP:\n");
2895 ir3_print(ir);
2896 }
2897
2898 ir3_cp(ir, so);
2899
2900 /* at this point, for binning pass, throw away unneeded outputs:
2901 * Note that for a6xx and later, we do this after ir3_cp to ensure
2902 * that the uniform/constant layout for BS and VS matches, so that
2903 * we can re-use same VS_CONST state group.
2904 */
2905 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
2906 fixup_binning_pass(ctx);
2907
2908 /* Insert mov if there's same instruction for each output.
2909 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
2910 */
2911 for (int i = ir->noutputs - 1; i >= 0; i--) {
2912 if (!ir->outputs[i])
2913 continue;
2914 for (unsigned j = 0; j < i; j++) {
2915 if (ir->outputs[i] == ir->outputs[j]) {
2916 ir->outputs[i] =
2917 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
2918 }
2919 }
2920 }
2921
2922 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2923 printf("BEFORE GROUPING:\n");
2924 ir3_print(ir);
2925 }
2926
2927 ir3_sched_add_deps(ir);
2928
2929 /* Group left/right neighbors, inserting mov's where needed to
2930 * solve conflicts:
2931 */
2932 ir3_group(ir);
2933
2934 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2935 printf("AFTER GROUPING:\n");
2936 ir3_print(ir);
2937 }
2938
2939 ir3_depth(ir);
2940
2941 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2942 printf("AFTER DEPTH:\n");
2943 ir3_print(ir);
2944 }
2945
2946 /* do Sethi–Ullman numbering before scheduling: */
2947 ir3_sun(ir);
2948
2949 ret = ir3_sched(ir);
2950 if (ret) {
2951 DBG("SCHED failed!");
2952 goto out;
2953 }
2954
2955 if (compiler->gpu_id >= 600) {
2956 ir3_a6xx_fixup_atomic_dests(ir, so);
2957 }
2958
2959 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2960 printf("AFTER SCHED:\n");
2961 ir3_print(ir);
2962 }
2963
2964 ret = ir3_ra(ir, so->type, so->frag_coord, so->frag_face);
2965 if (ret) {
2966 DBG("RA failed!");
2967 goto out;
2968 }
2969
2970 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2971 printf("AFTER RA:\n");
2972 ir3_print(ir);
2973 }
2974
2975 if (so->type == MESA_SHADER_FRAGMENT)
2976 pack_inlocs(ctx);
2977
2978 /* fixup input/outputs: */
2979 for (i = 0; i < so->outputs_count; i++) {
2980 /* sometimes we get outputs that don't write the .x coord, like:
2981 *
2982 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
2983 *
2984 * Presumably the result of varying packing and then eliminating
2985 * some unneeded varyings? Just skip head to the first valid
2986 * component of the output.
2987 */
2988 for (unsigned j = 0; j < 4; j++) {
2989 struct ir3_instruction *instr = ir->outputs[(i*4) + j];
2990 if (instr) {
2991 so->outputs[i].regid = instr->regs[0]->num;
2992 so->outputs[i].half = !!(instr->regs[0]->flags & IR3_REG_HALF);
2993 break;
2994 }
2995 }
2996 }
2997
2998 /* Note that some or all channels of an input may be unused: */
2999 for (i = 0; i < so->inputs_count; i++) {
3000 unsigned j, reg = regid(63,0);
3001 bool half = false;
3002 for (j = 0; j < 4; j++) {
3003 struct ir3_instruction *in = inputs[(i*4) + j];
3004
3005 if (in && !(in->flags & IR3_INSTR_UNUSED)) {
3006 reg = in->regs[0]->num - j;
3007 if (half) {
3008 compile_assert(ctx, in->regs[0]->flags & IR3_REG_HALF);
3009 } else {
3010 half = !!(in->regs[0]->flags & IR3_REG_HALF);
3011 }
3012 }
3013 }
3014 so->inputs[i].regid = reg;
3015 so->inputs[i].half = half;
3016 }
3017
3018 if (ctx->astc_srgb)
3019 fixup_astc_srgb(ctx);
3020
3021 /* We need to do legalize after (for frag shader's) the "bary.f"
3022 * offsets (inloc) have been assigned.
3023 */
3024 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
3025
3026 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3027 printf("AFTER LEGALIZE:\n");
3028 ir3_print(ir);
3029 }
3030
3031 so->branchstack = ctx->max_stack;
3032
3033 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3034 if (so->type == MESA_SHADER_FRAGMENT)
3035 so->total_in = max_bary + 1;
3036
3037 so->max_sun = ir->max_sun;
3038
3039 out:
3040 if (ret) {
3041 if (so->ir)
3042 ir3_destroy(so->ir);
3043 so->ir = NULL;
3044 }
3045 ir3_context_free(ctx);
3046
3047 return ret;
3048 }